diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/quick/se/02.insttest | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/02.insttest')
12 files changed, 1688 insertions, 1658 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 7685aa1bd..4fcd776f1 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +139,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -715,7 +716,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -724,14 +725,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 7b48b6ce0..d5dd8e395 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:44:12 -gem5 started Nov 29 2016 18:44:33 -gem5 executing on zizzer, pid 58827 -command line: /z/powerjg/gem5-upstream/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:39 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64867 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -21,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 29908500 because target called exit() +Exiting @ tick 29673500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index d8bf75e3e..c16641d08 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,990 +1,990 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29673500 # Number of ticks simulated -final_tick 29673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97740 # Simulator instruction rate (inst/s) -host_op_rate 97731 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 200871294 # Simulator tick rate (ticks/s) -host_mem_usage 251556 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -sim_insts 14436 # Number of instructions simulated -sim_ops 14436 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 32640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 782920788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317050567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1099971355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 782920788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 782920788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 782920788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317050567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1099971355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 511 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 104 # Per bank write bursts -system.physmem.perBankRdBursts::1 28 # Per bank write bursts -system.physmem.perBankRdBursts::2 54 # Per bank write bursts -system.physmem.perBankRdBursts::3 28 # Per bank write bursts -system.physmem.perBankRdBursts::4 22 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 38 # Per bank write bursts -system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 4 # Per bank write bursts -system.physmem.perBankRdBursts::10 2 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 57 # Per bank write bursts -system.physmem.perBankRdBursts::13 31 # Per bank write bursts -system.physmem.perBankRdBursts::14 63 # Per bank write bursts -system.physmem.perBankRdBursts::15 41 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29642000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 511 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 393.025641 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 252.718123 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.605052 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 23.08% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14 17.95% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.13% 67.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 8.97% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation -system.physmem.totQLat 6610250 # Total ticks spent queuing -system.physmem.totMemAccLat 16191500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12935.91 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31685.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1102.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1102.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.61 # Data bus utilization in percentage -system.physmem.busUtilRead 8.61 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 422 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 58007.83 # Average gap between requests -system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 364140 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2184840 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3606960 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 9847320 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 18086550 # Total energy per rank (pJ) -system.physmem_0.averagePower 609.513459 # Core power per rank (mW) -system.physmem_0.totalIdleTime 21469250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states -system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7251250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 21598000 # Time in different power states -system.physmem_1.actEnergy 271320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2504580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 86400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10184760 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 622560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17098680 # Total energy per rank (pJ) -system.physmem_1.averagePower 576.222419 # Core power per rank (mW) -system.physmem_1.totalIdleTime 23952750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states -system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1619750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4797750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22333000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11901 # Number of BP lookups -system.cpu.branchPred.condPredicted 7287 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1354 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9352 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 685 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9352 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1949 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7403 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 793 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 29673500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 59348 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15163 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 55604 # Number of instructions fetch has processed -system.cpu.fetch.Branches 11901 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2634 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17364 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2905 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 12 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1168 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7191 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 701 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 35180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.580557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.839184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22867 65.00% 65.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4490 12.76% 77.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 508 1.44% 79.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 450 1.28% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.16% 82.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 731 2.08% 84.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 296 0.84% 85.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 343 0.97% 86.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4734 13.46% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.200529 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.936914 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12094 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13233 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7639 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 762 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1452 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 39805 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1452 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12828 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9904 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7640 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1543 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 35279 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 30611 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 63420 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 52396 # Number of integer rename lookups -system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16792 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 761 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 767 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4154 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 4391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 27854 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 724 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 24627 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14142 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10452 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.700028 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.493682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26218 74.53% 74.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3125 8.88% 83.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1567 4.45% 87.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1507 4.28% 92.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1190 3.38% 95.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 757 2.15% 97.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 486 1.38% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 254 0.72% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 76 0.22% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35180 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 151 52.07% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51 17.59% 69.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88 30.34% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18085 73.44% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4096 16.63% 90.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2446 9.93% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 24627 # Type of FU issued -system.cpu.iq.rate 0.414959 # Inst issue rate -system.cpu.iq.fu_busy_cnt 290 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011776 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 84846 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 42748 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22066 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 24917 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2166 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1355 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1452 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1841 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 30085 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 231 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 724 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 209 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23080 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3816 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1547 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1507 # number of nop insts executed -system.cpu.iew.exec_refs 6070 # number of memory reference insts executed -system.cpu.iew.exec_branches 4884 # Number of branches executed -system.cpu.iew.exec_stores 2254 # Number of stores executed -system.cpu.iew.exec_rate 0.388893 # Inst execution rate -system.cpu.iew.wb_sent 22529 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22066 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10367 # num instructions producing a value -system.cpu.iew.wb_consumers 13651 # num instructions consuming a value -system.cpu.iew.wb_rate 0.371807 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.759432 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14855 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1354 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32262 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.469965 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.260994 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25609 79.38% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3577 11.09% 90.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1157 3.59% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 603 1.87% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 332 1.03% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 298 0.92% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 393 1.22% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 58 0.18% 99.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 235 0.73% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32262 # Number of insts commited each cycle -system.cpu.commit.committedInsts 15162 # Number of instructions committed -system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 3673 # Number of memory references committed -system.cpu.commit.loads 2225 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 3358 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 12174 # Number of committed integer instructions. -system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 235 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 61221 # The number of ROB reads -system.cpu.rob.rob_writes 63021 # The number of ROB writes -system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24168 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 14436 # Number of Instructions Simulated -system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 4.111111 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.111111 # CPI: Total CPI of All Threads -system.cpu.ipc 0.243243 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.243243 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36173 # number of integer regfile reads -system.cpu.int_regfile_writes 20126 # number of integer regfile writes -system.cpu.misc_regfile_reads 7956 # number of misc regfile reads -system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.931439 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4528 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.013699 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.931439 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024153 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024153 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10292 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10292 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3489 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3489 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4522 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4522 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4522 # number of overall hits -system.cpu.dcache.overall_hits::total 4522 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 545 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 545 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 545 # number of overall misses -system.cpu.dcache.overall_misses::total 545 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10734500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10734500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29028485 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29028485 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39762985 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39762985 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39762985 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39762985 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5067 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5067 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5067 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5067 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037517 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037517 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.107559 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.107559 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.107559 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.107559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78930.147059 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78930.147059 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70974.290954 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70974.290954 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72959.605505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72959.605505 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 397 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 397 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 397 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 397 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6906500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6906500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12986500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12986500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12986500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12986500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017931 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017931 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93538.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93538.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83210.843373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83210.843373 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 202.053622 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6606 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.098630 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 202.053622 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.098659 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.098659 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 14747 # Number of tag accesses -system.cpu.icache.tags.data_accesses 14747 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6606 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6606 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6606 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6606 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6606 # number of overall hits -system.cpu.icache.overall_hits::total 6606 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 585 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 585 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 585 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 585 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 585 # number of overall misses -system.cpu.icache.overall_misses::total 585 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45161000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45161000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45161000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45161000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7191 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7191 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7191 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7191 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081352 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081352 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081352 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081352 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081352 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77198.290598 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77198.290598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77198.290598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77198.290598 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 220 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 220 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 220 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 220 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29981500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29981500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29981500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29981500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29981500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29981500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050758 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050758 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050758 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82141.095890 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82141.095890 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 300.398022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 201.414921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 98.983101 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006147 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003021 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.009167 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses -system.cpu.l2cache.overall_misses::total 511 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6781000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6781000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29411000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29411000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5985000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5985000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29411000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12766000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 42177000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 29411000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12766000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 42177000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81698.795181 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81698.795181 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81022.038567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81022.038567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92076.923077 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92076.923077 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82538.160470 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82538.160470 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5951000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5951000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25781000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25781000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5355000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5355000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25781000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11306000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37087000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25781000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11306000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37087000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71698.795181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71698.795181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71022.038567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71022.038567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426 # Transaction distribution -system.membus.trans_dist::ReadExReq 83 # Transaction distribution -system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 511 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 511 # Request fanout histogram -system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2697250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.1 # Layer utilization (%) +sim_seconds 0.000030 +sim_ticks 29673500 +final_tick 29673500 +sim_freq 1000000000000 +host_inst_rate 61209 +host_op_rate 61203 +host_tick_rate 125793033 +host_mem_usage 263540 +host_seconds 0.24 +sim_insts 14436 +sim_ops 14436 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 +system.physmem.bytes_read::cpu.inst 23232 +system.physmem.bytes_read::cpu.data 9408 +system.physmem.bytes_read::total 32640 +system.physmem.bytes_inst_read::cpu.inst 23232 +system.physmem.bytes_inst_read::total 23232 +system.physmem.num_reads::cpu.inst 363 +system.physmem.num_reads::cpu.data 147 +system.physmem.num_reads::total 510 +system.physmem.bw_read::cpu.inst 782920788 +system.physmem.bw_read::cpu.data 317050567 +system.physmem.bw_read::total 1099971355 +system.physmem.bw_inst_read::cpu.inst 782920788 +system.physmem.bw_inst_read::total 782920788 +system.physmem.bw_total::cpu.inst 782920788 +system.physmem.bw_total::cpu.data 317050567 +system.physmem.bw_total::total 1099971355 +system.physmem.readReqs 511 +system.physmem.writeReqs 0 +system.physmem.readBursts 511 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 32704 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 32704 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 104 +system.physmem.perBankRdBursts::1 28 +system.physmem.perBankRdBursts::2 54 +system.physmem.perBankRdBursts::3 28 +system.physmem.perBankRdBursts::4 22 +system.physmem.perBankRdBursts::5 0 +system.physmem.perBankRdBursts::6 32 +system.physmem.perBankRdBursts::7 38 +system.physmem.perBankRdBursts::8 7 +system.physmem.perBankRdBursts::9 4 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511 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5951000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5951000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25781000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25781000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5355000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5355000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25781000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11306000 +system.cpu.l2cache.demand_mshr_miss_latency::total 37087000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25781000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11306000 +system.cpu.l2cache.overall_mshr_miss_latency::total 37087000 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71698.795181 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71698.795181 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71022.038567 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71022.038567 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82384.615385 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82384.615385 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71022.038567 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76391.891892 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72577.299413 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71022.038567 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76391.891892 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72577.299413 +system.cpu.toL2Bus.snoop_filter.tot_requests 513 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29673500 +system.cpu.toL2Bus.trans_dist::ReadResp 428 +system.cpu.toL2Bus.trans_dist::ReadExReq 83 +system.cpu.toL2Bus.trans_dist::ReadExResp 83 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 +system.cpu.toL2Bus.pkt_count::total 1024 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 +system.cpu.toL2Bus.pkt_size::total 32704 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 513 +system.cpu.toL2Bus.snoop_fanout::mean 0.003899 +system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% +system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 513 +system.cpu.toL2Bus.reqLayer0.occupancy 256500 +system.cpu.toL2Bus.reqLayer0.utilization 0.9 +system.cpu.toL2Bus.respLayer0.occupancy 547500 +system.cpu.toL2Bus.respLayer0.utilization 1.8 +system.cpu.toL2Bus.respLayer1.occupancy 219000 +system.cpu.toL2Bus.respLayer1.utilization 0.7 +system.membus.snoop_filter.tot_requests 511 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 29673500 +system.membus.trans_dist::ReadResp 426 +system.membus.trans_dist::ReadExReq 83 +system.membus.trans_dist::ReadExResp 83 +system.membus.trans_dist::ReadSharedReq 428 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 +system.membus.pkt_count::total 1020 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 +system.membus.pkt_size::total 32576 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 511 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 511 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 511 +system.membus.reqLayer0.occupancy 623500 +system.membus.reqLayer0.utilization 2.1 +system.membus.respLayer1.occupancy 2697250 +system.membus.respLayer1.utilization 9.1 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 28ad26872..297f86454 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index da1b76716..bf2b3f4bd 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38677 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:41 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64897 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -21,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 7612000 because target called exit() +Exiting @ tick 7612000 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 008914f75..322c3c70b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 7612000 # Number of ticks simulated -final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 446852 # Simulator instruction rate (inst/s) -host_op_rate 446721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 224213840 # Simulator tick rate (ticks/s) -host_mem_usage 239476 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 15162 # Number of instructions simulated -sim_ops 15162 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory -system.physmem.bytes_read::total 72170 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory -system.physmem.bytes_written::total 9042 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 17432 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory -system.physmem.num_other::total 6 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7991066737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1490015765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9481082501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7991066737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7991066737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1187861272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1187861272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 7612000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 15225 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15162 # Number of instructions committed -system.cpu.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls -system.cpu.num_int_insts 12219 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29037 # number of times the integer registers were read -system.cpu.num_int_register_writes 13819 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3683 # number of memory refs -system.cpu.num_load_insts 2231 # Number of load instructions -system.cpu.num_store_insts 1452 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 15224.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 3363 # Number of branches fetched -system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction -system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction -system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 15207 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 17432 # Transaction distribution -system.membus.trans_dist::ReadResp 17432 # Transaction distribution -system.membus.trans_dist::WriteReq 1442 # Transaction distribution -system.membus.trans_dist::WriteResp 1442 # Transaction distribution -system.membus.trans_dist::SwapReq 6 # Transaction distribution -system.membus.trans_dist::SwapResp 6 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18880 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18880 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18880 # Request fanout histogram +sim_seconds 0.000008 +sim_ticks 7612000 +final_tick 7612000 +sim_freq 1000000000000 +host_inst_rate 370319 +host_op_rate 370098 +host_tick_rate 185717309 +host_mem_usage 251756 +host_seconds 0.04 +sim_insts 15162 +sim_ops 15162 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 7612000 +system.physmem.bytes_read::cpu.inst 60828 +system.physmem.bytes_read::cpu.data 11342 +system.physmem.bytes_read::total 72170 +system.physmem.bytes_inst_read::cpu.inst 60828 +system.physmem.bytes_inst_read::total 60828 +system.physmem.bytes_written::cpu.data 9042 +system.physmem.bytes_written::total 9042 +system.physmem.num_reads::cpu.inst 15207 +system.physmem.num_reads::cpu.data 2225 +system.physmem.num_reads::total 17432 +system.physmem.num_writes::cpu.data 1442 +system.physmem.num_writes::total 1442 +system.physmem.num_other::cpu.data 6 +system.physmem.num_other::total 6 +system.physmem.bw_read::cpu.inst 7991066737 +system.physmem.bw_read::cpu.data 1490015765 +system.physmem.bw_read::total 9481082501 +system.physmem.bw_inst_read::cpu.inst 7991066737 +system.physmem.bw_inst_read::total 7991066737 +system.physmem.bw_write::cpu.data 1187861272 +system.physmem.bw_write::total 1187861272 +system.physmem.bw_total::cpu.inst 7991066737 +system.physmem.bw_total::cpu.data 2677877036 +system.physmem.bw_total::total 10668943773 +system.pwrStateResidencyTicks::UNDEFINED 7612000 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 18 +system.cpu.pwrStateResidencyTicks::ON 7612000 +system.cpu.numCycles 15225 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 15162 +system.cpu.committedOps 15162 +system.cpu.num_int_alu_accesses 12219 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 385 +system.cpu.num_conditional_control_insts 2434 +system.cpu.num_int_insts 12219 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 29037 +system.cpu.num_int_register_writes 13819 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 3683 +system.cpu.num_load_insts 2231 +system.cpu.num_store_insts 1452 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 15225 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 3363 +system.cpu.op_class::No_OpClass 726 4.77% 4.77% +system.cpu.op_class::IntAlu 10798 71.01% 75.78% +system.cpu.op_class::IntMult 0 0.00% 75.78% +system.cpu.op_class::IntDiv 0 0.00% 75.78% +system.cpu.op_class::FloatAdd 0 0.00% 75.78% +system.cpu.op_class::FloatCmp 0 0.00% 75.78% +system.cpu.op_class::FloatCvt 0 0.00% 75.78% +system.cpu.op_class::FloatMult 0 0.00% 75.78% +system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% +system.cpu.op_class::FloatDiv 0 0.00% 75.78% +system.cpu.op_class::FloatMisc 0 0.00% 75.78% +system.cpu.op_class::FloatSqrt 0 0.00% 75.78% +system.cpu.op_class::SimdAdd 0 0.00% 75.78% +system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% +system.cpu.op_class::SimdAlu 0 0.00% 75.78% +system.cpu.op_class::SimdCmp 0 0.00% 75.78% +system.cpu.op_class::SimdCvt 0 0.00% 75.78% +system.cpu.op_class::SimdMisc 0 0.00% 75.78% +system.cpu.op_class::SimdMult 0 0.00% 75.78% +system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% +system.cpu.op_class::SimdShift 0 0.00% 75.78% +system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% +system.cpu.op_class::SimdSqrt 0 0.00% 75.78% +system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% +system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% +system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% +system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% +system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% +system.cpu.op_class::MemRead 2231 14.67% 90.45% +system.cpu.op_class::MemWrite 1452 9.55% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 15207 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 +system.membus.trans_dist::ReadReq 17432 +system.membus.trans_dist::ReadResp 17432 +system.membus.trans_dist::WriteReq 1442 +system.membus.trans_dist::WriteResp 1442 +system.membus.trans_dist::SwapReq 6 +system.membus.trans_dist::SwapResp 6 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 +system.membus.pkt_count::total 37760 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 +system.membus.pkt_size::total 81270 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 18880 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 18880 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 18880 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index 76eaa1c9f..d56f74081 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index aa11b3776..65544f70a 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:38 -gem5 executing on e108600-lin, pid 38722 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:42 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64930 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -21,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 44282500 because target called exit() +Exiting @ tick 44698500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 08009f0ca..98ef53418 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,497 +1,497 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000045 # Number of seconds simulated -sim_ticks 44698500 # Number of ticks simulated -final_tick 44698500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 357665 # Simulator instruction rate (inst/s) -host_op_rate 357507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1053539740 # Simulator tick rate (ticks/s) -host_mem_usage 250236 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 15162 # Number of instructions simulated -sim_ops 15162 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 398044677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 197590523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 595635200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 398044677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 398044677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 398044677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 197590523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 595635200 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 44698500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 89397 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15162 # Number of instructions committed -system.cpu.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls -system.cpu.num_int_insts 12219 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29037 # number of times the integer registers were read -system.cpu.num_int_register_writes 13818 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3683 # number of memory refs -system.cpu.num_load_insts 2231 # Number of load instructions -system.cpu.num_store_insts 1452 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 89396.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 3363 # Number of branches fetched -system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction -system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction -system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 15207 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.037351 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023691 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits -system.cpu.dcache.overall_hits::total 3529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3339000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3339000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5355000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5355000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8694000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8694000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8694000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8694000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3286000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3286000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8556000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8556000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8556000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8556000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 151.480746 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 151.480746 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073965 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073965 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 30696 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits -system.cpu.icache.overall_hits::total 14928 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses -system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17542500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17542500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17542500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17542500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17542500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17542500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62651.785714 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62651.785714 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62651.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62651.785714 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17262500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17262500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17262500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17262500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17262500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17262500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61651.785714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61651.785714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 247.870917 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 416 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.004808 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 150.801148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 97.069768 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007564 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012695 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5142500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5142500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8349000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25168500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8349000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25168500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.201923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.201923 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4292500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4292500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6969000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21008500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6969000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21008500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 331 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 416 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 416 # Request fanout histogram -system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.7 # Layer utilization (%) +sim_seconds 0.000045 +sim_ticks 44698500 +final_tick 44698500 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+system.cpu.op_class::SimdSqrt 0 0.00% 75.78% +system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% +system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% +system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% +system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% +system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% +system.cpu.op_class::MemRead 2231 14.67% 90.45% +system.cpu.op_class::MemWrite 1452 9.55% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 15207 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 +system.cpu.dcache.tags.replacements 0 +system.cpu.dcache.tags.tagsinuse 97.037351 +system.cpu.dcache.tags.total_refs 3535 +system.cpu.dcache.tags.sampled_refs 138 +system.cpu.dcache.tags.avg_refs 25.615942 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 +system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 +system.cpu.dcache.tags.occ_percent::total 0.023691 +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 +system.cpu.dcache.tags.tag_accesses 7484 +system.cpu.dcache.tags.data_accesses 7484 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 +system.cpu.dcache.ReadReq_hits::cpu.data 2172 +system.cpu.dcache.ReadReq_hits::total 2172 +system.cpu.dcache.WriteReq_hits::cpu.data 1357 +system.cpu.dcache.WriteReq_hits::total 1357 +system.cpu.dcache.SwapReq_hits::cpu.data 6 +system.cpu.dcache.SwapReq_hits::total 6 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