diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level')
4 files changed, 865 insertions, 861 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini index 733323a88..df4988eaf 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini @@ -93,6 +93,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -106,10 +107,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -123,6 +124,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -135,15 +137,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -202,10 +205,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -219,6 +222,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -231,15 +235,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -258,8 +263,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -270,8 +273,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -331,7 +332,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/arm/linux/hello cwd= drivers= @@ -344,10 +345,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -397,10 +399,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -414,6 +416,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -426,15 +429,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout index 7a7d67b77..00615c5ed 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:05:17 -gem5 executing on e108600-lin, pid 17589 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55755 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 52453000 because target called exit() +Exiting @ tick 52453000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 0bf6798da..67ec14819 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -1,846 +1,846 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000052 # Number of seconds simulated -sim_ticks 52453000 # Number of ticks simulated -final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 494492 # Simulator instruction rate (inst/s) -host_op_rate 571324 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5188174566 # Simulator tick rate (ticks/s) -host_mem_usage 654324 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4988 # Number of instructions simulated -sim_ops 5770 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 351 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 52348000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation -system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 149139.60 # Average gap between requests -system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states -system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 52453000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 52453 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4988 # Number of instructions committed -system.cpu.committedOps 5770 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 215 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls -system.cpu.num_int_insts 4977 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 8049 # number of times the integer registers were read -system.cpu.num_int_register_writes 2992 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written -system.cpu.num_mem_refs 2035 # number of memory refs -system.cpu.num_load_insts 1085 # Number of load instructions -system.cpu.num_store_insts 950 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 52452.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1107 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction -system.cpu.op_class::MemWrite 934 16.02% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5831 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.380856 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082403 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082403 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1833 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1833 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1833 # number of overall hits -system.cpu.dcache.overall_hits::total 1833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9073000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4652000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13725000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13725000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13725000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13725000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1975 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1975 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1975 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1975 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 96654.929577 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 96654.929577 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13441000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.586088 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10305 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits -system.cpu.icache.overall_hits::total 4779 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses -system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25472000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25472000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25472000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25472000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25472000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 102297.188755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 102297.188755 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24974000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24974000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 348 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 391 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram -system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 391 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 184.362995 # Cycle average of tags in use -system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.367017 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 76.995978 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026213 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.018798 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045010 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 3959 # Number of tag accesses -system.l2cache.tags.data_accesses 3959 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits -system.l2cache.demand_hits::total 40 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.l2cache.overall_hits::cpu.data 16 # number of overall hits -system.l2cache.overall_hits::total 40 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 225 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses -system.l2cache.demand_misses::total 351 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 225 # number of overall misses -system.l2cache.overall_misses::cpu.data 126 # number of overall misses -system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4437000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4437000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 23683000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 8214000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 31897000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 23683000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 12651000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 36334000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 23683000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 12651000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 36334000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 249 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 391 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for 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miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 103515.669516 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 103515.669516 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 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-system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3577000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19183000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6554000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 25737000 # number of ReadSharedReq MSHR miss cycles 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ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. 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+system.membus.reqLayer0.utilization 0.7 +system.membus.respLayer0.occupancy 1866250 +system.membus.respLayer0.utilization 3.6 ---------- End Simulation Statistics ---------- |