diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/se/03.learning-gem5/ref/arm | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/arm')
| -rw-r--r-- | tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt | 229 | ||||
| -rw-r--r-- | tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt | 366 |
2 files changed, 304 insertions, 291 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index b0e38a814..670cfd0c1 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000326 # Number of seconds simulated -sim_ticks 325849000 # Number of ticks simulated -final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000333 # Number of seconds simulated +sim_ticks 332645000 # Number of ticks simulated +final_tick 332645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174378 # Simulator instruction rate (inst/s) -host_op_rate 201529 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11371603109 # Simulator tick rate (ticks/s) -host_mem_usage 647324 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 141116 # Simulator instruction rate (inst/s) +host_op_rate 163173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9403646091 # Simulator tick rate (ticks/s) +host_mem_usage 651444 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.mem_ctrl.num_reads::cpu.data 1061 # Nu system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 61709565 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14337930 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 76047494 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 61709565 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 61709565 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 11342677 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 11342677 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 61709565 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 25680607 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 87390172 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 60448827 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 14045003 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 74493830 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 60448827 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 60448827 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 11110944 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 11110944 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 60448827 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 25155947 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 85604774 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6089 # Number of read requests accepted system.mem_ctrl.writeReqs 936 # Number of write requests accepted system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 384000 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 3072 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadDRAM 383296 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6400 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 3696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 856 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 855 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 911 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 1454 # Per bank write bursts @@ -58,8 +58,8 @@ system.mem_ctrl.perBankRdBursts::6 487 # Pe system.mem_ctrl.perBankRdBursts::7 206 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 42 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 155 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 194 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 431 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 192 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 422 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 108 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 36 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.mem_ctrl.perBankWrBursts::7 0 # Pe system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 30 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 46 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 325773000 # Total gap between requests +system.mem_ctrl.totGap 332568000 # Total gap between requests system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 5991 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 5980 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 9 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -161,7 +161,7 @@ system.mem_ctrl.wrQLenPdf::28 4 # Wh system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 3 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,85 +193,86 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 495 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 775.886869 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 648.412049 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 330.044561 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 19 3.84% 3.84% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 31 6.26% 10.10% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 37 7.47% 17.58% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 33 6.67% 24.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 20 4.04% 28.28% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 33 6.67% 34.95% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 27 5.45% 40.40% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 25 5.05% 45.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 270 54.55% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 495 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1299.666667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1199.462709 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 577.403094 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-703 1 33.33% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1471 1 33.33% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1792-1855 1 33.33% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 3 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads +system.mem_ctrl.bytesPerActivate::samples 498 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 770.698795 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 632.685353 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 340.090332 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 21 4.22% 4.22% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 40 8.03% 12.25% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 36 7.23% 19.48% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 28 5.62% 25.10% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 23 4.62% 29.72% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 25 5.02% 34.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 24 4.82% 39.56% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 28 5.62% 45.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 273 54.82% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 498 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 606.712727 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 3 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 3 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 17801000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 130301000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 30000000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 2966.83 # Average queueing delay per DRAM burst +system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 17899250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 130193000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 2988.69 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21716.83 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1178.46 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 9.43 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 76.06 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 11.34 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 21738.69 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1152.27 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 12.31 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 74.51 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 11.11 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.28 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.21 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 9.10 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.00 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 24.64 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5504 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 44 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.73 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 55.00 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 46373.38 # Average gap between requests -system.mem_ctrl.pageHitRate 91.25 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2782080 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1518000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37915800 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5487 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 91.62 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 47340.64 # Average gap between requests +system.mem_ctrl.pageHitRate 91.42 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2812320 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1534500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 38048400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 212134050 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 5616000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 280816890 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 878.932981 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 6234500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 216770715 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 6219750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 286745205 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 876.139742 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 7265500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 10920000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 303655500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 309110750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 922320 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 503250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 7932600 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.readEnergy 7893600 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 311040 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 182238975 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 31839000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 244598145 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 765.574385 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 52679500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 188416350 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 31092000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 250498080 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 765.387945 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 51038750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 10920000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 265729250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -301,7 +302,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -331,7 +332,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -361,7 +362,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -392,8 +393,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 325849000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 325849 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 332645000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 332645 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -414,7 +415,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 325848.999000 # Number of busy cycles +system.cpu.num_busy_cycles 332644.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -453,7 +454,13 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6078 # Transaction distribution system.membus.trans_dist::ReadResp 6088 # Transaction distribution system.membus.trans_dist::WriteReq 925 # Transaction distribution @@ -470,20 +477,20 @@ system.membus.pkt_size::total 28476 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7025 # Request fanout histogram -system.membus.snoop_fanout::mean 0.715730 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.451098 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1997 28.43% 28.43% # Request fanout histogram -system.membus.snoop_fanout::1 5028 71.57% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7025 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7025 # Request fanout histogram system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 11411750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3326000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11412500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3325250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index b14eb2f25..005f27b4b 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000050 # Number of seconds simulated -sim_ticks 49855000 # Number of ticks simulated -final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 50074000 # Number of ticks simulated +final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 256506 # Simulator instruction rate (inst/s) -host_op_rate 296356 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2557788683 # Simulator tick rate (ticks/s) -host_mem_usage 651420 # Number of bytes of host memory used +host_inst_rate 207988 # Simulator instruction rate (inst/s) +host_op_rate 240459 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2085706484 # Simulator tick rate (ticks/s) +host_mem_usage 655032 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14400 # Nu system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 288837629 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 161749072 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 450586701 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 288837629 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 288837629 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 288837629 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 161749072 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 450586701 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 351 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 49757000 # Total gap between requests +system.mem_ctrl.totGap 49975000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -189,30 +189,30 @@ system.mem_ctrl.wrQLenPdf::62 0 # Wh system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 214.051474 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 262.513782 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,38 +220,38 @@ system.mem_ctrl.readRowHits 274 # Nu system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 141757.83 # Average gap between requests +system.mem_ctrl.avgGap 142378.92 # Average gap between requests system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states +system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -281,7 +281,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -311,7 +311,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +341,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -372,8 +372,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 49855000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 49855 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 50074 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -394,7 +394,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 49854.999000 # Number of busy cycles +system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -433,23 +433,23 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits @@ -470,14 +470,14 @@ system.cpu.dcache.demand_misses::cpu.data 142 # n system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -498,14 +498,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,14 +520,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses @@ -536,31 +536,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses system.cpu.icache.tags.data_accesses 10305 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits @@ -573,12 +573,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses @@ -591,12 +591,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -609,31 +609,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 249 system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -664,25 +664,25 @@ system.l2bus.respLayer0.occupancy 747000 # La system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id +system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id +system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3959 # Number of tag accesses system.l2cache.tags.data_accesses 3959 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits @@ -703,17 +703,17 @@ system.l2cache.demand_misses::total 351 # nu system.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.l2cache.overall_misses::cpu.data 126 # number of overall misses system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) @@ -736,17 +736,17 @@ system.l2cache.demand_miss_rate::total 0.897698 # mi system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -764,17 +764,17 @@ system.l2cache.demand_mshr_misses::total 351 # nu system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses @@ -786,18 +786,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.897698 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -820,7 +826,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 351 # Request fanout histogram system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1865750 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- |