stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

2 files changed, 31 insertions, 8 deletions

diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
index 0fe3c4c97..1d743770e 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.000326                       # Nu
 sim_ticks                                   325849000                       # Number of ticks simulated
 final_tick                                  325849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 204518                       # Simulator instruction rate (inst/s)
-host_op_rate                                   236491                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            13350749795                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 689808                       # Number of bytes of host memory used
+host_inst_rate                                 301831                       # Simulator instruction rate (inst/s)
+host_op_rate                                   348968                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            19697741357                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 691496                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    325849000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            20108                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             4672                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               24780                       # Number of bytes read from this memory
@@ -269,6 +270,8 @@ system.mem_ctrl_1.memoryStateTime::REF       10660000                       # Ti
 system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.mem_ctrl_1.memoryStateTime::ACT      256888500                       # Time in different power states
 system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED    325849000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED    325849000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -298,6 +301,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED    325849000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -327,6 +331,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED    325849000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -356,6 +361,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED    325849000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -386,6 +392,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON       325849000                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                           325849                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -446,6 +453,7 @@ system.cpu.op_class::MemWrite                     950     16.29%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5831                       # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED    325849000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6078                       # Transaction distribution
 system.membus.trans_dist::ReadResp               6088                       # Transaction distribution
 system.membus.trans_dist::WriteReq                925                       # Transaction distribution
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
index 825faee95..bff9edae7 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.000050                       # Nu
 sim_ticks                                    49855000                       # Number of ticks simulated
 final_tick                                   49855000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 372227                       # Simulator instruction rate (inst/s)
-host_op_rate                                   430264                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3715181399                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 693900                       # Number of bytes of host memory used
+host_inst_rate                                 407452                       # Simulator instruction rate (inst/s)
+host_op_rate                                   470980                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4066768251                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 695596                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            14400                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             8064                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               22464                       # Number of bytes read from this memory
@@ -249,6 +250,8 @@ system.mem_ctrl_1.memoryStateTime::REF        1560000                       # Ti
 system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.mem_ctrl_1.memoryStateTime::ACT       42873250                       # Time in different power states
 system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -278,6 +281,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -307,6 +311,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -336,6 +341,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -366,6 +372,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON        49855000                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                            49855                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -426,6 +433,7 @@ system.cpu.op_class::MemWrite                     950     16.29%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5831                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
 system.cpu.dcache.tags.tagsinuse            84.288257                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1855                       # Total number of references to valid blocks.
@@ -441,6 +449,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          123
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.138672                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4136                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4136                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data          951                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             951                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          882                       # number of WriteReq hits
@@ -535,6 +544,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                70                       # number of replacements
 system.cpu.icache.tags.tagsinuse            96.468360                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4779                       # Total number of references to valid blocks.
@@ -550,6 +560,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          125
 system.cpu.icache.tags.occ_task_id_percent::1024     0.699219                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses             10305                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses            10305                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst         4779                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4779                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4779                       # number of demand (read+write) hits
@@ -622,6 +633,7 @@ system.l2bus.snoop_filter.hit_multi_requests           10
 system.l2bus.snoop_filter.tot_snoops                0                       # Total number of snoops made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2bus.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.l2bus.trans_dist::ReadResp                 348                       # Transaction distribution
 system.l2bus.trans_dist::CleanEvict                70                       # Transaction distribution
 system.l2bus.trans_dist::ReadExReq                 43                       # Transaction distribution
@@ -651,6 +663,7 @@ system.l2bus.respLayer0.occupancy              747000                       # La
 system.l2bus.respLayer0.utilization               1.5                       # Layer utilization (%)
 system.l2bus.respLayer1.occupancy              426000                       # Layer occupancy (ticks)
 system.l2bus.respLayer1.utilization               0.9                       # Layer utilization (%)
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.l2cache.tags.replacements                    0                       # number of replacements
 system.l2cache.tags.tagsinuse              156.197536                       # Cycle average of tags in use
 system.l2cache.tags.total_refs                    100                       # Total number of references to valid blocks.
@@ -668,6 +681,7 @@ system.l2cache.tags.age_task_id_blocks_1024::1          246
 system.l2cache.tags.occ_task_id_percent::1024     0.075195                       # Percentage of cache occupancy per task id
 system.l2cache.tags.tag_accesses                 3959                       # Number of tag accesses
 system.l2cache.tags.data_accesses                3959                       # Number of data accesses
+system.l2cache.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.l2cache.ReadSharedReq_hits::cpu.inst           24                       # number of ReadSharedReq hits
 system.l2cache.ReadSharedReq_hits::cpu.data           16                       # number of ReadSharedReq hits
 system.l2cache.ReadSharedReq_hits::total           40                       # number of ReadSharedReq hits
@@ -782,6 +796,7 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114
 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114                       # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED     49855000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                308                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               43                       # Transaction distribution