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author | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
commit | 607c2772915628c2c67c1c5bfdefaa33ae66a06e (patch) | |
tree | f8f23fd4012f9a0053d65ac91792a7dc61d6baff /tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level | |
parent | 71c982ff708cc3adc7c0eccf536fea34c20cc5f0 (diff) | |
download | gem5-607c2772915628c2c67c1c5bfdefaa33ae66a06e.tar.xz |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level')
-rw-r--r-- | tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 3bd6c6ff6..c7fcf57ee 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000062 # Nu sim_ticks 62333000 # Number of ticks simulated final_tick 62333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 499257 # Simulator instruction rate (inst/s) -host_op_rate 498740 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5505866075 # Simulator tick rate (ticks/s) -host_mem_usage 635976 # Number of bytes of host memory used +host_inst_rate 472885 # Simulator instruction rate (inst/s) +host_op_rate 471880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5205204018 # Simulator tick rate (ticks/s) +host_mem_usage 636424 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated @@ -313,7 +313,9 @@ system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Cl system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction @@ -337,6 +339,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction |