diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/se/03.learning-gem5/ref/mips | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/mips')
| -rw-r--r-- | tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt | 232 | ||||
| -rw-r--r-- | tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt | 390 |
2 files changed, 317 insertions, 305 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index 54ae8e9b7..60c6ac279 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000369 # Number of seconds simulated -sim_ticks 368887000 # Number of ticks simulated -final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000377 # Number of seconds simulated +sim_ticks 376893000 # Number of ticks simulated +final_tick 376893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 354647 # Simulator instruction rate (inst/s) -host_op_rate 354403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23159010384 # Simulator tick rate (ticks/s) -host_mem_usage 629604 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 173660 # Simulator instruction rate (inst/s) +host_op_rate 173583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11593149844 # Simulator tick rate (ticks/s) +host_mem_usage 632708 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.mem_ctrl.num_reads::cpu.data 1135 # Nu system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 61178627 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 11659397 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 72838024 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 61178627 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 61178627 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 9761797 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 9761797 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 61178627 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 21421194 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 82599821 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 59879064 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 11411727 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 71290791 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 59879064 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 59879064 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 9554436 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 9554436 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 59879064 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 20966163 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 80845227 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6778 # Number of read requests accepted system.mem_ctrl.writeReqs 901 # Number of write requests accepted system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 427648 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 428096 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 807 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 811 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 275 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts @@ -55,15 +55,15 @@ system.mem_ctrl.perBankRdBursts::3 0 # Pe system.mem_ctrl.perBankRdBursts::4 215 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 518 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 519 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 346 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 350 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 50 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 1429 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 49 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts @@ -71,18 +71,18 @@ system.mem_ctrl.perBankWrBursts::3 0 # Pe system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 8 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 8 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 29 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 2 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 30 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 19 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 2 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 14 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 3 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 368811000 # Total gap between requests +system.mem_ctrl.totGap 376816000 # Total gap between requests system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6682 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6689 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -155,10 +155,10 @@ system.mem_ctrl.wrQLenPdf::22 5 # Wh system.mem_ctrl.wrQLenPdf::23 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see @@ -193,26 +193,26 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 506.270907 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 291.216794 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 415.367861 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 272 32.04% 32.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 76 8.95% 40.99% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 61 7.18% 48.17% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 46 5.42% 53.59% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 36 4.24% 57.83% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 42 4.95% 62.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 24 2.83% 65.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 67.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 277 32.63% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 838 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 513.374702 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 298.080754 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 413.335022 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 263 31.38% 31.38% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 85 10.14% 41.53% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 42 5.01% 46.54% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 43 5.13% 51.67% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 44 5.25% 56.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 53 6.32% 63.25% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 15 1.79% 65.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 22 2.63% 67.66% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 271 32.34% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 838 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1349.750000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1262.645152 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 506.185325 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-703 1 25.00% 25.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1522.250000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1505.224255 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 263.075876 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1343 1 25.00% 50.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes @@ -221,57 +221,57 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 28067250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 153354750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 33410000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 4200.43 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 28198000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 153616750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 33445000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 4215.58 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22950.43 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1159.29 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 11.10 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 72.85 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 9.76 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 22965.58 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1135.86 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 10.87 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 71.30 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 9.55 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.14 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.06 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.96 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.87 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5834 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 58 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 87.31 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 61.70 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48028.52 # Average gap between requests -system.mem_ctrl.pageHitRate 86.95 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 1058400 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 577500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl.avgWrQLen 23.23 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5853 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 57 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 87.50 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 63.33 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 49070.97 # Average gap between requests +system.mem_ctrl.pageHitRate 87.18 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 1020600 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 556875 # Energy for precharge commands per rank (pJ) system.mem_ctrl_0.readEnergy 8806200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 143993115 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 93418500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 271794915 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 742.175615 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 153996500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_0.writeEnergy 51840 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 141780375 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 100031250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 276658020 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 739.727326 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 165010500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 200230500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 196602500 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 5344920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 2916375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 42907800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 375840 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 246623040 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 3392250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 325462545 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 888.722897 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 3452250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 42939000 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 362880 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 252188235 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 3192750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 331284930 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 885.747138 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2538750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 12480000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 350555250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 359011750 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -291,8 +291,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368887000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 368887 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 376893000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 376893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -311,7 +311,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 368887 # Number of busy cycles +system.cpu.num_busy_cycles 376893 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -350,7 +350,13 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6778 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution @@ -364,20 +370,20 @@ system.membus.pkt_size::total 30470 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7679 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734861 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441436 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2036 26.51% 26.51% # Request fanout histogram -system.membus.snoop_fanout::1 5643 73.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7679 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7679 # Request fanout histogram system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 12857500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer0.occupancy 12853500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3555500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index c2c263451..27ea6dc01 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000059 # Number of seconds simulated -sim_ticks 58892000 # Number of ticks simulated -final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 59115000 # Number of ticks simulated +final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 557970 # Simulator instruction rate (inst/s) -host_op_rate 557350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5812791438 # Simulator tick rate (ticks/s) -host_mem_usage 633704 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 219311 # Simulator instruction rate (inst/s) +host_op_rate 219196 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2295881155 # Simulator tick rate (ticks/s) +host_mem_usage 637060 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 18752 # Nu system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 318413367 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 148882701 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 467296067 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 318413367 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 318413367 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 318413367 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 148882701 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 467296067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 430 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 58762000 # Total gap between requests +system.mem_ctrl.totGap 58984000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,70 +187,70 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 232.212389 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 169.054443 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 210.567831 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 44 38.94% 65.49% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 17 15.04% 80.53% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 9 7.96% 88.50% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.65 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.65 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 313 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 72.79 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 136655.81 # Average gap between requests -system.mem_ctrl.pageHitRate 72.79 # Row buffer hit rate, read and write combined +system.mem_ctrl.avgGap 137172.09 # Average gap between requests +system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 196560 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 678600 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 26204040 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 9872250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 40618620 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 741.706329 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 17140250 # Time in different power states +system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 36672750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 635040 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 346500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 2425800 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 37227555 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 202500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 44397315 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 810.706261 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 145000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -270,8 +270,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58892000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 58892 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 59115 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -290,7 +290,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 58892 # Number of busy cycles +system.cpu.num_busy_cycles 59115 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -329,23 +329,23 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -362,14 +362,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8910000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8910000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5264000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5264000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14174000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -386,14 +386,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 105280 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 103459.854015 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 103459.854015 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,14 +408,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5164000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5164000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -424,31 +424,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 94 # number of replacements -system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses system.cpu.icache.tags.data_accesses 11583 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits @@ -461,12 +461,12 @@ system.cpu.icache.demand_misses::cpu.inst 297 # n system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses system.cpu.icache.overall_misses::total 297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses @@ -479,12 +479,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,31 +497,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 297 system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 384 # Transaction distribution system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -552,25 +552,25 @@ system.l2bus.respLayer0.occupancy 891000 # La system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id +system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4654 # Number of tag accesses system.l2cache.tags.data_accesses 4654 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits @@ -588,17 +588,17 @@ system.l2cache.demand_misses::total 430 # nu system.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 430 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses) @@ -621,17 +621,17 @@ system.l2cache.demand_miss_rate::total 0.990783 # mi system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,17 +649,17 @@ system.l2cache.demand_mshr_misses::total 430 # nu system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses @@ -671,18 +671,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.990783 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -705,7 +711,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 430 # Request fanout histogram system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2299000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- |