diff options
| author | Jason Lowe-Power <power.jg@gmail.com> | 2015-09-16 09:35:36 -0500 |
|---|---|---|
| committer | Jason Lowe-Power <power.jg@gmail.com> | 2015-09-16 09:35:36 -0500 |
| commit | fdf2a6f43928323c880928ef8446bc277e643781 (patch) | |
| tree | 4b48dc66ea4b3dd47ff6253575eac084f7bf3b61 /tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level | |
| parent | 29dd04cfe96f095414d881b53cb0838661996f57 (diff) | |
| download | gem5-fdf2a6f43928323c880928ef8446bc277e643781.tar.xz | |
stats: files for regression tests for Learning gem5 scripts
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level')
4 files changed, 1086 insertions, 0 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini new file mode 100644 index 000000000..24aab210d --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini @@ -0,0 +1,382 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[2] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=apic_clk_domain dcache dtb icache interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.clk_domain +eventq_index=0 + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=65536 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.l2bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=65536 + +[system.cpu.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +clk_domain=system.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=16384 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.l2bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=16384 + +[system.cpu.interrupts] +type=X86LocalApic +clk_domain=system.cpu.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.membus.slave[1] +int_slave=system.membus.master[1] +pio=system.membus.master[0] + +[system.cpu.isa] +type=X86ISA +eventq_index=0 + +[system.cpu.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +clk_domain=system.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/x86/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2bus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=262144 +system=system +tags=system.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +cpu_side=system.l2bus.master[0] +mem_side=system.membus.slave[0] + +[system.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=262144 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[2] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port +slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout new file mode 100755 index 000000000..f552f3ed5 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout @@ -0,0 +1,13 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 6 2015 10:35:34 +gem5 started Jul 6 2015 14:40:25 +gem5 executing on mustardseed.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 55844000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt new file mode 100644 index 000000000..eeac393c4 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -0,0 +1,689 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000056 # Number of seconds simulated +sim_ticks 55844000 # Number of ticks simulated +final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 212931 # Simulator instruction rate (inst/s) +host_op_rate 384017 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2076955895 # Simulator tick rate (ticks/s) +host_mem_usage 693340 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 5712 # Number of instructions simulated +sim_ops 10314 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory +system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 262445384 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 154716711 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 417162094 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 262445384 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 262445384 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 262445384 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 154716711 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 417162094 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 364 # Number of read requests accepted +system.mem_ctrl.writeReqs 0 # Number of write requests accepted +system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 23296 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 23296 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 30 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 1 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 5 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 8 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 43 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 40 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 13 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 24 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 17 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 71 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 62 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 14 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 2 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 14 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 4 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 16 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 55714000 # Total gap between requests +system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 364 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 364 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 115 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 199.234783 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 135.588464 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 217.243914 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 49 42.61% 42.61% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 34 29.57% 72.17% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3554250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10379250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 9764.42 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 28514.42 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 244 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 67.03 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrl.avgGap 153060.44 # Average gap between requests +system.mem_ctrl.pageHitRate 67.03 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1240200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 32401080 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 4436250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 42104850 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 768.845267 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 7212250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 45745250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 567000 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 309375 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 36016020 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 55844 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5712 # Number of instructions committed +system.cpu.committedOps 10314 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 221 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls +system.cpu.num_int_insts 10205 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 19296 # number of times the integer registers were read +system.cpu.num_int_register_writes 7977 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written +system.cpu.num_mem_refs 2025 # number of memory refs +system.cpu.num_load_insts 1084 # Number of load instructions +system.cpu.num_store_insts 941 # Number of store instructions +system.cpu.num_idle_cycles 0.001000 # Number of idle cycles +system.cpu.num_busy_cycles 55843.999000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 1306 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction +system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction +system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 10314 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 81.671962 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 81.671962 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079758 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079758 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits +system.cpu.dcache.overall_hits::total 1890 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses +system.cpu.dcache.overall_misses::total 135 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6006000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6006000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8260000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8260000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14266000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14266000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14266000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14266000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 941 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2025 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2025 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2025 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2025 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.051661 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.083953 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 107250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 107250 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104556.962025 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 104556.962025 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 105674.074074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8102000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8102000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13996000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13996000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 58 # number of replacements +system.cpu.icache.tags.tagsinuse 91.240171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 91.240171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.356407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.356407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses +system.cpu.icache.tags.data_accesses 14801 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits +system.cpu.icache.overall_hits::total 7048 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 235 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses +system.cpu.icache.overall_misses::total 235 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23702000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23702000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23702000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23702000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23702000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23702000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7283 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 7283 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7283 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032267 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.032267 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100859.574468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100859.574468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100859.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23232000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23232000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23232000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23232000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.trans_dist::ReadResp 291 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution +system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution +system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution +system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.snoops 0 # Total snoops (count) +system.l2bus.snoop_fanout::samples 428 # Request fanout histogram +system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 428 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::total 428 # Request fanout histogram +system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) +system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) +system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) +system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.l2cache.tags.replacements 0 # number of replacements +system.l2cache.tags.tagsinuse 135.849297 # Cycle average of tags in use +system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. +system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. +system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2cache.tags.occ_blocks::cpu.inst 106.899114 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 28.950183 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id +system.l2cache.tags.tag_accesses 3788 # Number of tag accesses +system.l2cache.tags.data_accesses 3788 # Number of data accesses +system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits +system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits +system.l2cache.demand_hits::total 6 # number of demand (read+write) hits +system.l2cache.overall_hits::cpu.inst 6 # number of overall hits +system.l2cache.overall_hits::total 6 # number of overall hits +system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses +system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses +system.l2cache.ReadSharedReq_misses::cpu.inst 229 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::total 285 # number of ReadSharedReq misses +system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses +system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.l2cache.demand_misses::total 364 # number of demand (read+write) misses +system.l2cache.overall_misses::cpu.inst 229 # number of overall misses +system.l2cache.overall_misses::cpu.data 135 # number of overall misses +system.l2cache.overall_misses::total 364 # number of overall misses +system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22401000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 28127000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22401000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 35992000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22401000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 35992000 # number of overall miss cycles +system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses +system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses +system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses +system.l2cache.overall_accesses::cpu.inst 235 # number of overall (read+write) accesses +system.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses +system.l2cache.overall_accesses::total 370 # number of overall (read+write) accesses +system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.974468 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::total 0.979381 # miss rate for ReadSharedReq accesses +system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses +system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses +system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses +system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97820.960699 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 98691.228070 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98879.120879 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98879.120879 # average overall miss latency +system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2cache.fast_writes 0 # number of fast writes performed +system.l2cache.cache_copies 0 # number of cache copies performed +system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses +system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses +system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses +system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17821000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 22427000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17821000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 28712000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17821000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 28712000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses +system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses +system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77820.960699 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78691.228070 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency +system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadResp 285 # Transaction distribution +system.membus.trans_dist::ReadExReq 79 # Transaction distribution +system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution +system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2cache.mem_side::total 23296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23296 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 364 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 364 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 364 # Request fanout histogram +system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 1952750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |