diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/se/03.learning-gem5/ref/x86/linux | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/x86/linux')
| -rw-r--r-- | tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt | 263 | ||||
| -rw-r--r-- | tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt | 405 |
2 files changed, 339 insertions, 329 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index f9a903a5e..7312a839d 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000445 # Number of seconds simulated -sim_ticks 445082000 # Number of ticks simulated -final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000455 # Number of seconds simulated +sim_ticks 454507000 # Number of ticks simulated +final_tick 454507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125099 # Simulator instruction rate (inst/s) -host_op_rate 225788 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9739384878 # Simulator tick rate (ticks/s) -host_mem_usage 648172 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 76712 # Simulator instruction rate (inst/s) +host_op_rate 138489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6101741543 # Simulator tick rate (ticks/s) +host_mem_usage 651776 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory @@ -26,29 +26,29 @@ system.mem_ctrl.num_reads::cpu.data 1084 # Nu system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 130906215 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 16102651 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 147008866 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 130906215 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 130906215 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 16086923 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 16086923 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 130906215 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 32189574 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 163095789 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 128191645 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 15768734 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 143960379 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 128191645 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 128191645 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 15753333 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 15753333 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 128191645 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 31522067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 159713712 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 8367 # Number of read requests accepted system.mem_ctrl.writeReqs 941 # Number of write requests accepted system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadDRAM 524736 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 10752 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 168 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 819 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::0 273 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts @@ -58,13 +58,13 @@ system.mem_ctrl.perBankRdBursts::6 1103 # Pe system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 1055 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 12 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 115 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 6 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts @@ -72,17 +72,17 @@ system.mem_ctrl.perBankWrBursts::4 0 # Pe system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 55 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 29 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 2 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 53 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 23 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 5 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 444958000 # Total gap between requests +system.mem_ctrl.totGap 454381000 # Total gap between requests system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 861 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 8199 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -146,8 +146,8 @@ system.mem_ctrl.wrQLenPdf::13 1 # Wh system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see @@ -155,13 +155,13 @@ system.mem_ctrl.wrQLenPdf::22 7 # Wh system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,94 +194,93 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 625.677267 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 430.153995 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 392.580114 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 141 16.61% 16.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 68 8.01% 24.62% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 71 8.36% 32.98% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 65 7.66% 40.64% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 53 6.24% 46.88% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 45 5.30% 52.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 35 4.12% 56.30% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 58.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 356 41.93% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 622.812721 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 426.803074 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 394.306776 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 142 16.73% 16.73% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 69 8.13% 24.85% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 77 9.07% 33.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 63 7.42% 41.34% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 55 6.48% 47.82% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 39 4.59% 52.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 28 3.30% 55.71% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 21 2.47% 58.19% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 355 41.81% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads +system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1282.333333 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1020.532539 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 764.587906 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::256-383 1 16.67% 16.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::384-511 1 16.67% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1407 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1920-2047 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2048-2175 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 29060250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 182922750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3541.34 # Average queueing delay per DRAM burst +system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 29381000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 183112250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 40995000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3583.49 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22291.34 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1179.97 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 16.10 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 147.01 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 16.09 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 22333.49 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1154.52 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 13.52 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 143.96 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 15.75 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.34 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.22 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.13 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 9.13 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.02 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.11 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.76 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 7369 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.80 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47803.82 # Average gap between requests -system.mem_ctrl.pageHitRate 89.56 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3265920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1782000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 40552200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 77760 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 28987920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 242604540 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 53634750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 370905090 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 835.228387 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 86580500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 14820000 # Time in different power states +system.mem_ctrl.avgWrQLen 23.84 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 7356 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 85 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 69.67 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 48816.18 # Average gap between requests +system.mem_ctrl.pageHitRate 89.42 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3281040 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1790250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 40294800 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 248297130 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 53313000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 376511580 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 833.243697 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 86206500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 15080000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 342689500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 350589750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 3152520 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1720125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 23314200 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 648000 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 28987920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 267116535 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 32133000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 357072300 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 804.078804 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 51572750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 14820000 # Time in different power states +system.mem_ctrl_1.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 23275200 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 583200 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 273625650 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 31095000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 362913120 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 803.149454 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 50725000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 15080000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 377923250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 387261000 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 445082000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 445082 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 454507000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 454507 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -302,7 +301,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 445081.999000 # Number of busy cycles +system.cpu.num_busy_cycles 454506.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -341,7 +340,13 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 8367 # Transaction distribution system.membus.trans_dist::ReadResp 8367 # Transaction distribution system.membus.trans_dist::WriteReq 941 # Transaction distribution @@ -359,20 +364,20 @@ system.membus.pkt_size::total 72591 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 9308 # Request fanout histogram -system.membus.snoop_fanout::mean 0.782445 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.412605 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2025 21.76% 21.76% # Request fanout histogram -system.membus.snoop_fanout::1 7283 78.24% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 9308 # Request fanout histogram system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 16547500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3433750 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 16547250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3431500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index 7d909cf8e..a74924642 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000056 # Number of seconds simulated -sim_ticks 55844000 # Number of ticks simulated -final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 56435000 # Number of ticks simulated +final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197644 # Simulator instruction rate (inst/s) -host_op_rate 356622 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1929610808 # Simulator tick rate (ticks/s) -host_mem_usage 652268 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 125605 # Simulator instruction rate (inst/s) +host_op_rate 226732 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1240265940 # Simulator tick rate (ticks/s) +host_mem_usage 656384 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14656 # Nu system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 262445384 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 154716711 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 417162094 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 262445384 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 262445384 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 262445384 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 154716711 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 417162094 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 364 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 55714000 # Total gap between requests +system.mem_ctrl.totGap 56304000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,78 +187,77 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 115 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 199.234783 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 135.588464 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 217.243914 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 49 42.61% 42.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 34 29.57% 72.17% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 244 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 67.03 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 153060.44 # Average gap between requests -system.mem_ctrl.pageHitRate 67.03 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1240200 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 154681.32 # Average gap between requests +system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 32401080 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 4436250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 42104850 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 768.845267 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 7212250 # Time in different power states +system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 45745250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 567000 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 309375 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 36016020 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 55844000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 55844 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 56435 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -279,7 +278,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 55843.999000 # Number of busy cycles +system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -318,23 +317,23 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits @@ -351,14 +350,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6006000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6006000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8260000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8260000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14266000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14266000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14266000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14266000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) @@ -375,14 +374,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 107250 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 107250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104556.962025 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 104556.962025 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 105674.074074 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -397,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5894000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5894000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8102000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8102000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13996000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13996000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses @@ -413,31 +412,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits @@ -450,12 +449,12 @@ system.cpu.icache.demand_misses::cpu.inst 235 # n system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23702000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23702000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23702000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23702000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23702000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23702000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses @@ -468,12 +467,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100859.574468 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100859.574468 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100859.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -486,31 +485,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 235 system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23232000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23232000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23232000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23232000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -538,28 +537,28 @@ system.l2bus.snoop_fanout::total 370 # Re system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id +system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3788 # Number of tag accesses system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits @@ -577,17 +576,17 @@ system.l2cache.demand_misses::total 364 # nu system.l2cache.overall_misses::cpu.inst 229 # number of overall misses system.l2cache.overall_misses::cpu.data 135 # number of overall misses system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) @@ -610,17 +609,17 @@ system.l2cache.demand_miss_rate::total 0.983784 # mi system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,17 +637,17 @@ system.l2cache.demand_mshr_misses::total 364 # nu system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses @@ -660,18 +659,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.983784 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution @@ -695,8 +700,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 364 # Request fanout histogram system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1952750 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) +system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |