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authorSteve Reinhardt <steve.reinhardt@amd.com>2016-03-17 10:32:53 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2016-03-17 10:32:53 -0700
commitd7c083864c85c3ab24b40fc85ef3cae8031c5912 (patch)
treeae575d831de5d67596ca3aae5e87a71f9c9fd1cd /tests/quick/se/03.learning-gem5/ref
parent9b4249410ec18cac9df2c7e9c0a4a6ce5459233d (diff)
downloadgem5-d7c083864c85c3ab24b40fc85ef3cae8031c5912.tar.xz
stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref')
-rw-r--r--tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini1
-rwxr-xr-xtests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout12
-rw-r--r--tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt345
-rw-r--r--tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini5
-rwxr-xr-xtests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout12
-rw-r--r--tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt552
-rw-r--r--tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini1
-rwxr-xr-xtests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr1
-rwxr-xr-xtests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout12
-rw-r--r--tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt292
-rw-r--r--tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini5
-rwxr-xr-xtests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr1
-rwxr-xr-xtests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout10
-rw-r--r--tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt346
14 files changed, 800 insertions, 795 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
index 3db01e542..7b696dc10 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
@@ -222,6 +222,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
index e1906cb05..fa59b7ebb 100755
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
@@ -1,14 +1,16 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:15
-gem5 executing on zizzer, pid 34054
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:58:08
+gem5 executing on phenom, pid 28209
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 405501000 because target called exit()
+Exiting @ tick 405365000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
index dee41c633..1b652ed70 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
@@ -1,91 +1,91 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000406 # Number of seconds simulated
-sim_ticks 405501000 # Number of ticks simulated
-final_tick 405501000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000405 # Number of seconds simulated
+sim_ticks 405365000 # Number of ticks simulated
+final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86197 # Simulator instruction rate (inst/s)
-host_op_rate 86167 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5423806428 # Simulator tick rate (ticks/s)
-host_mem_usage 613516 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-sim_insts 6440 # Number of instructions simulated
-sim_ops 6440 # Number of ops (including micro ops) simulated
+host_inst_rate 83628 # Simulator instruction rate (inst/s)
+host_op_rate 83610 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5251060650 # Simulator tick rate (ticks/s)
+host_mem_usage 610048 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+sim_insts 6453 # Number of instructions simulated
+sim_ops 6453 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrl.bytes_read::cpu.inst 25800 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::cpu.data 8828 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::total 34628 # Number of bytes read from this memory
-system.mem_ctrl.bytes_inst_read::cpu.inst 25800 # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_inst_read::total 25800 # Number of instructions bytes read from this memory
+system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory
+system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory
+system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory
+system.mem_ctrl.bytes_inst_read::cpu.inst 25852 # Number of instructions bytes read from this memory
+system.mem_ctrl.bytes_inst_read::total 25852 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.mem_ctrl.bytes_written::total 6696 # Number of bytes written to this memory
-system.mem_ctrl.num_reads::cpu.inst 6450 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::cpu.data 1188 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::total 7638 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::cpu.inst 6463 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::cpu.data 1190 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory
system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst 63624997 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data 21770600 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total 85395597 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst 63624997 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total 63624997 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data 16512906 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total 16512906 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst 63624997 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data 38283506 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total 101908503 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.readReqs 7639 # Number of read requests accepted
+system.mem_ctrl.bw_read::cpu.inst 63774623 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data 21817374 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total 85591997 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst 63774623 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total 63774623 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::cpu.data 16518446 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::total 16518446 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst 63774623 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data 38335821 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total 102110444 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.readReqs 7654 # Number of read requests accepted
system.mem_ctrl.writeReqs 865 # Number of write requests accepted
-system.mem_ctrl.readBursts 7639 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM 477632 # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ 11264 # Total number of bytes read from write queue
+system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM
+system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue
system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM
-system.mem_ctrl.bytesReadSys 34632 # Total read bytes from the system interface side
+system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side
system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.mergedWrBursts 747 # Number of DRAM write bursts merged with an existing one
system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::3 787 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::4 776 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::4 763 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::10 253 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::13 1430 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::15 156 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::4 27 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::5 6 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::5 8 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::10 6 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::13 14 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::13 21 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::14 43 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrl.totGap 405425000 # Total gap between requests
+system.mem_ctrl.totGap 405289000 # Total gap between requests
system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::2 6620 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::3 1019 # Read request sizes (log2)
+system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2)
+system.mem_ctrl.readPktSize::3 1021 # Read request sizes (log2)
system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2)
@@ -96,7 +96,7 @@ system.mem_ctrl.writePktSize::3 809 # Wr
system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0 7463 # What read queue length does an incoming req see
+system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -192,106 +192,105 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh
system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples 775 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean 623.649032 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean 407.696259 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev 407.140251 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127 158 20.39% 20.39% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255 63 8.13% 28.52% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383 48 6.19% 34.71% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511 41 5.29% 40.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639 47 6.06% 46.06% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767 28 3.61% 49.68% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895 28 3.61% 53.29% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023 33 4.26% 57.55% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151 329 42.45% 100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total 775 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::samples 762 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean 634.288714 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean 419.900652 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev 405.302633 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127 146 19.16% 19.16% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255 69 9.06% 28.22% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383 39 5.12% 33.33% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511 43 5.64% 38.98% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639 44 5.77% 44.75% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767 27 3.54% 48.29% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895 31 4.07% 52.36% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023 30 3.94% 56.30% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151 333 43.70% 100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total 762 # Bytes accessed per row activation
system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean 1159.333333 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean 1053.861325 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev 505.634519 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1344-1407 1 16.67% 66.67% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1792-1855 1 16.67% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::mean 1203.833333 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::gmean 1052.985580 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::stdev 699.444184 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::896-1023 1 16.67% 50.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1152-1279 1 16.67% 66.67% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::2432-2559 1 16.67% 100.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes
system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat 26448250 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 166379500 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat 37315000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 3543.92 # Average queueing delay per DRAM burst
+system.mem_ctrl.totQLat 26088750 # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat 165982500 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers
+system.mem_ctrl.avgQLat 3496.68 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 22293.92 # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW 1177.88 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW 15.15 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys 85.41 # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys 16.51 # Average system write bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat 22246.68 # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW 1177.96 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBW 15.16 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys 85.60 # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBWSys 16.52 # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil 9.32 # Data bus utilization in percentage
system.mem_ctrl.busUtilRead 9.20 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen 23.37 # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits 6696 # Number of row buffer hits during reads
-system.mem_ctrl.writeRowHits 87 # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate 73.73 # Row buffer hit rate for writes
-system.mem_ctrl.avgGap 47674.62 # Average gap between requests
-system.mem_ctrl.pageHitRate 89.47 # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy 3439800 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy 1876875 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy 37268400 # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy 213840 # Energy for write commands per rank (pJ)
+system.mem_ctrl.avgWrQLen 24.34 # Average write queue length when enqueuing
+system.mem_ctrl.readRowHits 6706 # Number of row buffer hits during reads
+system.mem_ctrl.writeRowHits 88 # Number of row buffer hits during writes
+system.mem_ctrl.readRowHitRate 89.88 # Row buffer hit rate for reads
+system.mem_ctrl.writeRowHitRate 74.58 # Row buffer hit rate for writes
+system.mem_ctrl.avgGap 47574.72 # Average gap between requests
+system.mem_ctrl.pageHitRate 89.64 # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy 3333960 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy 1819125 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy 37284000 # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.writeEnergy 168480 # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy 264293325 # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy 11250750 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy 344788110 # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower 851.023979 # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE 15542500 # Time in different power states
+system.mem_ctrl_0.actBackEnergy 262765440 # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy 12591750 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.totalEnergy 344407875 # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower 850.082840 # Core power per rank (mW)
+system.mem_ctrl_0.memoryStateTime::IDLE 17896000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF 13520000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT 376096250 # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT 373743250 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrl_1.actEnergy 2419200 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy 1320000 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy 20888400 # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy 408240 # Energy for write commands per rank (pJ)
+system.mem_ctrl_1.actEnergy 2426760 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy 1324125 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy 20872800 # Energy for read commands per rank (pJ)
+system.mem_ctrl_1.writeEnergy 453600 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy 228585105 # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy 42573750 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy 322639815 # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower 796.356403 # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE 69100250 # Time in different power states
+system.mem_ctrl_1.actBackEnergy 229562370 # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy 41716500 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.totalEnergy 322801275 # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower 796.754927 # Core power per rank (mW)
+system.mem_ctrl_1.memoryStateTime::IDLE 67586500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF 13520000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT 322538500 # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT 324052250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1188 # DTB read hits
+system.cpu.dtb.read_hits 1190 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1195 # DTB read accesses
+system.cpu.dtb.read_accesses 1197 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2053 # DTB hits
+system.cpu.dtb.data_hits 2055 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2063 # DTB accesses
-system.cpu.itb.fetch_hits 6451 # ITB hits
+system.cpu.dtb.data_accesses 2065 # DTB accesses
+system.cpu.itb.fetch_hits 6464 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6468 # ITB accesses
+system.cpu.itb.fetch_accesses 6481 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -305,90 +304,90 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 405501 # number of cpu cycles simulated
+system.cpu.numCycles 405365 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6440 # Number of instructions committed
-system.cpu.committedOps 6440 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses
+system.cpu.committedInsts 6453 # Number of instructions committed
+system.cpu.committedOps 6453 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6368 # number of integer instructions
+system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6380 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8380 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4614 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8392 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4621 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2063 # number of memory refs
-system.cpu.num_load_insts 1195 # Number of load instructions
+system.cpu.num_mem_refs 2065 # number of memory refs
+system.cpu.num_load_insts 1197 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 405501 # Number of busy cycles
+system.cpu.num_busy_cycles 405365 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1054 # Number of branches fetched
+system.cpu.Branches 1060 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction
-system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6450 # Class of executed instruction
-system.membus.trans_dist::ReadReq 7639 # Transaction distribution
-system.membus.trans_dist::ReadResp 7638 # Transaction distribution
+system.cpu.op_class::total 6463 # Class of executed instruction
+system.membus.trans_dist::ReadReq 7654 # Transaction distribution
+system.membus.trans_dist::ReadResp 7653 # Transaction distribution
system.membus.trans_dist::WriteReq 865 # Transaction distribution
system.membus.trans_dist::WriteResp 865 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12901 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4106 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 17007 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25800 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15524 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 41324 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12927 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4110 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 17037 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25852 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15540 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 41392 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 8504 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.758584 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.427967 # Request fanout histogram
+system.membus.snoop_fanout::samples 8519 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.758775 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.427852 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2053 24.14% 24.14% # Request fanout histogram
-system.membus.snoop_fanout::1 6451 75.86% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2055 24.12% 24.12% # Request fanout histogram
+system.membus.snoop_fanout::1 6464 75.88% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 8504 # Request fanout histogram
-system.membus.reqLayer0.occupancy 9369000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 8519 # Request fanout histogram
+system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
-system.membus.respLayer0.occupancy 14662500 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 14690750 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 3.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3576750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3574500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
index 66f02e253..2d8c24695 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
@@ -94,7 +94,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -136,7 +135,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -220,6 +218,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@@ -245,7 +244,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -356,6 +354,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
index e33184bae..33f584256 100755
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
@@ -1,14 +1,16 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:14
-gem5 executing on zizzer, pid 34037
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:56:34
+gem5 executing on phenom, pid 28126
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 61610000 because target called exit()
+Exiting @ tick 61470000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
index f030be200..b37d8b5b7 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000062 # Number of seconds simulated
-sim_ticks 61610000 # Number of ticks simulated
-final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000061 # Number of seconds simulated
+sim_ticks 61470000 # Number of ticks simulated
+final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98323 # Simulator instruction rate (inst/s)
-host_op_rate 98283 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 939896452 # Simulator tick rate (ticks/s)
-host_mem_usage 618136 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-sim_insts 6440 # Number of instructions simulated
-sim_ops 6440 # Number of ops (including micro ops) simulated
+host_inst_rate 62593 # Simulator instruction rate (inst/s)
+host_op_rate 62569 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 595804848 # Simulator tick rate (ticks/s)
+host_mem_usage 614668 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+sim_insts 6453 # Number of instructions simulated
+sim_ops 6453 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
@@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu
system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst 289442004 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data 174914592 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total 464356597 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst 289442004 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total 289442004 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst 289442004 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data 174914592 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total 464356597 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs 446 # Number of read requests accepted
system.mem_ctrl.writeReqs 0 # Number of write requests accepted
system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe
system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrl.totGap 61360000 # Total gap between requests
+system.mem_ctrl.totGap 61220000 # Total gap between requests
system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2)
@@ -187,88 +187,88 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean 180.864884 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev 259.243949 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127 27 28.42% 28.42% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255 31 32.63% 61.05% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383 11 11.58% 72.63% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511 8 8.42% 81.05% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean 270.821053 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean 180.792132 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev 259.793616 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127 28 29.47% 29.47% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255 29 30.53% 60.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383 12 12.63% 72.63% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511 9 9.47% 82.11% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639 5 5.26% 87.37% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation
-system.mem_ctrl.totQLat 3464500 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 11827000 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totQLat 3294500 # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat 11657000 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat 7386.77 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat 26136.77 # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW 464.36 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys 464.36 # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead 3.62 # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtil 3.63 # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead 3.63 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads
+system.mem_ctrl.readRowHits 341 # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate 76.46 # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes
-system.mem_ctrl.avgGap 137578.48 # Average gap between requests
-system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ)
+system.mem_ctrl.avgGap 137264.57 # Average gap between requests
+system.mem_ctrl.pageHitRate 76.46 # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy 1591200 # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy 37159155 # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy 262500 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy 43032375 # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower 785.782110 # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE 256750 # Time in different power states
+system.mem_ctrl_0.actBackEnergy 37059120 # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy 350250 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.totalEnergy 43039575 # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower 785.913583 # Core power per rank (mW)
+system.mem_ctrl_0.memoryStateTime::IDLE 388750 # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT 52700750 # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT 52568750 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrl_1.actEnergy 393120 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy 214500 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy 210375 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy 35929665 # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy 1341000 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy 42928005 # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower 783.876287 # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE 2295000 # Time in different power states
+system.mem_ctrl_1.actBackEnergy 35948475 # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW)
+system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT 51042000 # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1188 # DTB read hits
+system.cpu.dtb.read_hits 1190 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1195 # DTB read accesses
+system.cpu.dtb.read_accesses 1197 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2053 # DTB hits
+system.cpu.dtb.data_hits 2055 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2063 # DTB accesses
-system.cpu.itb.fetch_hits 6451 # ITB hits
+system.cpu.dtb.data_accesses 2065 # DTB accesses
+system.cpu.itb.fetch_hits 6464 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6468 # ITB accesses
+system.cpu.itb.fetch_accesses 6481 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -282,87 +282,87 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 61610 # number of cpu cycles simulated
+system.cpu.numCycles 61470 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6440 # Number of instructions committed
-system.cpu.committedOps 6440 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses
+system.cpu.committedInsts 6453 # Number of instructions committed
+system.cpu.committedOps 6453 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6368 # number of integer instructions
+system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6380 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8380 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4614 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8392 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4621 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2063 # number of memory refs
-system.cpu.num_load_insts 1195 # Number of load instructions
+system.cpu.num_mem_refs 2065 # number of memory refs
+system.cpu.num_load_insts 1197 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 61610 # Number of busy cycles
+system.cpu.num_busy_cycles 61470 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1054 # Number of branches fetched
+system.cpu.Branches 1060 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction
-system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6450 # Class of executed instruction
+system.cpu.op_class::total 6463 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4274 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4274 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1093 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1093 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1885 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1885 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1885 # number of overall hits
-system.cpu.dcache.overall_hits::total 1885 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits
+system.cpu.dcache.overall_hits::total 1887 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
@@ -371,38 +371,38 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n
system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.dcache.overall_misses::total 168 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9733000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9733000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 7588000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 7588000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 17321000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 17321000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 17321000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 17321000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1188 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1188 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 10102000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 7278000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 7278000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 17380000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 17380000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 17380000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 17380000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2053 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2053 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2053 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2053 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.081831 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.081831 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.081831 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.081831 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102452.631579 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 102452.631579 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103945.205479 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 103945.205479 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 103101.190476 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 103101.190476 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 106336.842105 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 106336.842105 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99698.630137 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 99698.630137 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 103452.380952 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -419,82 +419,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9543000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9543000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7442000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7442000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16985000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 16985000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16985000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 16985000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079966 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079966 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.081831 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.081831 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100452.631579 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100452.631579 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101945.205479 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101945.205479 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 62 # number of replacements
-system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 13183 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 13183 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 6170 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 6170 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 6170 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 6170 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 6170 # number of overall hits
-system.cpu.icache.overall_hits::total 6170 # number of overall hits
+system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 13209 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits
+system.cpu.icache.overall_hits::total 6183 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses
system.cpu.icache.overall_misses::total 281 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 6451 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 6451 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 6451 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043559 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.043559 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.043559 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -509,24 +509,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281
system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -564,16 +564,16 @@ system.l2bus.respLayer0.utilization 1.4 # La
system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.l2cache.tags.replacements 0 # number of replacements
-system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use
+system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use
system.l2cache.tags.total_refs 65 # Total number of references to valid blocks.
system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks.
system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy
+system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor
+system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor
+system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy
system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
@@ -597,17 +597,17 @@ system.l2cache.demand_misses::total 446 # nu
system.l2cache.overall_misses::cpu.inst 278 # number of overall misses
system.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.l2cache.overall_misses::total 446 # number of overall misses
-system.l2cache.ReadExReq_miss_latency::cpu.data 7223000 # number of ReadExReq miss cycles
-system.l2cache.ReadExReq_miss_latency::total 7223000 # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26711000 # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.data 9258000 # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total 35969000 # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst 26711000 # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::cpu.data 16481000 # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total 43192000 # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst 26711000 # number of overall miss cycles
-system.l2cache.overall_miss_latency::cpu.data 16481000 # number of overall miss cycles
-system.l2cache.overall_miss_latency::total 43192000 # number of overall miss cycles
+system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles
+system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles
+system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles
+system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles
+system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles
+system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles
system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses)
@@ -630,17 +630,17 @@ system.l2cache.demand_miss_rate::total 0.993318 # mi
system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses
system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses
-system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98945.205479 # average ReadExReq miss latency
-system.l2cache.ReadExReq_avg_miss_latency::total 98945.205479 # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96082.733813 # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97452.631579 # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 96431.635389 # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency
-system.l2cache.demand_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 96843.049327 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 96843.049327 # average overall miss latency
+system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency
+system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency
+system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
+system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
+system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency
system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -660,17 +660,17 @@ system.l2cache.demand_mshr_misses::total 446 # nu
system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
-system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5763000 # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_latency::total 5763000 # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21151000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7358000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total 28509000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst 21151000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.data 13121000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total 34272000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst 21151000 # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.data 13121000 # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total 34272000 # number of overall MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses
@@ -682,17 +682,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.993318 #
system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78945.205479 # average ReadExReq mshr miss latency
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78945.205479 # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76082.733813 # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77452.631579 # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76431.635389 # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 373 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
index 7660b2f8f..59bad1d00 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
@@ -224,6 +224,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr
index b3b7d2ff9..8e03cc523 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr
@@ -1,3 +1,2 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
index 0bd088620..f1e009cf1 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
@@ -1,14 +1,16 @@
+Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:17:41
-gem5 started Jan 21 2016 14:18:13
-gem5 executing on zizzer, pid 60583
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
+gem5 compiled Mar 14 2016 22:04:10
+gem5 started Mar 14 2016 22:06:34
+gem5 executing on phenom, pid 29862
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 367783000 because target called exit()
+Exiting @ tick 368887000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
index e03fcae5a..4088c6bf9 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
@@ -1,48 +1,48 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000368 # Number of seconds simulated
-sim_ticks 367783000 # Number of ticks simulated
-final_tick 367783000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000369 # Number of seconds simulated
+sim_ticks 368887000 # Number of ticks simulated
+final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 91194 # Simulator instruction rate (inst/s)
-host_op_rate 91153 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5958550453 # Simulator tick rate (ticks/s)
-host_mem_usage 611392 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-sim_insts 5624 # Number of instructions simulated
-sim_ops 5624 # Number of ops (including micro ops) simulated
+host_inst_rate 25687 # Simulator instruction rate (inst/s)
+host_op_rate 25686 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1679592961 # Simulator tick rate (ticks/s)
+host_mem_usage 607900 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
+sim_insts 5641 # Number of instructions simulated
+sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrl.bytes_read::cpu.inst 22500 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::cpu.data 4289 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::total 26789 # Number of bytes read from this memory
-system.mem_ctrl.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory
+system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory
+system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory
+system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory
+system.mem_ctrl.bytes_inst_read::cpu.inst 22568 # Number of instructions bytes read from this memory
+system.mem_ctrl.bytes_inst_read::total 22568 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_written::cpu.data 3601 # Number of bytes written to this memory
system.mem_ctrl.bytes_written::total 3601 # Number of bytes written to this memory
-system.mem_ctrl.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::cpu.data 1132 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::total 6757 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::cpu.inst 5642 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::cpu.data 1135 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory
system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory
system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst 61177379 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data 11661768 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total 72839147 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst 61177379 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total 61177379 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data 9791100 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total 9791100 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst 61177379 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data 21452868 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total 82630247 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.readReqs 6758 # Number of read requests accepted
+system.mem_ctrl.bw_read::cpu.inst 61178627 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data 11659397 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total 72838024 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst 61178627 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total 61178627 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::cpu.data 9761797 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::total 9761797 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst 61178627 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data 21421194 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total 82599821 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.readReqs 6778 # Number of read requests accepted
system.mem_ctrl.writeReqs 901 # Number of write requests accepted
-system.mem_ctrl.readBursts 6758 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM 426368 # Total number of bytes read from DRAM
+system.mem_ctrl.bytesReadDRAM 427648 # Total number of bytes read from DRAM
system.mem_ctrl.bytesReadWrQ 6144 # Total number of bytes read from write queue
system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM
-system.mem_ctrl.bytesReadSys 26793 # Total read bytes from the system interface side
+system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side
system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side
system.mem_ctrl.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.mergedWrBursts 807 # Number of DRAM write bursts merged with an existing one
@@ -56,12 +56,12 @@ system.mem_ctrl.perBankRdBursts::5 18 # Pe
system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::7 518 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::9 1211 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::11 346 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::13 396 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::14 1409 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::15 50 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
@@ -81,10 +81,10 @@ system.mem_ctrl.perBankWrBursts::14 19 # Pe
system.mem_ctrl.perBankWrBursts::15 2 # Per bank write bursts
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrl.totGap 367707000 # Total gap between requests
+system.mem_ctrl.totGap 368811000 # Total gap between requests
system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2)
system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::2 6678 # Read request sizes (log2)
+system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2)
system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
@@ -96,7 +96,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr
system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0 6662 # What read queue length does an incoming req see
+system.mem_ctrl.rdQLenPdf::0 6682 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -192,27 +192,27 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh
system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples 842 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean 509.263658 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean 293.556275 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev 414.582189 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127 268 31.83% 31.83% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255 81 9.62% 41.45% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383 48 5.70% 47.15% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511 49 5.82% 52.97% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639 36 4.28% 57.24% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767 49 5.82% 63.06% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895 19 2.26% 65.32% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023 21 2.49% 67.81% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151 271 32.19% 100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total 842 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean 506.270907 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean 291.216794 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev 415.367861 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127 272 32.04% 32.04% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255 76 8.95% 40.99% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383 61 7.18% 48.17% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511 46 5.42% 53.59% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639 36 4.24% 57.83% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767 42 4.95% 62.78% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895 24 2.83% 65.61% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 67.37% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151 277 32.63% 100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation
system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean 1344.750000 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean 1258.849963 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev 502.036104 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::mean 1349.750000 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::gmean 1262.645152 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::stdev 506.185325 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::640-703 1 25.00% 25.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1600-1663 1 25.00% 75.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes
system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads
@@ -220,55 +220,55 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr
system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat 27926000 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 152838500 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat 33310000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 4191.83 # Average queueing delay per DRAM burst
+system.mem_ctrl.totQLat 28067250 # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat 153354750 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totBusLat 33410000 # Total ticks spent in databus transfers
+system.mem_ctrl.avgQLat 4200.43 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 22941.83 # Average memory access latency per DRAM burst
+system.mem_ctrl.avgMemAccLat 22950.43 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 1159.29 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW 11.14 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrl.avgWrBW 11.10 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 72.85 # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys 9.79 # Average system write bandwidth in MiByte/s
+system.mem_ctrl.avgWrBWSys 9.76 # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil 9.14 # Data bus utilization in percentage
system.mem_ctrl.busUtilRead 9.06 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen 23.24 # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits 5822 # Number of row buffer hits during reads
+system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing
+system.mem_ctrl.readRowHits 5834 # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits 58 # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate 87.39 # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate 87.31 # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate 61.70 # Row buffer hit rate for writes
-system.mem_ctrl.avgGap 48009.79 # Average gap between requests
-system.mem_ctrl.pageHitRate 87.03 # Row buffer hit rate, read and write combined
+system.mem_ctrl.avgGap 48028.52 # Average gap between requests
+system.mem_ctrl.pageHitRate 86.95 # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy 1058400 # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy 577500 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy 8821800 # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.readEnergy 8806200 # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy 136778625 # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy 99747000 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy 270924525 # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower 739.798888 # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE 164402500 # Time in different power states
+system.mem_ctrl_0.actBackEnergy 143993115 # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy 93418500 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.totalEnergy 271794915 # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower 742.175615 # Core power per rank (mW)
+system.mem_ctrl_0.memoryStateTime::IDLE 153996500 # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT 189605000 # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT 200230500 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.actEnergy 5344920 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy 2916375 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy 42907800 # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy 375840 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy 246879540 # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy 3167250 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy 325423935 # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower 888.617467 # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE 3404750 # Time in different power states
+system.mem_ctrl_1.actBackEnergy 246623040 # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy 3392250 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.totalEnergy 325462545 # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower 888.722897 # Core power per rank (mW)
+system.mem_ctrl_1.memoryStateTime::IDLE 3452250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF 12220000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT 350602750 # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT 350555250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -289,90 +289,90 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
-system.cpu.numCycles 367783 # number of cpu cycles simulated
+system.cpu.numCycles 368887 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5624 # Number of instructions committed
-system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
+system.cpu.committedInsts 5641 # Number of instructions committed
+system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_func_calls 190 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4944 # number of integer instructions
+system.cpu.num_func_calls 191 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
+system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
+system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_mem_refs 2034 # number of memory refs
-system.cpu.num_load_insts 1132 # Number of load instructions
+system.cpu.num_mem_refs 2037 # number of memory refs
+system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 367783 # Number of busy cycles
+system.cpu.num_busy_cycles 368887 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 883 # Number of branches fetched
-system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
-system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
-system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
-system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
+system.cpu.Branches 886 # Number of branches fetched
+system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
+system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
+system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
+system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5625 # Class of executed instruction
-system.membus.trans_dist::ReadReq 6758 # Transaction distribution
-system.membus.trans_dist::ReadResp 6757 # Transaction distribution
+system.cpu.op_class::total 5642 # Class of executed instruction
+system.membus.trans_dist::ReadReq 6778 # Transaction distribution
+system.membus.trans_dist::ReadResp 6777 # Transaction distribution
system.membus.trans_dist::WriteReq 901 # Transaction distribution
system.membus.trans_dist::WriteResp 901 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11251 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 15317 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22500 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7890 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11285 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4072 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 15357 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22568 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7902 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30470 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 7659 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.734561 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.441596 # Request fanout histogram
+system.membus.snoop_fanout::samples 7679 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.734861 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.441436 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2033 26.54% 26.54% # Request fanout histogram
-system.membus.snoop_fanout::1 5626 73.46% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2036 26.51% 26.51% # Request fanout histogram
+system.membus.snoop_fanout::1 5643 73.49% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 7659 # Request fanout histogram
-system.membus.reqLayer0.occupancy 8560000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 7679 # Request fanout histogram
+system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
-system.membus.respLayer0.occupancy 12820000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 12857500 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 3.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3545250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3555500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
index 1fc2588a9..9caeea038 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
@@ -94,7 +94,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -136,7 +135,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -222,6 +220,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@@ -247,7 +246,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -358,6 +356,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr
index b3b7d2ff9..8e03cc523 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr
@@ -1,3 +1,2 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
index 3d3991862..cda55876d 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:17:41
-gem5 started Jan 21 2016 14:18:14
-gem5 executing on zizzer, pid 60586
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
+gem5 compiled Mar 14 2016 22:04:10
+gem5 started Mar 14 2016 22:06:34
+gem5 executing on phenom, pid 29863
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
index 8a196fe6c..c1870ce65 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,13 +4,13 @@ sim_seconds 0.000059 # Nu
sim_ticks 58892000 # Number of ticks simulated
final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 88343 # Simulator instruction rate (inst/s)
-host_op_rate 88311 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 924415589 # Simulator tick rate (ticks/s)
-host_mem_usage 616028 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-sim_insts 5624 # Number of instructions simulated
-sim_ops 5624 # Number of ops (including micro ops) simulated
+host_inst_rate 44023 # Simulator instruction rate (inst/s)
+host_op_rate 44007 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 459268108 # Simulator tick rate (ticks/s)
+host_mem_usage 612532 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+sim_insts 5641 # Number of instructions simulated
+sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
@@ -199,12 +199,12 @@ system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # B
system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
-system.mem_ctrl.totQLat 3878500 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 11941000 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 9019.77 # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 27769.77 # Average memory access latency per DRAM burst
+system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s
@@ -271,84 +271,84 @@ system.cpu.workload.num_syscalls 7 # Nu
system.cpu.numCycles 58892 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5624 # Number of instructions committed
-system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
+system.cpu.committedInsts 5641 # Number of instructions committed
+system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_func_calls 190 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4944 # number of integer instructions
+system.cpu.num_func_calls 191 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
+system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
+system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_mem_refs 2034 # number of memory refs
-system.cpu.num_load_insts 1132 # Number of load instructions
+system.cpu.num_mem_refs 2037 # number of memory refs
+system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 58892 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 883 # Number of branches fetched
-system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
-system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
-system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
-system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
+system.cpu.Branches 886 # Number of branches fetched
+system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
+system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
+system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
+system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5625 # Class of executed instruction
+system.cpu.op_class::total 5642 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 86.277492 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 86.277492 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.084255 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.084255 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
-system.cpu.dcache.overall_hits::total 1896 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
+system.cpu.dcache.overall_hits::total 1899 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
@@ -365,22 +365,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 14174000
system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency
@@ -413,14 +413,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000
system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency
@@ -431,56 +431,56 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 94 # number of replacements
-system.cpu.icache.tags.tagsinuse 110.157629 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 5329 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 17.942761 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 110.157629 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.430303 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.430303 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 11549 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 11549 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 5329 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 5329 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 5329 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 5329 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 5329 # number of overall hits
-system.cpu.icache.overall_hits::total 5329 # number of overall hits
+system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 11583 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits
+system.cpu.icache.overall_hits::total 5346 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 297 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses
system.cpu.icache.overall_misses::total 297 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 30270000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 30270000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 30270000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 30270000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 30270000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 30270000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052791 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.052791 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.052791 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.052791 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.052791 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.052791 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101919.191919 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 101919.191919 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 101919.191919 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 101919.191919 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052632 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.052632 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -495,24 +495,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 297
system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29676000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 29676000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29676000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 29676000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29676000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 29676000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052791 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.052791 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.052791 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99919.191919 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99919.191919 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter.
system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -550,16 +550,16 @@ system.l2bus.respLayer0.utilization 1.5 # La
system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%)
system.l2cache.tags.replacements 0 # number of replacements
-system.l2cache.tags.tagsinuse 183.881600 # Cycle average of tags in use
+system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use
system.l2cache.tags.total_refs 98 # Total number of references to valid blocks.
system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks.
system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst 130.357827 # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data 53.523773 # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst 0.031826 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data 0.013067 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total 0.044893 # Average percentage of cache occupancy
+system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor
+system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor
+system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy
system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
@@ -585,15 +585,15 @@ system.l2cache.overall_misses::cpu.data 137 # nu
system.l2cache.overall_misses::total 430 # number of overall misses
system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles
system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28701000 # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total 37176000 # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst 28701000 # number of demand (read+write) miss cycles
+system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles
+system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total 42190000 # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst 28701000 # number of overall miss cycles
+system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles
+system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles
system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles
-system.l2cache.overall_miss_latency::total 42190000 # number of overall miss cycles
+system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles
system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses)
@@ -618,15 +618,15 @@ system.l2cache.overall_miss_rate::cpu.data 1 #
system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency
system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97955.631399 # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 97831.578947 # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency
+system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 98116.279070 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency
+system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 98116.279070 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency
system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -648,15 +648,15 @@ system.l2cache.overall_mshr_misses::cpu.data 137
system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22841000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total 29576000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst 22841000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total 33590000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst 22841000 # number of overall MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total 33590000 # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses
@@ -670,15 +670,15 @@ system.l2cache.overall_mshr_miss_rate::cpu.data 1
system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77955.631399 # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77831.578947 # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 380 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution