diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/se/03.learning-gem5 | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/se/03.learning-gem5')
10 files changed, 1581 insertions, 1522 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index 9f33ca572..f8c482cd0 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000405 # Number of seconds simulated -sim_ticks 405365000 # Number of ticks simulated -final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000415 # Number of seconds simulated +sim_ticks 414695000 # Number of ticks simulated +final_tick 414695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 357720 # Simulator instruction rate (inst/s) -host_op_rate 357500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22445039511 # Simulator tick rate (ticks/s) -host_mem_usage 631720 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 187951 # Simulator instruction rate (inst/s) +host_op_rate 187881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12069868237 # Simulator tick rate (ticks/s) +host_mem_usage 635076 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory @@ -26,63 +26,63 @@ system.mem_ctrl.num_reads::cpu.data 1190 # Nu system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 63774623 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 21817374 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 85591997 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 63774623 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 63774623 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 16518446 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 16518446 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 63774623 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 38335821 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 102110444 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 62339792 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 21326517 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 83666309 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 62339792 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 62339792 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 16146807 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 16146807 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 62339792 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 37473324 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 99813116 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 7654 # Number of read requests accepted system.mem_ctrl.writeReqs 865 # Number of write requests accepted system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 478016 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 11840 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 747 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 746 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 763 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 766 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 253 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 1430 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 1431 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 8 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 26 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 3 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 21 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 43 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 18 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 405289000 # Total gap between requests +system.mem_ctrl.totGap 414618000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 809 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 7469 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -151,7 +151,7 @@ system.mem_ctrl.wrQLenPdf::18 7 # Wh system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 6 # What write queue length does an incoming req see @@ -193,86 +193,87 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 762 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 634.288714 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 419.900652 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 405.302633 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 146 19.16% 19.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 69 9.06% 28.22% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 39 5.12% 33.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 43 5.64% 38.98% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 44 5.77% 44.75% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 27 3.54% 48.29% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 31 4.07% 52.36% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 30 3.94% 56.30% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 333 43.70% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 762 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 765 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 630.044444 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 420.142008 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 402.263677 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 142 18.56% 18.56% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 72 9.41% 27.97% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 39 5.10% 33.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 50 6.54% 39.61% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 49 6.41% 46.01% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 26 3.40% 49.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 27 3.53% 52.94% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 39 5.10% 58.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 321 41.96% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 765 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1203.833333 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1052.985580 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 699.444184 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::896-1023 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1152-1279 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2432-2559 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1155.166667 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1053.155116 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 490.786070 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1343 1 16.67% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1728-1791 1 16.67% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 26088750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 165982500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3496.68 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 26666250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 166710000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 37345000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3570.26 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22246.68 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1177.96 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 15.16 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 85.60 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 16.52 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 22320.26 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1152.69 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 14.82 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 83.68 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 16.15 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.32 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.20 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 9.12 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.01 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 24.34 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 6706 # Number of row buffer hits during reads +system.mem_ctrl.avgWrQLen 22.92 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 6707 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 88 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.88 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 74.58 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47574.72 # Average gap between requests -system.mem_ctrl.pageHitRate 89.64 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3333960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1819125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37284000 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 168480 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 262765440 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 12591750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 344407875 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 850.082840 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 17896000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 13520000 # Time in different power states +system.mem_ctrl.readRowHitRate 89.80 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 73.95 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 48669.80 # Average gap between requests +system.mem_ctrl.pageHitRate 89.55 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3409560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1860375 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 37159200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 187920 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 262129320 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 17820750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 349520805 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 846.438251 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 26708250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 13780000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 373743250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 372456750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 2426760 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1324125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 20872800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 453600 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 229562370 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 41716500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 322801275 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 796.754927 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 67586500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 13520000 # Time in different power states +system.mem_ctrl_1.actEnergy 2373840 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1295250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 20833800 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 434160 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 231001335 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 45144000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 328036065 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 794.350717 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 73389500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 13780000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 324052250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 325838500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -306,8 +307,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 405365000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 405365 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 414695000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 414695 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -326,7 +327,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 405365 # Number of busy cycles +system.cpu.num_busy_cycles 414695 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -365,7 +366,13 @@ system.cpu.op_class::MemWrite 868 13.43% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7654 # Transaction distribution system.membus.trans_dist::ReadResp 7653 # Transaction distribution system.membus.trans_dist::WriteReq 865 # Transaction distribution @@ -379,20 +386,20 @@ system.membus.pkt_size::total 41392 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 8519 # Request fanout histogram -system.membus.snoop_fanout::mean 0.758775 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.427852 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2055 24.12% 24.12% # Request fanout histogram -system.membus.snoop_fanout::1 6464 75.88% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 8519 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 8519 # Request fanout histogram system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 14690750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3574500 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 14691750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3578000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 674c577ef..1f58ca472 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000061 # Number of seconds simulated -sim_ticks 61470000 # Number of ticks simulated -final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000062 # Number of seconds simulated +sim_ticks 62213000 # Number of ticks simulated +final_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 601148 # Simulator instruction rate (inst/s) -host_op_rate 600523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5715150644 # Simulator tick rate (ticks/s) -host_mem_usage 635816 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 276862 # Simulator instruction rate (inst/s) +host_op_rate 276760 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2667377590 # Simulator tick rate (ticks/s) +host_mem_usage 639424 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 289442004 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 174914592 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 464356597 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 289442004 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 289442004 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 289442004 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 174914592 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 464356597 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 446 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 61220000 # Total gap between requests +system.mem_ctrl.totGap 61962000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -188,69 +188,69 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 270.821053 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 180.792132 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 259.793616 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 28 29.47% 29.47% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 29 30.53% 60.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 12 12.63% 72.63% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 9 9.47% 82.11% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 5 5.26% 87.37% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3294500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11657000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3590750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7386.77 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26136.77 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 464.36 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 464.36 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.63 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.63 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 341 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.46 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 137264.57 # Average gap between requests -system.mem_ctrl.pageHitRate 76.46 # Row buffer hit rate, read and write combined +system.mem_ctrl.avgGap 138928.25 # Average gap between requests +system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1591200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 37059120 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 350250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 43039575 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 785.913583 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 388750 # Time in different power states +system.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 52568750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 35948475 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states +system.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -284,8 +284,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 61470000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61470 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 62213 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -304,7 +304,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61470 # Number of busy cycles +system.cpu.num_busy_cycles 62213 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -343,23 +343,23 @@ system.cpu.op_class::MemWrite 868 13.43% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -376,14 +376,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10102000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7278000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7278000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17380000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17380000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17380000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17380000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -400,14 +400,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 106336.842105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 106336.842105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99698.630137 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 99698.630137 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 103452.380952 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,14 +422,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -438,31 +438,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses system.cpu.icache.tags.data_accesses 13209 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits @@ -475,12 +475,12 @@ system.cpu.icache.demand_misses::cpu.inst 281 # n system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses @@ -493,12 +493,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,31 +511,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281 system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 376 # Transaction distribution system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -566,25 +566,25 @@ system.l2bus.respLayer0.occupancy 843000 # La system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id +system.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id +system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4534 # Number of tag accesses system.l2cache.tags.data_accesses 4534 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -602,17 +602,17 @@ system.l2cache.demand_misses::total 446 # nu system.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.l2cache.overall_misses::cpu.data 168 # number of overall misses system.l2cache.overall_misses::total 446 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) @@ -635,17 +635,17 @@ system.l2cache.demand_miss_rate::total 0.993318 # mi system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -663,17 +663,17 @@ system.l2cache.demand_mshr_misses::total 446 # nu system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses @@ -685,18 +685,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.993318 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -719,7 +725,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2375000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index b0e38a814..670cfd0c1 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000326 # Number of seconds simulated -sim_ticks 325849000 # Number of ticks simulated -final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000333 # Number of seconds simulated +sim_ticks 332645000 # Number of ticks simulated +final_tick 332645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174378 # Simulator instruction rate (inst/s) -host_op_rate 201529 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11371603109 # Simulator tick rate (ticks/s) -host_mem_usage 647324 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 141116 # Simulator instruction rate (inst/s) +host_op_rate 163173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9403646091 # Simulator tick rate (ticks/s) +host_mem_usage 651444 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.mem_ctrl.num_reads::cpu.data 1061 # Nu system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 61709565 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14337930 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 76047494 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 61709565 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 61709565 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 11342677 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 11342677 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 61709565 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 25680607 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 87390172 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 60448827 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 14045003 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 74493830 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 60448827 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 60448827 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 11110944 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 11110944 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 60448827 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 25155947 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 85604774 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6089 # Number of read requests accepted system.mem_ctrl.writeReqs 936 # Number of write requests accepted system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 384000 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 3072 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadDRAM 383296 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6400 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 3696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 856 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 855 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 911 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 1454 # Per bank write bursts @@ -58,8 +58,8 @@ system.mem_ctrl.perBankRdBursts::6 487 # Pe system.mem_ctrl.perBankRdBursts::7 206 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 42 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 155 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 194 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 431 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 192 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 422 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 108 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 36 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.mem_ctrl.perBankWrBursts::7 0 # Pe system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 30 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 46 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 325773000 # Total gap between requests +system.mem_ctrl.totGap 332568000 # Total gap between requests system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 5991 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 5980 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 9 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -161,7 +161,7 @@ system.mem_ctrl.wrQLenPdf::28 4 # Wh system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 3 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,85 +193,86 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 495 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 775.886869 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 648.412049 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 330.044561 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 19 3.84% 3.84% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 31 6.26% 10.10% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 37 7.47% 17.58% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 33 6.67% 24.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 20 4.04% 28.28% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 33 6.67% 34.95% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 27 5.45% 40.40% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 25 5.05% 45.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 270 54.55% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 495 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1299.666667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1199.462709 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 577.403094 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-703 1 33.33% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1471 1 33.33% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1792-1855 1 33.33% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 3 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads +system.mem_ctrl.bytesPerActivate::samples 498 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 770.698795 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 632.685353 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 340.090332 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 21 4.22% 4.22% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 40 8.03% 12.25% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 36 7.23% 19.48% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 28 5.62% 25.10% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 23 4.62% 29.72% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 25 5.02% 34.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 24 4.82% 39.56% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 28 5.62% 45.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 273 54.82% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 498 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 606.712727 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 3 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 3 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 17801000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 130301000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 30000000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 2966.83 # Average queueing delay per DRAM burst +system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 17899250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 130193000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 2988.69 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21716.83 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1178.46 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 9.43 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 76.06 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 11.34 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 21738.69 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1152.27 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 12.31 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 74.51 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 11.11 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.28 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.21 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 9.10 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.00 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 24.64 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5504 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 44 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.73 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 55.00 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 46373.38 # Average gap between requests -system.mem_ctrl.pageHitRate 91.25 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2782080 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1518000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37915800 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5487 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 91.62 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 47340.64 # Average gap between requests +system.mem_ctrl.pageHitRate 91.42 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2812320 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1534500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 38048400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 212134050 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 5616000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 280816890 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 878.932981 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 6234500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 216770715 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 6219750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 286745205 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 876.139742 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 7265500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 10920000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 303655500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 309110750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 922320 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 503250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 7932600 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.readEnergy 7893600 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 311040 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 182238975 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 31839000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 244598145 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 765.574385 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 52679500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 188416350 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 31092000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 250498080 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 765.387945 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 51038750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 10920000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 265729250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -301,7 +302,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -331,7 +332,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -361,7 +362,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -392,8 +393,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 325849000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 325849 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 332645000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 332645 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -414,7 +415,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 325848.999000 # Number of busy cycles +system.cpu.num_busy_cycles 332644.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -453,7 +454,13 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6078 # Transaction distribution system.membus.trans_dist::ReadResp 6088 # Transaction distribution system.membus.trans_dist::WriteReq 925 # Transaction distribution @@ -470,20 +477,20 @@ system.membus.pkt_size::total 28476 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7025 # Request fanout histogram -system.membus.snoop_fanout::mean 0.715730 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.451098 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1997 28.43% 28.43% # Request fanout histogram -system.membus.snoop_fanout::1 5028 71.57% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7025 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7025 # Request fanout histogram system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 11411750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3326000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11412500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3325250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index b14eb2f25..005f27b4b 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000050 # Number of seconds simulated -sim_ticks 49855000 # Number of ticks simulated -final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 50074000 # Number of ticks simulated +final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 256506 # Simulator instruction rate (inst/s) -host_op_rate 296356 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2557788683 # Simulator tick rate (ticks/s) -host_mem_usage 651420 # Number of bytes of host memory used +host_inst_rate 207988 # Simulator instruction rate (inst/s) +host_op_rate 240459 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2085706484 # Simulator tick rate (ticks/s) +host_mem_usage 655032 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14400 # Nu system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 288837629 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 161749072 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 450586701 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 288837629 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 288837629 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 288837629 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 161749072 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 450586701 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 351 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 49757000 # Total gap between requests +system.mem_ctrl.totGap 49975000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -189,30 +189,30 @@ system.mem_ctrl.wrQLenPdf::62 0 # Wh system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 214.051474 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 262.513782 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,38 +220,38 @@ system.mem_ctrl.readRowHits 274 # Nu system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 141757.83 # Average gap between requests +system.mem_ctrl.avgGap 142378.92 # Average gap between requests system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states +system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -281,7 +281,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -311,7 +311,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +341,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -372,8 +372,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 49855000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 49855 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 50074 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -394,7 +394,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 49854.999000 # Number of busy cycles +system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -433,23 +433,23 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits @@ -470,14 +470,14 @@ system.cpu.dcache.demand_misses::cpu.data 142 # n system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -498,14 +498,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,14 +520,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses @@ -536,31 +536,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses system.cpu.icache.tags.data_accesses 10305 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits @@ -573,12 +573,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses @@ -591,12 +591,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -609,31 +609,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 249 system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -664,25 +664,25 @@ system.l2bus.respLayer0.occupancy 747000 # La system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id +system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id +system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3959 # Number of tag accesses system.l2cache.tags.data_accesses 3959 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits @@ -703,17 +703,17 @@ system.l2cache.demand_misses::total 351 # nu system.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.l2cache.overall_misses::cpu.data 126 # number of overall misses system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) @@ -736,17 +736,17 @@ system.l2cache.demand_miss_rate::total 0.897698 # mi system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -764,17 +764,17 @@ system.l2cache.demand_mshr_misses::total 351 # nu system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses @@ -786,18 +786,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.897698 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -820,7 +826,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 351 # Request fanout histogram system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1865750 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index 54ae8e9b7..60c6ac279 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000369 # Number of seconds simulated -sim_ticks 368887000 # Number of ticks simulated -final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000377 # Number of seconds simulated +sim_ticks 376893000 # Number of ticks simulated +final_tick 376893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 354647 # Simulator instruction rate (inst/s) -host_op_rate 354403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23159010384 # Simulator tick rate (ticks/s) -host_mem_usage 629604 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 173660 # Simulator instruction rate (inst/s) +host_op_rate 173583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11593149844 # Simulator tick rate (ticks/s) +host_mem_usage 632708 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.mem_ctrl.num_reads::cpu.data 1135 # Nu system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 61178627 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 11659397 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 72838024 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 61178627 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 61178627 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 9761797 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 9761797 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 61178627 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 21421194 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 82599821 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 59879064 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 11411727 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 71290791 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 59879064 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 59879064 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 9554436 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 9554436 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 59879064 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 20966163 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 80845227 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6778 # Number of read requests accepted system.mem_ctrl.writeReqs 901 # Number of write requests accepted system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 427648 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 428096 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 807 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 811 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 275 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts @@ -55,15 +55,15 @@ system.mem_ctrl.perBankRdBursts::3 0 # Pe system.mem_ctrl.perBankRdBursts::4 215 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 518 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 519 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 346 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 350 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 50 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 1429 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 49 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts @@ -71,18 +71,18 @@ system.mem_ctrl.perBankWrBursts::3 0 # Pe system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 8 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 8 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 29 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 2 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 30 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 19 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 2 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 14 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 3 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 368811000 # Total gap between requests +system.mem_ctrl.totGap 376816000 # Total gap between requests system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6682 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6689 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -155,10 +155,10 @@ system.mem_ctrl.wrQLenPdf::22 5 # Wh system.mem_ctrl.wrQLenPdf::23 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see @@ -193,26 +193,26 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 506.270907 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 291.216794 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 415.367861 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 272 32.04% 32.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 76 8.95% 40.99% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 61 7.18% 48.17% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 46 5.42% 53.59% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 36 4.24% 57.83% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 42 4.95% 62.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 24 2.83% 65.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 67.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 277 32.63% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 838 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 513.374702 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 298.080754 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 413.335022 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 263 31.38% 31.38% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 85 10.14% 41.53% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 42 5.01% 46.54% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 43 5.13% 51.67% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 44 5.25% 56.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 53 6.32% 63.25% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 15 1.79% 65.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 22 2.63% 67.66% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 271 32.34% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 838 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1349.750000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1262.645152 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 506.185325 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-703 1 25.00% 25.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1522.250000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1505.224255 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 263.075876 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1343 1 25.00% 50.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes @@ -221,57 +221,57 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 28067250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 153354750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 33410000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 4200.43 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 28198000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 153616750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 33445000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 4215.58 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22950.43 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1159.29 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 11.10 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 72.85 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 9.76 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 22965.58 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1135.86 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 10.87 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 71.30 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 9.55 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.14 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.06 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.96 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.87 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5834 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 58 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 87.31 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 61.70 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48028.52 # Average gap between requests -system.mem_ctrl.pageHitRate 86.95 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 1058400 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 577500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl.avgWrQLen 23.23 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5853 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 57 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 87.50 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 63.33 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 49070.97 # Average gap between requests +system.mem_ctrl.pageHitRate 87.18 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 1020600 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 556875 # Energy for precharge commands per rank (pJ) system.mem_ctrl_0.readEnergy 8806200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 143993115 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 93418500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 271794915 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 742.175615 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 153996500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_0.writeEnergy 51840 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 141780375 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 100031250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 276658020 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 739.727326 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 165010500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 200230500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 196602500 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 5344920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 2916375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 42907800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 375840 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 246623040 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 3392250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 325462545 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 888.722897 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 3452250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 42939000 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 362880 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 252188235 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 3192750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 331284930 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 885.747138 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2538750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 12480000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 350555250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 359011750 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -291,8 +291,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368887000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 368887 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 376893000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 376893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -311,7 +311,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 368887 # Number of busy cycles +system.cpu.num_busy_cycles 376893 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -350,7 +350,13 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6778 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution @@ -364,20 +370,20 @@ system.membus.pkt_size::total 30470 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7679 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734861 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441436 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2036 26.51% 26.51% # Request fanout histogram -system.membus.snoop_fanout::1 5643 73.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7679 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7679 # Request fanout histogram system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 12857500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer0.occupancy 12853500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3555500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index c2c263451..27ea6dc01 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000059 # Number of seconds simulated -sim_ticks 58892000 # Number of ticks simulated -final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 59115000 # Number of ticks simulated +final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 557970 # Simulator instruction rate (inst/s) -host_op_rate 557350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5812791438 # Simulator tick rate (ticks/s) -host_mem_usage 633704 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 219311 # Simulator instruction rate (inst/s) +host_op_rate 219196 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2295881155 # Simulator tick rate (ticks/s) +host_mem_usage 637060 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 18752 # Nu system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 318413367 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 148882701 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 467296067 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 318413367 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 318413367 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 318413367 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 148882701 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 467296067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 430 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 58762000 # Total gap between requests +system.mem_ctrl.totGap 58984000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,70 +187,70 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 232.212389 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 169.054443 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 210.567831 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 44 38.94% 65.49% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 17 15.04% 80.53% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 9 7.96% 88.50% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.65 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.65 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 313 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 72.79 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 136655.81 # Average gap between requests -system.mem_ctrl.pageHitRate 72.79 # Row buffer hit rate, read and write combined +system.mem_ctrl.avgGap 137172.09 # Average gap between requests +system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 196560 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 678600 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 26204040 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 9872250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 40618620 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 741.706329 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 17140250 # Time in different power states +system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 36672750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 635040 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 346500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 2425800 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 37227555 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 202500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 44397315 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 810.706261 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 145000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -270,8 +270,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58892000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 58892 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 59115 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -290,7 +290,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 58892 # Number of busy cycles +system.cpu.num_busy_cycles 59115 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -329,23 +329,23 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -362,14 +362,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8910000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8910000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5264000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5264000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14174000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -386,14 +386,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 105280 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 103459.854015 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 103459.854015 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,14 +408,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5164000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5164000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -424,31 +424,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 94 # number of replacements -system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses system.cpu.icache.tags.data_accesses 11583 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits @@ -461,12 +461,12 @@ system.cpu.icache.demand_misses::cpu.inst 297 # n system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses system.cpu.icache.overall_misses::total 297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses @@ -479,12 +479,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,31 +497,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 297 system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 384 # Transaction distribution system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -552,25 +552,25 @@ system.l2bus.respLayer0.occupancy 891000 # La system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id +system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4654 # Number of tag accesses system.l2cache.tags.data_accesses 4654 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits @@ -588,17 +588,17 @@ system.l2cache.demand_misses::total 430 # nu system.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 430 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses) @@ -621,17 +621,17 @@ system.l2cache.demand_miss_rate::total 0.990783 # mi system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,17 +649,17 @@ system.l2cache.demand_mshr_misses::total 430 # nu system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses @@ -671,18 +671,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.990783 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -705,7 +711,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 430 # Request fanout histogram system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2299000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index 81f7b029f..9a120d100 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000333 # Number of seconds simulated -sim_ticks 333033000 # Number of ticks simulated -final_tick 333033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000340 # Number of seconds simulated +sim_ticks 340278000 # Number of ticks simulated +final_tick 340278000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 341593 # Simulator instruction rate (inst/s) -host_op_rate 341350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20477364302 # Simulator tick rate (ticks/s) -host_mem_usage 630048 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 140763 # Simulator instruction rate (inst/s) +host_op_rate 140716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8627820590 # Simulator tick rate (ticks/s) +host_mem_usage 633396 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory @@ -26,42 +26,42 @@ system.mem_ctrl.num_reads::cpu.data 718 # Nu system.mem_ctrl.num_reads::total 6309 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 673 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 673 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 67152504 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 13932553 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 81085058 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 67152504 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 67152504 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 15208703 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 15208703 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 67152504 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 29141256 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 96293761 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 65722733 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 13635909 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 79358642 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 65722733 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 65722733 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 14884888 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 14884888 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 65722733 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 28520798 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 94243530 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6310 # Number of read requests accepted system.mem_ctrl.writeReqs 673 # Number of write requests accepted system.mem_ctrl.readBursts 6310 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 673 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 397376 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6464 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 397824 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6016 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 27008 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 5065 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 551 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 548 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 220 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 84 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 2 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 199 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 1001 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 1005 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 1555 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 876 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 875 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 710 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 348 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 99 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 623 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 56 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 158 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 162 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 200 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 78 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts @@ -69,9 +69,9 @@ system.mem_ctrl.perBankWrBursts::1 0 # Pe system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 14 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 37 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 27 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 17 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 42 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 19 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 5 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts @@ -82,7 +82,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 332957000 # Total gap between requests +system.mem_ctrl.totGap 340201000 # Total gap between requests system.mem_ctrl.readPktSize::0 88 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 2 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 5711 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 604 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6209 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6216 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -155,9 +155,9 @@ system.mem_ctrl.wrQLenPdf::22 7 # Wh system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see @@ -194,23 +194,23 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 569 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 706.024605 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 523.041408 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 385.942790 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 49 8.61% 8.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 76 13.36% 21.97% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 38 6.68% 28.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 27 4.75% 33.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 21 3.69% 37.08% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 21 3.69% 40.77% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 15 2.64% 43.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 706.474517 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 522.857650 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 386.052257 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 51 8.96% 8.96% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 75 13.18% 22.14% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 39 6.85% 29.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 23 4.04% 33.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 22 3.87% 36.91% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 18 3.16% 40.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 19 3.34% 43.41% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::896-1023 24 4.22% 47.63% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 298 52.37% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 569 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 772.166667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 643.154197 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 524.176084 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 772.333333 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 643.216539 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 524.537383 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% # Reads before turning the bus around for writes @@ -222,60 +222,60 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 19522250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 135941000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 31045000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3144.19 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 19583750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 136133750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 31080000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3150.54 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21894.19 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1193.20 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 18.45 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 81.10 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 15.21 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 21900.54 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1169.11 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 18.06 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 79.37 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 14.88 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.47 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.32 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 9.27 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.13 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.14 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 22.95 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5646 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 86 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 90.93 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 70.49 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47681.08 # Average gap between requests -system.mem_ctrl.pageHitRate 90.54 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2676240 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1460250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 29983200 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5657 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 82 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 91.01 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 65.60 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 48718.46 # Average gap between requests +system.mem_ctrl.pageHitRate 90.51 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2653560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1447875 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 30108000 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 505440 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 211046490 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 11241000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 278272140 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 850.250594 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 16881000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 10920000 # Time in different power states +system.mem_ctrl_0.refreshEnergy 21868080 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 217242675 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 10477500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 284303130 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 848.491929 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 15805250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 11180000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 299495250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 311151750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 1587600 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 866250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 17604600 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.actEnergy 1617840 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 882750 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 17635800 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 116640 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 163497375 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 52950750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 257982735 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 788.257041 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 88704750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 10920000 # Time in different power states +system.mem_ctrl_1.refreshEnergy 21868080 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 174520890 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 47944500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 264586500 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 789.680799 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 79696000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 11180000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 229634250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 245540000 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 333033000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 333033 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 340278000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 340278 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -294,7 +294,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 333032.999000 # Number of busy cycles +system.cpu.num_busy_cycles 340277.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -333,7 +333,13 @@ system.cpu.op_class::MemWrite 678 12.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6310 # Transaction distribution system.membus.trans_dist::ReadResp 6309 # Transaction distribution system.membus.trans_dist::WriteReq 673 # Transaction distribution @@ -347,19 +353,19 @@ system.membus.pkt_size::total 32069 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6983 # Request fanout histogram -system.membus.snoop_fanout::mean 0.800802 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.399426 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1391 19.92% 19.92% # Request fanout histogram -system.membus.snoop_fanout::1 5592 80.08% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6983 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6983 # Request fanout histogram system.membus.reqLayer0.occupancy 7656000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 12692250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.8 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer0.occupancy 12692500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) system.membus.respLayer1.occupancy 2298500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 6107833ad..563f4d9b3 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000053 # Number of seconds simulated -sim_ticks 53334000 # Number of ticks simulated -final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000054 # Number of seconds simulated +sim_ticks 53605000 # Number of ticks simulated +final_tick 53605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 532040 # Simulator instruction rate (inst/s) -host_op_rate 531414 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5103257870 # Simulator tick rate (ticks/s) -host_mem_usage 634140 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 205629 # Simulator instruction rate (inst/s) +host_op_rate 205519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1984690430 # Simulator tick rate (ticks/s) +host_mem_usage 637752 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 16448 # Nu system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 306837049 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 163566831 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 470403880 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 306837049 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 306837049 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 306837049 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 163566831 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 470403880 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 394 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 53238000 # Total gap between requests +system.mem_ctrl.totGap 53508000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,78 +187,77 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 93 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 243.612903 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 174.394567 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 202.881901 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::64-127 29 31.18% 31.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-191 15 16.13% 47.31% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::192-255 11 11.83% 59.14% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-319 8 8.60% 67.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::320-383 6 6.45% 74.19% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-447 8 8.60% 82.80% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::448-511 2 2.15% 84.95% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-575 3 3.23% 88.17% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::576-639 6 6.45% 94.62% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-703 2 2.15% 96.77% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 92 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 246.260870 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 176.635417 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 203.037423 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::64-127 28 30.43% 30.43% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-191 15 16.30% 46.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::192-255 11 11.96% 58.70% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-319 8 8.70% 67.39% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::320-383 6 6.52% 73.91% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-447 7 7.61% 81.52% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::448-511 3 3.26% 84.78% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-575 3 3.26% 88.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::576-639 6 6.52% 94.57% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-703 2 2.17% 96.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-831 1 1.09% 97.83% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-959 2 2.17% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 92 # Bytes accessed per row activation +system.mem_ctrl.totQLat 2887500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10275000 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 7328.68 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 26078.68 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 470.40 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 470.40 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.69 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.68 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.68 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 295 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 296 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 75.13 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 135121.83 # Average gap between requests -system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 135807.11 # Average gap between requests +system.mem_ctrl.pageHitRate 75.13 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 378000 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 206250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1614600 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states +system.mem_ctrl_0.actBackEnergy 30461940 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1478250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37190400 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 791.306152 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 2310750 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 43141000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 272160 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 148500 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 29447910 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states +system.mem_ctrl_1.actBackEnergy 29252115 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 2526750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 36303885 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 772.793039 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 5312750 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 41373250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53334000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 53334 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 53605000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 53605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -277,7 +276,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles +system.cpu.num_busy_cycles 53604.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -316,23 +315,23 @@ system.cpu.op_class::MemWrite 678 12.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 83.787726 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 83.787726 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.081824 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.081824 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits @@ -349,14 +348,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13965000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5756000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5756000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8522000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8522000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14278000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14278000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14278000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14278000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -373,14 +372,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102785.714286 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 102785.714286 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103926.829268 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 103926.829268 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 103463.768116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 103463.768116 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,14 +394,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13689000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5644000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5644000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8358000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8358000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14002000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14002000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14002000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14002000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses @@ -411,31 +410,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100785.714286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100785.714286 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101926.829268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101926.829268 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 98.163046 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 98.163046 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.383449 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.383449 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses system.cpu.icache.tags.data_accesses 11443 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits @@ -448,12 +447,12 @@ system.cpu.icache.demand_misses::cpu.inst 259 # n system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26157000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26157000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26157000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26157000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26157000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26157000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses @@ -466,12 +465,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100992.277992 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100992.277992 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100992.277992 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100992.277992 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -484,31 +483,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 259 system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25639000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25639000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98992.277992 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98992.277992 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 315 # Transaction distribution system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution @@ -536,28 +535,28 @@ system.l2bus.snoop_fanout::total 397 # Re system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 200.697345 # Cycle average of tags in use system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id +system.l2cache.tags.occ_blocks::cpu.inst 117.835895 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 82.861451 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.028769 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.020230 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.048998 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id +system.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4130 # Number of tag accesses system.l2cache.tags.data_accesses 4130 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits @@ -578,17 +577,17 @@ system.l2cache.demand_misses::total 394 # nu system.l2cache.overall_misses::cpu.inst 257 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8112000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8112000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24816000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 5453000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 30269000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 24816000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13565000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 38381000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 24816000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13565000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 38381000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) @@ -611,17 +610,17 @@ system.l2cache.demand_miss_rate::total 0.992443 # mi system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98926.829268 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 98926.829268 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96560.311284 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99145.454545 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 97016.025641 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 97413.705584 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 97413.705584 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,17 +638,17 @@ system.l2cache.demand_mshr_misses::total 394 # nu system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6472000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6472000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19676000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4353000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 24029000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19676000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10825000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19676000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10825000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses @@ -661,18 +660,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.992443 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.829268 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.829268 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76560.311284 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79145.454545 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77016.025641 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution system.membus.trans_dist::ReadExResp 82 # Transaction distribution @@ -695,7 +700,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 394 # Request fanout histogram system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2102250 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2102000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index f9a903a5e..7312a839d 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000445 # Number of seconds simulated -sim_ticks 445082000 # Number of ticks simulated -final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000455 # Number of seconds simulated +sim_ticks 454507000 # Number of ticks simulated +final_tick 454507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125099 # Simulator instruction rate (inst/s) -host_op_rate 225788 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9739384878 # Simulator tick rate (ticks/s) -host_mem_usage 648172 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 76712 # Simulator instruction rate (inst/s) +host_op_rate 138489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6101741543 # Simulator tick rate (ticks/s) +host_mem_usage 651776 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory @@ -26,29 +26,29 @@ system.mem_ctrl.num_reads::cpu.data 1084 # Nu system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 130906215 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 16102651 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 147008866 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 130906215 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 130906215 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 16086923 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 16086923 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 130906215 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 32189574 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 163095789 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 128191645 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 15768734 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 143960379 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 128191645 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 128191645 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 15753333 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 15753333 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 128191645 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 31522067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 159713712 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 8367 # Number of read requests accepted system.mem_ctrl.writeReqs 941 # Number of write requests accepted system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadDRAM 524736 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 10752 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 168 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 819 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::0 273 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts @@ -58,13 +58,13 @@ system.mem_ctrl.perBankRdBursts::6 1103 # Pe system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 1055 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 12 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 115 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 6 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts @@ -72,17 +72,17 @@ system.mem_ctrl.perBankWrBursts::4 0 # Pe system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 55 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 29 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 2 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 53 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 23 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 5 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 444958000 # Total gap between requests +system.mem_ctrl.totGap 454381000 # Total gap between requests system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 861 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 8199 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -146,8 +146,8 @@ system.mem_ctrl.wrQLenPdf::13 1 # Wh system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see @@ -155,13 +155,13 @@ system.mem_ctrl.wrQLenPdf::22 7 # Wh system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,94 +194,93 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 625.677267 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 430.153995 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 392.580114 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 141 16.61% 16.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 68 8.01% 24.62% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 71 8.36% 32.98% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 65 7.66% 40.64% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 53 6.24% 46.88% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 45 5.30% 52.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 35 4.12% 56.30% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 58.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 356 41.93% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 622.812721 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 426.803074 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 394.306776 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 142 16.73% 16.73% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 69 8.13% 24.85% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 77 9.07% 33.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 63 7.42% 41.34% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 55 6.48% 47.82% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 39 4.59% 52.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 28 3.30% 55.71% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 21 2.47% 58.19% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 355 41.81% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads +system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1282.333333 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1020.532539 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 764.587906 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::256-383 1 16.67% 16.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::384-511 1 16.67% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1407 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1920-2047 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2048-2175 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 29060250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 182922750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3541.34 # Average queueing delay per DRAM burst +system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 29381000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 183112250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 40995000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3583.49 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22291.34 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1179.97 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 16.10 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 147.01 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 16.09 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 22333.49 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1154.52 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 13.52 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 143.96 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 15.75 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.34 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.22 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.13 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 9.13 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.02 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.11 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.76 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 7369 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.80 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47803.82 # Average gap between requests -system.mem_ctrl.pageHitRate 89.56 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3265920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1782000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 40552200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 77760 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 28987920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 242604540 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 53634750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 370905090 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 835.228387 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 86580500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 14820000 # Time in different power states +system.mem_ctrl.avgWrQLen 23.84 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 7356 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 85 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 69.67 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 48816.18 # Average gap between requests +system.mem_ctrl.pageHitRate 89.42 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3281040 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1790250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 40294800 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 248297130 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 53313000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 376511580 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 833.243697 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 86206500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 15080000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 342689500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 350589750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 3152520 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1720125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 23314200 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 648000 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 28987920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 267116535 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 32133000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 357072300 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 804.078804 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 51572750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 14820000 # Time in different power states +system.mem_ctrl_1.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 23275200 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 583200 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 273625650 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 31095000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 362913120 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 803.149454 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 50725000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 15080000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 377923250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 387261000 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 445082000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 445082 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 454507000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 454507 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -302,7 +301,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 445081.999000 # Number of busy cycles +system.cpu.num_busy_cycles 454506.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -341,7 +340,13 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 8367 # Transaction distribution system.membus.trans_dist::ReadResp 8367 # Transaction distribution system.membus.trans_dist::WriteReq 941 # Transaction distribution @@ -359,20 +364,20 @@ system.membus.pkt_size::total 72591 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 9308 # Request fanout histogram -system.membus.snoop_fanout::mean 0.782445 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.412605 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2025 21.76% 21.76% # Request fanout histogram -system.membus.snoop_fanout::1 7283 78.24% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 9308 # Request fanout histogram system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 16547500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3433750 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 16547250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3431500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index 7d909cf8e..a74924642 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000056 # Number of seconds simulated -sim_ticks 55844000 # Number of ticks simulated -final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 56435000 # Number of ticks simulated +final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197644 # Simulator instruction rate (inst/s) -host_op_rate 356622 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1929610808 # Simulator tick rate (ticks/s) -host_mem_usage 652268 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 125605 # Simulator instruction rate (inst/s) +host_op_rate 226732 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1240265940 # Simulator tick rate (ticks/s) +host_mem_usage 656384 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14656 # Nu system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 262445384 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 154716711 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 417162094 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 262445384 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 262445384 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 262445384 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 154716711 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 417162094 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 364 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 55714000 # Total gap between requests +system.mem_ctrl.totGap 56304000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,78 +187,77 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 115 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 199.234783 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 135.588464 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 217.243914 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 49 42.61% 42.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 34 29.57% 72.17% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 244 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 67.03 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 153060.44 # Average gap between requests -system.mem_ctrl.pageHitRate 67.03 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1240200 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 154681.32 # Average gap between requests +system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 32401080 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 4436250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 42104850 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 768.845267 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 7212250 # Time in different power states +system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 45745250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 567000 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 309375 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 36016020 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 55844000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 55844 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 56435 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -279,7 +278,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 55843.999000 # Number of busy cycles +system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -318,23 +317,23 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits @@ -351,14 +350,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6006000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6006000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8260000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8260000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14266000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14266000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14266000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14266000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) @@ -375,14 +374,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 107250 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 107250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104556.962025 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 104556.962025 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 105674.074074 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -397,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5894000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5894000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8102000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8102000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13996000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13996000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses @@ -413,31 +412,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits @@ -450,12 +449,12 @@ system.cpu.icache.demand_misses::cpu.inst 235 # n system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23702000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23702000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23702000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23702000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23702000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23702000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses @@ -468,12 +467,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100859.574468 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100859.574468 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100859.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -486,31 +485,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 235 system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23232000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23232000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23232000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23232000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -538,28 +537,28 @@ system.l2bus.snoop_fanout::total 370 # Re system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id +system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3788 # Number of tag accesses system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits @@ -577,17 +576,17 @@ system.l2cache.demand_misses::total 364 # nu system.l2cache.overall_misses::cpu.inst 229 # number of overall misses system.l2cache.overall_misses::cpu.data 135 # number of overall misses system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) @@ -610,17 +609,17 @@ system.l2cache.demand_miss_rate::total 0.983784 # mi system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,17 +637,17 @@ system.l2cache.demand_mshr_misses::total 364 # nu system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses @@ -660,18 +659,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.983784 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution @@ -695,8 +700,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 364 # Request fanout histogram system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1952750 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) +system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |