diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/quick/se/03.learning-gem5 | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/03.learning-gem5')
24 files changed, 3658 insertions, 3634 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini index 2d26791e9..34c898798 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini @@ -93,6 +93,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -166,8 +167,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -178,8 +177,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/arm/linux/hello cwd= drivers= @@ -252,10 +249,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout index 40266a5d8..01bb29eda 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:05:23 -gem5 executing on e108600-lin, pid 17594 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:05:51 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55329 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 372284000 because target called exit() +Exiting @ tick 372284000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index d96e2fe55..bf625223f 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -1,510 +1,510 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000372 # Number of seconds simulated -sim_ticks 372284000 # Number of ticks simulated -final_tick 372284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264702 # Simulator instruction rate (inst/s) -host_op_rate 305997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19731375693 # Simulator tick rate (ticks/s) -host_mem_usage 650740 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 4988 # Number of instructions simulated -sim_ops 5770 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1061 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 54012528 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 12549559 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 66562087 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 54012528 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 54012528 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 9927905 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 9927905 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 54012528 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 22477463 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 76489992 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 6089 # Number of read requests accepted -system.mem_ctrl.writeReqs 936 # Number of write requests accepted -system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 383296 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6400 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 3696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 855 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 911 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 1454 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 724 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 364 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 505 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 303 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 487 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 206 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 42 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 155 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 192 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 422 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 108 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 36 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 80 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 46 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 372207000 # Total gap between requests -system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 160 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 16 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 920 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 5980 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 9 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 514 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 749.322957 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 608.037375 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 344.826867 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 514 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 606.712727 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 57609500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 169903250 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9619.22 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28369.22 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1029.58 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 11.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 66.57 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 9.93 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.13 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.04 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5473 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.38 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 52983.20 # Average gap between requests -system.mem_ctrl.pageHitRate 91.19 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2727480 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1438305 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 35364420 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 64999380 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1619520 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 98643060 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 3533760 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 237214005 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 637.183891 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 225396250 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 954000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 133713750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750 # Time in different power states -system.mem_ctrl_1.actEnergy 971040 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 512325 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 7389900 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 334080 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 27658800.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 18607080 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 791520 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 128152530 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 7837920 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 7265340 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 199520535 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 535.934929 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 328663750 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 770000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 11706000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 27971000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 30385000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 372284000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 372284 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4988 # Number of instructions committed -system.cpu.committedOps 5770 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 215 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls -system.cpu.num_int_insts 4977 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 8049 # number of times the integer registers were read -system.cpu.num_int_register_writes 2992 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written -system.cpu.num_mem_refs 2035 # number of memory refs -system.cpu.num_load_insts 1085 # Number of load instructions -system.cpu.num_store_insts 950 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 372283.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1107 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction -system.cpu.op_class::MemWrite 934 16.02% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5831 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6078 # Transaction distribution -system.membus.trans_dist::ReadResp 6088 # Transaction distribution -system.membus.trans_dist::WriteReq 925 # Transaction distribution -system.membus.trans_dist::WriteResp 925 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14049 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28476 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7025 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7025 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7025 # Request fanout histogram -system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer0.occupancy 11413250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3327250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +sim_seconds 0.000372 +sim_ticks 372284000 +final_tick 372284000 +sim_freq 1000000000000 +host_inst_rate 111411 +host_op_rate 128815 +host_tick_rate 8307715104 +host_mem_usage 662496 +host_seconds 0.05 +sim_insts 4988 +sim_ops 5770 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 +system.mem_ctrl.bytes_read::cpu.inst 20108 +system.mem_ctrl.bytes_read::cpu.data 4672 +system.mem_ctrl.bytes_read::total 24780 +system.mem_ctrl.bytes_inst_read::cpu.inst 20108 +system.mem_ctrl.bytes_inst_read::total 20108 +system.mem_ctrl.bytes_written::cpu.data 3696 +system.mem_ctrl.bytes_written::total 3696 +system.mem_ctrl.num_reads::cpu.inst 5027 +system.mem_ctrl.num_reads::cpu.data 1061 +system.mem_ctrl.num_reads::total 6088 +system.mem_ctrl.num_writes::cpu.data 936 +system.mem_ctrl.num_writes::total 936 +system.mem_ctrl.bw_read::cpu.inst 54012528 +system.mem_ctrl.bw_read::cpu.data 12549559 +system.mem_ctrl.bw_read::total 66562087 +system.mem_ctrl.bw_inst_read::cpu.inst 54012528 +system.mem_ctrl.bw_inst_read::total 54012528 +system.mem_ctrl.bw_write::cpu.data 9927905 +system.mem_ctrl.bw_write::total 9927905 +system.mem_ctrl.bw_total::cpu.inst 54012528 +system.mem_ctrl.bw_total::cpu.data 22477463 +system.mem_ctrl.bw_total::total 76489992 +system.mem_ctrl.readReqs 6089 +system.mem_ctrl.writeReqs 936 +system.mem_ctrl.readBursts 6089 +system.mem_ctrl.writeBursts 936 +system.mem_ctrl.bytesReadDRAM 383296 +system.mem_ctrl.bytesReadWrQ 6400 +system.mem_ctrl.bytesWritten 4096 +system.mem_ctrl.bytesReadSys 24784 +system.mem_ctrl.bytesWrittenSys 3696 +system.mem_ctrl.servicedByWrQ 100 +system.mem_ctrl.mergedWrBursts 855 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 911 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+system.cpu.op_class::IntDiv 0 0.00% 65.05% +system.cpu.op_class::FloatAdd 0 0.00% 65.05% +system.cpu.op_class::FloatCmp 0 0.00% 65.05% +system.cpu.op_class::FloatCvt 0 0.00% 65.05% +system.cpu.op_class::FloatMult 0 0.00% 65.05% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% +system.cpu.op_class::FloatDiv 0 0.00% 65.05% +system.cpu.op_class::FloatMisc 0 0.00% 65.05% +system.cpu.op_class::FloatSqrt 0 0.00% 65.05% +system.cpu.op_class::SimdAdd 0 0.00% 65.05% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% +system.cpu.op_class::SimdAlu 0 0.00% 65.05% +system.cpu.op_class::SimdCmp 0 0.00% 65.05% +system.cpu.op_class::SimdCvt 0 0.00% 65.05% +system.cpu.op_class::SimdMisc 0 0.00% 65.05% +system.cpu.op_class::SimdMult 0 0.00% 65.05% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% +system.cpu.op_class::SimdShift 0 0.00% 65.05% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% +system.cpu.op_class::SimdSqrt 0 0.00% 65.05% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% +system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% +system.cpu.op_class::MemRead 1085 18.61% 83.71% +system.cpu.op_class::MemWrite 934 16.02% 99.73% +system.cpu.op_class::FloatMemRead 0 0.00% 99.73% +system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5831 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 +system.membus.trans_dist::ReadReq 6078 +system.membus.trans_dist::ReadResp 6088 +system.membus.trans_dist::WriteReq 925 +system.membus.trans_dist::WriteResp 925 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994 +system.membus.pkt_count::total 14049 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368 +system.membus.pkt_size::total 28476 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 7025 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 7025 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 7025 +system.membus.reqLayer0.occupancy 7961000 +system.membus.reqLayer0.utilization 2.1 +system.membus.respLayer0.occupancy 11413250 +system.membus.respLayer0.utilization 3.1 +system.membus.respLayer1.occupancy 3327250 +system.membus.respLayer1.utilization 0.9 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini index 733323a88..df4988eaf 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini @@ -93,6 +93,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -106,10 +107,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -123,6 +124,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -135,15 +137,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -202,10 +205,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -219,6 +222,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -231,15 +235,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -258,8 +263,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -270,8 +273,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -331,7 +332,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/arm/linux/hello cwd= drivers= @@ -344,10 +345,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -397,10 +399,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -414,6 +416,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -426,15 +429,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout index 7a7d67b77..00615c5ed 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:05:17 -gem5 executing on e108600-lin, pid 17589 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55755 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 52453000 because target called exit() +Exiting @ tick 52453000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 0bf6798da..67ec14819 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -1,846 +1,846 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000052 # Number of seconds simulated -sim_ticks 52453000 # Number of ticks simulated -final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 494492 # Simulator instruction rate (inst/s) -host_op_rate 571324 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5188174566 # Simulator tick rate (ticks/s) -host_mem_usage 654324 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4988 # Number of instructions simulated -sim_ops 5770 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 351 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 52348000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation -system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 149139.60 # Average gap between requests -system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states -system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 52453000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 52453 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4988 # Number of instructions committed -system.cpu.committedOps 5770 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 215 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls -system.cpu.num_int_insts 4977 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 8049 # number of times the integer registers were read -system.cpu.num_int_register_writes 2992 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written -system.cpu.num_mem_refs 2035 # number of memory refs -system.cpu.num_load_insts 1085 # Number of load instructions -system.cpu.num_store_insts 950 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 52452.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1107 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction -system.cpu.op_class::MemWrite 934 16.02% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5831 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.380856 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082403 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082403 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1833 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1833 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1833 # number of overall hits -system.cpu.dcache.overall_hits::total 1833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9073000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4652000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13725000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13725000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13725000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13725000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1975 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1975 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1975 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1975 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 96654.929577 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 96654.929577 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13441000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.586088 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10305 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits -system.cpu.icache.overall_hits::total 4779 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses -system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25472000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25472000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25472000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25472000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25472000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 102297.188755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 102297.188755 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24974000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24974000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 348 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 391 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram -system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 391 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 184.362995 # Cycle average of tags in use -system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.367017 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 76.995978 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026213 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.018798 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045010 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 3959 # Number of tag accesses -system.l2cache.tags.data_accesses 3959 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits -system.l2cache.demand_hits::total 40 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.l2cache.overall_hits::cpu.data 16 # number of overall hits -system.l2cache.overall_hits::total 40 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 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ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 249 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 391 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.903614 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 103515.669516 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 103515.669516 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 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-system.l2cache.demand_mshr_miss_latency::cpu.inst 19183000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10131000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 29314000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19183000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10131000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 29314000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. 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+system.membus.reqLayer0.utilization 0.7 +system.membus.respLayer0.occupancy 1866250 +system.membus.respLayer0.utilization 3.6 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini index d1ab85628..22ac65ead 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini @@ -91,6 +91,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -120,7 +121,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/sparc/linux/hello cwd= drivers= @@ -133,10 +134,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout index 4568a6760..4f2bfd587 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:47:16 -gem5 executing on e108600-lin, pid 17418 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:38 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64860 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 380341000 because target called exit() +Hello World!Exiting @ tick 380341000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index 25ad41fa6..c3baff489 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -1,386 +1,386 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000380 # Number of seconds simulated -sim_ticks 380341000 # Number of ticks simulated -final_tick 380341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290732 # Simulator instruction rate (inst/s) -host_op_rate 290372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19883940078 # Simulator tick rate (ticks/s) -host_mem_usage 632768 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5548 # Number of instructions simulated -sim_ops 5548 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 22364 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 22364 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 5065 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 5065 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 5591 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 718 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 6309 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 673 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 673 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 58799866 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 12199579 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 70999445 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 58799866 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 58799866 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 13316997 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 13316997 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 58799866 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 25516576 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 84316442 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 6310 # Number of read requests accepted -system.mem_ctrl.writeReqs 673 # Number of write requests accepted -system.mem_ctrl.readBursts 6310 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 673 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 397760 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6080 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 27008 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 5065 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 548 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 220 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 84 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 2 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 199 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 1004 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 1555 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 875 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 710 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 348 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 99 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 623 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 56 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 162 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 200 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 78 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 16 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 42 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 19 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 5 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 4 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 10 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 380264000 # Total gap between requests -system.mem_ctrl.readPktSize::0 88 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 2 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 5711 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 509 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 13 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 2 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 54 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 604 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6215 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 575 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 700.438261 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 528.229400 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 375.888489 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 575 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 772.166667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 643.154197 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 524.176084 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::896-959 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1664-1727 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 59680000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 176211250 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 31075000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9602.57 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28352.57 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1045.80 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 16.15 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 71.01 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 13.32 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.30 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.17 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.12 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5650 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 83 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 90.91 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 66.40 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 54455.68 # Average gap between requests -system.mem_ctrl.pageHitRate 90.43 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2598960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1377585 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 28124460 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 401940 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 55884510 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 903360 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 108619200 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 6618240 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 234030975 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 615.318415 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 255286000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 462000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 111848750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750 # Time in different power states -system.mem_ctrl_1.actEnergy 1527960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 804540 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 16243500 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 99180 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 28273440.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 35538930 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1997760 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 96272430 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 16892160 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 11758020 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 209407920 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 550.579039 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 297220000 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 3473000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 11978000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 42087750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 67670000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 380341000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 380341 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5548 # Number of instructions committed -system.cpu.committedOps 5548 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls -system.cpu.num_int_insts 4660 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10977 # number of times the integer registers were read -system.cpu.num_int_register_writes 5062 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1404 # number of memory refs -system.cpu.num_load_insts 726 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 380340.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1187 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction -system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5591 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6310 # Transaction distribution -system.membus.trans_dist::ReadResp 6309 # Transaction distribution -system.membus.trans_dist::WriteReq 673 # Transaction distribution -system.membus.trans_dist::WriteResp 673 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11183 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 2782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13965 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 9705 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32069 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6983 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6983 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6983 # Request fanout histogram -system.membus.reqLayer0.occupancy 7656000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 12691750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2300750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +sim_seconds 0.000380 +sim_ticks 380341000 +final_tick 380341000 +sim_freq 1000000000000 +host_inst_rate 164409 +host_op_rate 164322 +host_tick_rate 11259796640 +host_mem_usage 644796 +host_seconds 0.03 +sim_insts 5548 +sim_ops 5548 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000 +system.mem_ctrl.bytes_read::cpu.inst 22364 +system.mem_ctrl.bytes_read::cpu.data 4640 +system.mem_ctrl.bytes_read::total 27004 +system.mem_ctrl.bytes_inst_read::cpu.inst 22364 +system.mem_ctrl.bytes_inst_read::total 22364 +system.mem_ctrl.bytes_written::cpu.data 5065 +system.mem_ctrl.bytes_written::total 5065 +system.mem_ctrl.num_reads::cpu.inst 5591 +system.mem_ctrl.num_reads::cpu.data 718 +system.mem_ctrl.num_reads::total 6309 +system.mem_ctrl.num_writes::cpu.data 673 +system.mem_ctrl.num_writes::total 673 +system.mem_ctrl.bw_read::cpu.inst 58799866 +system.mem_ctrl.bw_read::cpu.data 12199579 +system.mem_ctrl.bw_read::total 70999445 +system.mem_ctrl.bw_inst_read::cpu.inst 58799866 +system.mem_ctrl.bw_inst_read::total 58799866 +system.mem_ctrl.bw_write::cpu.data 13316997 +system.mem_ctrl.bw_write::total 13316997 +system.mem_ctrl.bw_total::cpu.inst 58799866 +system.mem_ctrl.bw_total::cpu.data 25516576 +system.mem_ctrl.bw_total::total 84316442 +system.mem_ctrl.readReqs 6310 +system.mem_ctrl.writeReqs 673 +system.mem_ctrl.readBursts 6310 +system.mem_ctrl.writeBursts 673 +system.mem_ctrl.bytesReadDRAM 397760 +system.mem_ctrl.bytesReadWrQ 6080 +system.mem_ctrl.bytesWritten 6144 +system.mem_ctrl.bytesReadSys 27008 +system.mem_ctrl.bytesWrittenSys 5065 +system.mem_ctrl.servicedByWrQ 95 +system.mem_ctrl.mergedWrBursts 548 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 220 +system.mem_ctrl.perBankRdBursts::1 84 +system.mem_ctrl.perBankRdBursts::2 2 +system.mem_ctrl.perBankRdBursts::3 199 +system.mem_ctrl.perBankRdBursts::4 0 +system.mem_ctrl.perBankRdBursts::5 1004 +system.mem_ctrl.perBankRdBursts::6 1555 +system.mem_ctrl.perBankRdBursts::7 875 +system.mem_ctrl.perBankRdBursts::8 710 +system.mem_ctrl.perBankRdBursts::9 348 +system.mem_ctrl.perBankRdBursts::10 99 +system.mem_ctrl.perBankRdBursts::11 623 +system.mem_ctrl.perBankRdBursts::12 56 +system.mem_ctrl.perBankRdBursts::13 162 +system.mem_ctrl.perBankRdBursts::14 200 +system.mem_ctrl.perBankRdBursts::15 78 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 16 +system.mem_ctrl.perBankWrBursts::6 42 +system.mem_ctrl.perBankWrBursts::7 19 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 5 +system.mem_ctrl.perBankWrBursts::10 0 +system.mem_ctrl.perBankWrBursts::11 0 +system.mem_ctrl.perBankWrBursts::12 4 +system.mem_ctrl.perBankWrBursts::13 10 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 0 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 380264000 +system.mem_ctrl.readPktSize::0 88 +system.mem_ctrl.readPktSize::1 2 +system.mem_ctrl.readPktSize::2 5711 +system.mem_ctrl.readPktSize::3 509 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 0 +system.mem_ctrl.writePktSize::0 13 +system.mem_ctrl.writePktSize::1 2 +system.mem_ctrl.writePktSize::2 54 +system.mem_ctrl.writePktSize::3 604 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 6215 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 1 +system.mem_ctrl.wrQLenPdf::1 1 +system.mem_ctrl.wrQLenPdf::2 1 +system.mem_ctrl.wrQLenPdf::3 1 +system.mem_ctrl.wrQLenPdf::4 1 +system.mem_ctrl.wrQLenPdf::5 1 +system.mem_ctrl.wrQLenPdf::6 1 +system.mem_ctrl.wrQLenPdf::7 1 +system.mem_ctrl.wrQLenPdf::8 1 +system.mem_ctrl.wrQLenPdf::9 1 +system.mem_ctrl.wrQLenPdf::10 1 +system.mem_ctrl.wrQLenPdf::11 1 +system.mem_ctrl.wrQLenPdf::12 1 +system.mem_ctrl.wrQLenPdf::13 1 +system.mem_ctrl.wrQLenPdf::14 1 +system.mem_ctrl.wrQLenPdf::15 1 +system.mem_ctrl.wrQLenPdf::16 1 +system.mem_ctrl.wrQLenPdf::17 7 +system.mem_ctrl.wrQLenPdf::18 7 +system.mem_ctrl.wrQLenPdf::19 7 +system.mem_ctrl.wrQLenPdf::20 7 +system.mem_ctrl.wrQLenPdf::21 7 +system.mem_ctrl.wrQLenPdf::22 7 +system.mem_ctrl.wrQLenPdf::23 7 +system.mem_ctrl.wrQLenPdf::24 7 +system.mem_ctrl.wrQLenPdf::25 7 +system.mem_ctrl.wrQLenPdf::26 7 +system.mem_ctrl.wrQLenPdf::27 7 +system.mem_ctrl.wrQLenPdf::28 7 +system.mem_ctrl.wrQLenPdf::29 6 +system.mem_ctrl.wrQLenPdf::30 6 +system.mem_ctrl.wrQLenPdf::31 6 +system.mem_ctrl.wrQLenPdf::32 6 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 575 +system.mem_ctrl.bytesPerActivate::mean 700.438261 +system.mem_ctrl.bytesPerActivate::gmean 528.229400 +system.mem_ctrl.bytesPerActivate::stdev 375.888489 +system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83% +system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52% +system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96% +system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04% +system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57% +system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26% +system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78% +system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48% +system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00% +system.mem_ctrl.bytesPerActivate::total 575 +system.mem_ctrl.rdPerTurnAround::samples 6 +system.mem_ctrl.rdPerTurnAround::mean 772.166667 +system.mem_ctrl.rdPerTurnAround::gmean 643.154197 +system.mem_ctrl.rdPerTurnAround::stdev 524.176084 +system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% +system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% +system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% +system.mem_ctrl.rdPerTurnAround::896-959 1 16.67% 83.33% +system.mem_ctrl.rdPerTurnAround::1664-1727 1 16.67% 100.00% +system.mem_ctrl.rdPerTurnAround::total 6 +system.mem_ctrl.wrPerTurnAround::samples 6 +system.mem_ctrl.wrPerTurnAround::mean 16 +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 +system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% +system.mem_ctrl.wrPerTurnAround::total 6 +system.mem_ctrl.totQLat 59680000 +system.mem_ctrl.totMemAccLat 176211250 +system.mem_ctrl.totBusLat 31075000 +system.mem_ctrl.avgQLat 9602.57 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 28352.57 +system.mem_ctrl.avgRdBW 1045.80 +system.mem_ctrl.avgWrBW 16.15 +system.mem_ctrl.avgRdBWSys 71.01 +system.mem_ctrl.avgWrBWSys 13.32 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 8.30 +system.mem_ctrl.busUtilRead 8.17 +system.mem_ctrl.busUtilWrite 0.13 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 23.12 +system.mem_ctrl.readRowHits 5650 +system.mem_ctrl.writeRowHits 83 +system.mem_ctrl.readRowHitRate 90.91 +system.mem_ctrl.writeRowHitRate 66.40 +system.mem_ctrl.avgGap 54455.68 +system.mem_ctrl.pageHitRate 90.43 +system.mem_ctrl_0.actEnergy 2598960 +system.mem_ctrl_0.preEnergy 1377585 +system.mem_ctrl_0.readEnergy 28124460 +system.mem_ctrl_0.writeEnergy 401940 +system.mem_ctrl_0.refreshEnergy 29502720.000000 +system.mem_ctrl_0.actBackEnergy 55884510 +system.mem_ctrl_0.preBackEnergy 903360 +system.mem_ctrl_0.actPowerDownEnergy 108619200 +system.mem_ctrl_0.prePowerDownEnergy 6618240 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 234030975 +system.mem_ctrl_0.averagePower 615.318415 +system.mem_ctrl_0.totalIdleTime 255286000 +system.mem_ctrl_0.memoryStateTime::IDLE 462000 +system.mem_ctrl_0.memoryStateTime::REF 12480000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500 +system.mem_ctrl_0.memoryStateTime::ACT 111848750 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750 +system.mem_ctrl_1.actEnergy 1527960 +system.mem_ctrl_1.preEnergy 804540 +system.mem_ctrl_1.readEnergy 16243500 +system.mem_ctrl_1.writeEnergy 99180 +system.mem_ctrl_1.refreshEnergy 28273440.000000 +system.mem_ctrl_1.actBackEnergy 35538930 +system.mem_ctrl_1.preBackEnergy 1997760 +system.mem_ctrl_1.actPowerDownEnergy 96272430 +system.mem_ctrl_1.prePowerDownEnergy 16892160 +system.mem_ctrl_1.selfRefreshEnergy 11758020 +system.mem_ctrl_1.totalEnergy 209407920 +system.mem_ctrl_1.averagePower 550.579039 +system.mem_ctrl_1.totalIdleTime 297220000 +system.mem_ctrl_1.memoryStateTime::IDLE 3473000 +system.mem_ctrl_1.memoryStateTime::REF 11978000 +system.mem_ctrl_1.memoryStateTime::SREF 42087750 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250 +system.mem_ctrl_1.memoryStateTime::ACT 67670000 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000 +system.pwrStateResidencyTicks::UNDEFINED 380341000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 380341000 +system.cpu.numCycles 380341 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5548 +system.cpu.committedOps 5548 +system.cpu.num_int_alu_accesses 4660 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 835 +system.cpu.num_int_insts 4660 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10977 +system.cpu.num_int_register_writes 5062 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1404 +system.cpu.num_load_insts 726 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 380341 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1187 +system.cpu.op_class::No_OpClass 173 3.09% 3.09% +system.cpu.op_class::IntAlu 4014 71.79% 74.89% +system.cpu.op_class::IntMult 0 0.00% 74.89% +system.cpu.op_class::IntDiv 0 0.00% 74.89% +system.cpu.op_class::FloatAdd 0 0.00% 74.89% +system.cpu.op_class::FloatCmp 0 0.00% 74.89% +system.cpu.op_class::FloatCvt 0 0.00% 74.89% +system.cpu.op_class::FloatMult 0 0.00% 74.89% +system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% +system.cpu.op_class::FloatDiv 0 0.00% 74.89% +system.cpu.op_class::FloatMisc 0 0.00% 74.89% +system.cpu.op_class::FloatSqrt 0 0.00% 74.89% +system.cpu.op_class::SimdAdd 0 0.00% 74.89% +system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% +system.cpu.op_class::SimdAlu 0 0.00% 74.89% +system.cpu.op_class::SimdCmp 0 0.00% 74.89% +system.cpu.op_class::SimdCvt 0 0.00% 74.89% +system.cpu.op_class::SimdMisc 0 0.00% 74.89% +system.cpu.op_class::SimdMult 0 0.00% 74.89% +system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% +system.cpu.op_class::SimdShift 0 0.00% 74.89% +system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% +system.cpu.op_class::SimdSqrt 0 0.00% 74.89% +system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% +system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% +system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% +system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% +system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% +system.cpu.op_class::MemRead 726 12.99% 87.87% +system.cpu.op_class::MemWrite 678 12.13% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5591 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 380341000 +system.membus.trans_dist::ReadReq 6310 +system.membus.trans_dist::ReadResp 6309 +system.membus.trans_dist::WriteReq 673 +system.membus.trans_dist::WriteResp 673 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11183 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 2782 +system.membus.pkt_count::total 13965 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22364 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 9705 +system.membus.pkt_size::total 32069 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6983 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6983 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6983 +system.membus.reqLayer0.occupancy 7656000 +system.membus.reqLayer0.utilization 2.0 +system.membus.respLayer0.occupancy 12691750 +system.membus.respLayer0.utilization 3.3 +system.membus.respLayer1.occupancy 2300750 +system.membus.respLayer1.utilization 0.6 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini index d90641228..ec35c6b67 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini @@ -91,6 +91,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -104,10 +105,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +122,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +135,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -155,10 +158,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -172,6 +175,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -184,15 +188,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -212,7 +217,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/sparc/linux/hello cwd= drivers= @@ -225,10 +230,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -278,10 +284,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -295,6 +301,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -307,15 +314,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout index 95530f5be..ca7e9e456 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:45:43 -gem5 executing on e108600-lin, pid 17392 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:43:32 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66465 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 56511000 because target called exit() +Hello World!Exiting @ tick 56511000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 86dd54128..c0123cf6a 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,716 +1,716 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000057 # Number of seconds simulated -sim_ticks 56511000 # Number of ticks simulated -final_tick 56511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 572788 # Simulator instruction rate (inst/s) -host_op_rate 572177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5822018151 # Simulator tick rate (ticks/s) -host_mem_usage 636864 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5548 # Number of instructions simulated -sim_ops 5548 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 291058378 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 155155633 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 446214011 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 291058378 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 291058378 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 291058378 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 155155633 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 446214011 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 394 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 21 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 7 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 7 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 69 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 79 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 62 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 32 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 17 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 9 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 47 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 10 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 21 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 7 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 56394000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 394 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 248.816327 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 183.748429 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 196.431638 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 98 # Bytes accessed per row activation -system.mem_ctrl.totQLat 5793000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 13180500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 14703.05 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 33453.05 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 446.21 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 446.21 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.49 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.49 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 292 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 74.11 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 143131.98 # Average gap between requests -system.mem_ctrl.pageHitRate 74.11 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 421260 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 216315 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1756440 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 4075500 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 122880 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 21123630 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 357120 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 32375625 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 572.905837 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 47002000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 71000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 7357750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000 # Time in different power states -system.mem_ctrl_1.actEnergy 307020 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 155595 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1056720 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 2785590 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 293760 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 20523420 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 1777920 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 31202505 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 552.146785 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 49582750 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 557000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 4495750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 56511000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 56511 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5548 # Number of instructions committed -system.cpu.committedOps 5548 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls -system.cpu.num_int_insts 4660 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10977 # number of times the integer registers were read -system.cpu.num_int_register_writes 5062 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1404 # number of memory refs -system.cpu.num_load_insts 726 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 56510.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1187 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction -system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5591 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.847801 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.847801 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.081883 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.081883 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6576000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6576000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8937000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8937000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15513000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15513000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15513000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15513000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1391 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1391 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1391 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1391 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 117428.571429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 117428.571429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108987.804878 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108987.804878 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 112413.043478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 112413.043478 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15237000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15237000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115428.571429 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115428.571429 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106987.804878 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106987.804878 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.324434 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.324434 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.384080 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.384080 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11443 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits -system.cpu.icache.overall_hits::total 5333 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses -system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27828000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27828000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27828000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27828000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27828000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27828000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 107444.015444 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 107444.015444 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 107444.015444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 107444.015444 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27310000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27310000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27310000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27310000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27310000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27310000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 105444.015444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 105444.015444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 315 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 397 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.007557 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.086709 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 394 99.24% 99.24% # Request fanout histogram -system.l2bus.snoop_fanout::1 3 0.76% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 397 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 201.052259 # Cycle average of tags in use -system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 118.133782 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 82.918477 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.028841 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.020244 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.049085 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 4130 # Number of tag accesses -system.l2cache.tags.data_accesses 4130 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.l2cache.overall_hits::total 3 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 82 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 82 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 257 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses -system.l2cache.demand_misses::total 394 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 257 # number of overall misses -system.l2cache.overall_misses::cpu.data 137 # number of overall misses -system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8527000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8527000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26487000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 6273000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 32760000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 26487000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 14800000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 41287000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 26487000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 14800000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 41287000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 259 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 397 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.992278 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103987.804878 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 103987.804878 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 103062.256809 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 114054.545455 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 105000 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 104789.340102 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 104789.340102 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6887000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6887000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21347000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5173000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 26520000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 21347000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 12060000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 33407000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 21347000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 12060000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 33407000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83987.804878 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83987.804878 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 83062.256809 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 94054.545455 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85000 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 312 # Transaction distribution -system.membus.trans_dist::ReadExReq 82 # Transaction distribution -system.membus.trans_dist::ReadExResp 82 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 394 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 394 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 394 # Request fanout histogram -system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2102500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) +sim_seconds 0.000057 +sim_ticks 56511000 +final_tick 56511000 +sim_freq 1000000000000 +host_inst_rate 336003 +host_op_rate 335612 +host_tick_rate 3415114336 +host_mem_usage 648892 +host_seconds 0.02 +sim_insts 5548 +sim_ops 5548 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000 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+system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 +system.membus.pkt_size::total 25216 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 394 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 394 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 394 +system.membus.reqLayer0.occupancy 394000 +system.membus.reqLayer0.utilization 0.7 +system.membus.respLayer0.occupancy 2102500 +system.membus.respLayer0.utilization 3.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini index 612b72e20..55e4fb657 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -91,6 +92,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/x86/linux/hello cwd= drivers= @@ -180,10 +182,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout index 3227a9df4..7864b0cf9 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:11:23 -gem5 executing on e108600-lin, pid 17668 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:23 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87205 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 507841000 because target called exit() +Exiting @ tick 507841000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index 7797c05db..b34dd3952 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -1,398 +1,398 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000508 # Number of seconds simulated -sim_ticks 507841000 # Number of ticks simulated -final_tick 507841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118772 # Simulator instruction rate (inst/s) -host_op_rate 214398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10553661963 # Simulator tick rate (ticks/s) -host_mem_usage 651408 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 5712 # Number of instructions simulated -sim_ops 10314 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 58264 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 58264 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 7160 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 7160 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 7283 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1084 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 114728823 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14112685 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 128841507 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 114728823 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 114728823 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 14098901 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 14098901 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 114728823 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 28211586 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 142940409 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 8367 # Number of read requests accepted -system.mem_ctrl.writeReqs 941 # Number of write requests accepted -system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 1619 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 965 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 1103 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 10 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 54 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 34 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 4 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 507709000 # Total gap between requests -system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 8099 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 14 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 3 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 63 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 861 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 856 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 618.018692 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 421.107711 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 393.969749 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 856 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 82515500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 236378000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 10055.51 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28805.51 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1034.15 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 14.11 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 128.84 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 14.10 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.08 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.11 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.79 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 7357 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.65 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 54545.44 # Average gap between requests -system.mem_ctrl.pageHitRate 89.42 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3127320 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1647030 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37149420 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 52200 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 70559160 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1716480 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 113314290 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 13222080 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 17426520 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 294478260 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 579.862821 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 347720500 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 1584000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 15358000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 65707000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 142245250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 # Time in different power states -system.mem_ctrl_1.actEnergy 3034500 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1601490 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 21441420 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 532440 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 51598110 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1155360 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 151289970 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 18740160 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 3216240 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 291946650 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 574.877779 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 391695500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 757000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 16646000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 11100000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 98712250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 507841000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 507841 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5712 # Number of instructions committed -system.cpu.committedOps 10314 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 221 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls -system.cpu.num_int_insts 10205 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 19296 # number of times the integer registers were read -system.cpu.num_int_register_writes 7977 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written -system.cpu.num_mem_refs 2025 # number of memory refs -system.cpu.num_load_insts 1084 # Number of load instructions -system.cpu.num_store_insts 941 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 507840.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1306 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction -system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction -system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 10314 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 8367 # Transaction distribution -system.membus.trans_dist::ReadResp 8367 # Transaction distribution -system.membus.trans_dist::WriteReq 941 # Transaction distribution -system.membus.trans_dist::WriteResp 941 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 14566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 4050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 18616 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 58264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14327 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 72591 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 9308 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9308 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9308 # Request fanout histogram -system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 2.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 16544750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 3432250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +sim_seconds 0.000508 +sim_ticks 507841000 +final_tick 507841000 +sim_freq 1000000000000 +host_inst_rate 110016 +host_op_rate 198569 +host_tick_rate 9773316243 +host_mem_usage 663056 +host_seconds 0.05 +sim_insts 5712 +sim_ops 10314 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 +system.mem_ctrl.bytes_read::cpu.inst 58264 +system.mem_ctrl.bytes_read::cpu.data 7167 +system.mem_ctrl.bytes_read::total 65431 +system.mem_ctrl.bytes_inst_read::cpu.inst 58264 +system.mem_ctrl.bytes_inst_read::total 58264 +system.mem_ctrl.bytes_written::cpu.data 7160 +system.mem_ctrl.bytes_written::total 7160 +system.mem_ctrl.num_reads::cpu.inst 7283 +system.mem_ctrl.num_reads::cpu.data 1084 +system.mem_ctrl.num_reads::total 8367 +system.mem_ctrl.num_writes::cpu.data 941 +system.mem_ctrl.num_writes::total 941 +system.mem_ctrl.bw_read::cpu.inst 114728823 +system.mem_ctrl.bw_read::cpu.data 14112685 +system.mem_ctrl.bw_read::total 128841507 +system.mem_ctrl.bw_inst_read::cpu.inst 114728823 +system.mem_ctrl.bw_inst_read::total 114728823 +system.mem_ctrl.bw_write::cpu.data 14098901 +system.mem_ctrl.bw_write::total 14098901 +system.mem_ctrl.bw_total::cpu.inst 114728823 +system.mem_ctrl.bw_total::cpu.data 28211586 +system.mem_ctrl.bw_total::total 142940409 +system.mem_ctrl.readReqs 8368 +system.mem_ctrl.writeReqs 941 +system.mem_ctrl.readBursts 8368 +system.mem_ctrl.writeBursts 941 +system.mem_ctrl.bytesReadDRAM 525248 +system.mem_ctrl.bytesReadWrQ 10304 +system.mem_ctrl.bytesWritten 7168 +system.mem_ctrl.bytesReadSys 65439 +system.mem_ctrl.bytesWrittenSys 7160 +system.mem_ctrl.servicedByWrQ 161 +system.mem_ctrl.mergedWrBursts 810 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 277 +system.mem_ctrl.perBankRdBursts::1 4 +system.mem_ctrl.perBankRdBursts::2 227 +system.mem_ctrl.perBankRdBursts::3 102 +system.mem_ctrl.perBankRdBursts::4 1619 +system.mem_ctrl.perBankRdBursts::5 965 +system.mem_ctrl.perBankRdBursts::6 1103 +system.mem_ctrl.perBankRdBursts::7 906 +system.mem_ctrl.perBankRdBursts::8 703 +system.mem_ctrl.perBankRdBursts::9 491 +system.mem_ctrl.perBankRdBursts::10 1059 +system.mem_ctrl.perBankRdBursts::11 59 +system.mem_ctrl.perBankRdBursts::12 11 +system.mem_ctrl.perBankRdBursts::13 489 +system.mem_ctrl.perBankRdBursts::14 78 +system.mem_ctrl.perBankRdBursts::15 114 +system.mem_ctrl.perBankWrBursts::0 10 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 3 +system.mem_ctrl.perBankWrBursts::9 54 +system.mem_ctrl.perBankWrBursts::10 34 +system.mem_ctrl.perBankWrBursts::11 7 +system.mem_ctrl.perBankWrBursts::12 0 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 4 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 507764000 +system.mem_ctrl.readPktSize::0 135 +system.mem_ctrl.readPktSize::1 14 +system.mem_ctrl.readPktSize::2 119 +system.mem_ctrl.readPktSize::3 8100 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 0 +system.mem_ctrl.writePktSize::0 14 +system.mem_ctrl.writePktSize::1 3 +system.mem_ctrl.writePktSize::2 63 +system.mem_ctrl.writePktSize::3 861 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 8207 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 1 +system.mem_ctrl.wrQLenPdf::1 1 +system.mem_ctrl.wrQLenPdf::2 1 +system.mem_ctrl.wrQLenPdf::3 1 +system.mem_ctrl.wrQLenPdf::4 1 +system.mem_ctrl.wrQLenPdf::5 1 +system.mem_ctrl.wrQLenPdf::6 1 +system.mem_ctrl.wrQLenPdf::7 1 +system.mem_ctrl.wrQLenPdf::8 1 +system.mem_ctrl.wrQLenPdf::9 1 +system.mem_ctrl.wrQLenPdf::10 1 +system.mem_ctrl.wrQLenPdf::11 1 +system.mem_ctrl.wrQLenPdf::12 1 +system.mem_ctrl.wrQLenPdf::13 1 +system.mem_ctrl.wrQLenPdf::14 1 +system.mem_ctrl.wrQLenPdf::15 1 +system.mem_ctrl.wrQLenPdf::16 1 +system.mem_ctrl.wrQLenPdf::17 8 +system.mem_ctrl.wrQLenPdf::18 8 +system.mem_ctrl.wrQLenPdf::19 7 +system.mem_ctrl.wrQLenPdf::20 7 +system.mem_ctrl.wrQLenPdf::21 7 +system.mem_ctrl.wrQLenPdf::22 7 +system.mem_ctrl.wrQLenPdf::23 7 +system.mem_ctrl.wrQLenPdf::24 7 +system.mem_ctrl.wrQLenPdf::25 7 +system.mem_ctrl.wrQLenPdf::26 7 +system.mem_ctrl.wrQLenPdf::27 7 +system.mem_ctrl.wrQLenPdf::28 7 +system.mem_ctrl.wrQLenPdf::29 7 +system.mem_ctrl.wrQLenPdf::30 7 +system.mem_ctrl.wrQLenPdf::31 7 +system.mem_ctrl.wrQLenPdf::32 7 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 856 +system.mem_ctrl.bytesPerActivate::mean 618.018692 +system.mem_ctrl.bytesPerActivate::gmean 421.107711 +system.mem_ctrl.bytesPerActivate::stdev 393.969749 +system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% +system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% +system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% +system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% +system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% +system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% +system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% +system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% +system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% +system.mem_ctrl.bytesPerActivate::total 856 +system.mem_ctrl.rdPerTurnAround::samples 7 +system.mem_ctrl.rdPerTurnAround::mean 1165.285714 +system.mem_ctrl.rdPerTurnAround::gmean 941.793638 +system.mem_ctrl.rdPerTurnAround::stdev 714.559471 +system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% +system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% +system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% +system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% +system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% +system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% +system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% +system.mem_ctrl.rdPerTurnAround::total 7 +system.mem_ctrl.wrPerTurnAround::samples 7 +system.mem_ctrl.wrPerTurnAround::mean 16 +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 +system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% +system.mem_ctrl.wrPerTurnAround::total 7 +system.mem_ctrl.totQLat 82521500 +system.mem_ctrl.totMemAccLat 236402750 +system.mem_ctrl.totBusLat 41035000 +system.mem_ctrl.avgQLat 10055.01 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 28805.01 +system.mem_ctrl.avgRdBW 1034.28 +system.mem_ctrl.avgWrBW 14.11 +system.mem_ctrl.avgRdBWSys 128.86 +system.mem_ctrl.avgWrBWSys 14.10 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 8.19 +system.mem_ctrl.busUtilRead 8.08 +system.mem_ctrl.busUtilWrite 0.11 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 23.79 +system.mem_ctrl.readRowHits 7358 +system.mem_ctrl.writeRowHits 98 +system.mem_ctrl.readRowHitRate 89.66 +system.mem_ctrl.writeRowHitRate 74.81 +system.mem_ctrl.avgGap 54545.49 +system.mem_ctrl.pageHitRate 89.42 +system.mem_ctrl_0.actEnergy 3127320 +system.mem_ctrl_0.preEnergy 1647030 +system.mem_ctrl_0.readEnergy 37149420 +system.mem_ctrl_0.writeEnergy 52200 +system.mem_ctrl_0.refreshEnergy 36263760.000000 +system.mem_ctrl_0.actBackEnergy 70559160 +system.mem_ctrl_0.preBackEnergy 1716480 +system.mem_ctrl_0.actPowerDownEnergy 113314290 +system.mem_ctrl_0.prePowerDownEnergy 13222080 +system.mem_ctrl_0.selfRefreshEnergy 17426520 +system.mem_ctrl_0.totalEnergy 294478260 +system.mem_ctrl_0.averagePower 579.862821 +system.mem_ctrl_0.totalIdleTime 347720500 +system.mem_ctrl_0.memoryStateTime::IDLE 1584000 +system.mem_ctrl_0.memoryStateTime::REF 15358000 +system.mem_ctrl_0.memoryStateTime::SREF 65707000 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 +system.mem_ctrl_0.memoryStateTime::ACT 142245250 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 +system.mem_ctrl_1.actEnergy 3034500 +system.mem_ctrl_1.preEnergy 1601490 +system.mem_ctrl_1.readEnergy 21441420 +system.mem_ctrl_1.writeEnergy 532440 +system.mem_ctrl_1.refreshEnergy 39336960.000000 +system.mem_ctrl_1.actBackEnergy 51598110 +system.mem_ctrl_1.preBackEnergy 1155360 +system.mem_ctrl_1.actPowerDownEnergy 151289970 +system.mem_ctrl_1.prePowerDownEnergy 18740160 +system.mem_ctrl_1.selfRefreshEnergy 3216240 +system.mem_ctrl_1.totalEnergy 291946650 +system.mem_ctrl_1.averagePower 574.877779 +system.mem_ctrl_1.totalIdleTime 391725750 +system.mem_ctrl_1.memoryStateTime::IDLE 757000 +system.mem_ctrl_1.memoryStateTime::REF 16646000 +system.mem_ctrl_1.memoryStateTime::SREF 11100000 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 +system.mem_ctrl_1.memoryStateTime::ACT 98712250 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 +system.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.apic_clk_domain.clock 16000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 507841000 +system.cpu.numCycles 507841 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5712 +system.cpu.committedOps 10314 +system.cpu.num_int_alu_accesses 10205 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 221 +system.cpu.num_conditional_control_insts 986 +system.cpu.num_int_insts 10205 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 19296 +system.cpu.num_int_register_writes 7977 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 7020 +system.cpu.num_cc_register_writes 3825 +system.cpu.num_mem_refs 2025 +system.cpu.num_load_insts 1084 +system.cpu.num_store_insts 941 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 507841 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1306 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 8275 80.23% 80.24% +system.cpu.op_class::IntMult 6 0.06% 80.30% +system.cpu.op_class::IntDiv 7 0.07% 80.37% +system.cpu.op_class::FloatAdd 0 0.00% 80.37% +system.cpu.op_class::FloatCmp 0 0.00% 80.37% +system.cpu.op_class::FloatCvt 0 0.00% 80.37% +system.cpu.op_class::FloatMult 0 0.00% 80.37% +system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::FloatDiv 0 0.00% 80.37% +system.cpu.op_class::FloatMisc 0 0.00% 80.37% +system.cpu.op_class::FloatSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdAdd 0 0.00% 80.37% +system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% +system.cpu.op_class::SimdAlu 0 0.00% 80.37% +system.cpu.op_class::SimdCmp 0 0.00% 80.37% +system.cpu.op_class::SimdCvt 0 0.00% 80.37% +system.cpu.op_class::SimdMisc 0 0.00% 80.37% +system.cpu.op_class::SimdMult 0 0.00% 80.37% +system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdShift 0 0.00% 80.37% +system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% +system.cpu.op_class::SimdSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% +system.cpu.op_class::MemRead 1084 10.51% 90.88% +system.cpu.op_class::MemWrite 941 9.12% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 10314 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 +system.membus.trans_dist::ReadReq 8368 +system.membus.trans_dist::ReadResp 8367 +system.membus.trans_dist::WriteReq 941 +system.membus.trans_dist::WriteResp 941 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14567 +system.membus.pkt_count_system.cpu.icache_port::total 14567 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050 +system.membus.pkt_count_system.cpu.dcache_port::total 4050 +system.membus.pkt_count::total 18617 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264 +system.membus.pkt_size_system.cpu.icache_port::total 58264 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327 +system.membus.pkt_size_system.cpu.dcache_port::total 14327 +system.membus.pkt_size::total 72591 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 9309 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 9309 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 9309 +system.membus.reqLayer2.occupancy 10250000 +system.membus.reqLayer2.utilization 2.0 +system.membus.respLayer0.occupancy 16544750 +system.membus.respLayer0.utilization 3.3 +system.membus.respLayer1.occupancy 3432250 +system.membus.respLayer1.utilization 0.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini index c3a9301a3..be3d0013c 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -91,6 +92,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -110,10 +112,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -127,6 +129,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -139,15 +142,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -175,10 +179,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -192,6 +196,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -204,15 +209,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -259,7 +265,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/x86/linux/hello cwd= drivers= @@ -272,10 +278,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -325,10 +332,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -342,6 +349,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -354,15 +362,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout index 736ff89ea..51ea33107 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:22 -gem5 executing on e108600-lin, pid 17647 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87157 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 58513000 because target called exit() +Exiting @ tick 58513000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index c7497d010..5f55051fc 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,722 +1,722 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000059 # Number of seconds simulated -sim_ticks 58513000 # Number of ticks simulated -final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297973 # Simulator instruction rate (inst/s) -host_op_rate 537391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3045372421 # Simulator tick rate (ticks/s) -host_mem_usage 656016 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5712 # Number of instructions simulated -sim_ops 10314 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 364 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 23296 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 23296 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 30 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 8 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 40 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 13 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 24 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 17 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 71 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 62 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 16 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 58376000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 364 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 364 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an 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length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation -system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 160373.63 # Average gap between requests -system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states -system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 58513 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5712 # Number of instructions committed -system.cpu.committedOps 10314 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 221 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls -system.cpu.num_int_insts 10205 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 19296 # number of times the integer registers were read -system.cpu.num_int_register_writes 7977 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written -system.cpu.num_mem_refs 2025 # number of memory refs -system.cpu.num_load_insts 1084 # Number of load instructions -system.cpu.num_store_insts 941 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1306 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction -system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction -system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits -system.cpu.dcache.overall_hits::total 1890 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 941 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2025 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2025 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2025 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2025 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.051661 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.083953 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses -system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits -system.cpu.icache.overall_hits::total 7048 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses -system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7283 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7283 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7283 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032267 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.032267 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 291 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 370 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.002703 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.051988 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 369 99.73% 99.73% # Request fanout histogram -system.l2bus.snoop_fanout::1 1 0.27% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 370 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use -system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 3788 # Number of tag accesses -system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits -system.l2cache.demand_hits::total 6 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 6 # number of overall hits -system.l2cache.overall_hits::total 6 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 229 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 285 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.l2cache.demand_misses::total 364 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 229 # number of overall misses -system.l2cache.overall_misses::cpu.data 135 # number of overall misses -system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 235 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 370 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.974468 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.979381 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 285 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::total 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 364 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 364 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 364 # Request fanout histogram -system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) +sim_seconds 0.000059 +sim_ticks 58513000 +final_tick 58513000 +sim_freq 1000000000000 +host_inst_rate 157408 +host_op_rate 284057 +host_tick_rate 1610644917 +host_mem_usage 667152 +host_seconds 0.04 +sim_insts 5712 +sim_ops 10314 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 +system.mem_ctrl.bytes_read::cpu.inst 14656 +system.mem_ctrl.bytes_read::cpu.data 8640 +system.mem_ctrl.bytes_read::total 23296 +system.mem_ctrl.bytes_inst_read::cpu.inst 14656 +system.mem_ctrl.bytes_inst_read::total 14656 +system.mem_ctrl.num_reads::cpu.inst 229 +system.mem_ctrl.num_reads::cpu.data 135 +system.mem_ctrl.num_reads::total 364 +system.mem_ctrl.bw_read::cpu.inst 250474254 +system.mem_ctrl.bw_read::cpu.data 147659494 +system.mem_ctrl.bw_read::total 398133748 +system.mem_ctrl.bw_inst_read::cpu.inst 250474254 +system.mem_ctrl.bw_inst_read::total 250474254 +system.mem_ctrl.bw_total::cpu.inst 250474254 +system.mem_ctrl.bw_total::cpu.data 147659494 +system.mem_ctrl.bw_total::total 398133748 +system.mem_ctrl.readReqs 364 +system.mem_ctrl.writeReqs 0 +system.mem_ctrl.readBursts 364 +system.mem_ctrl.writeBursts 0 +system.mem_ctrl.bytesReadDRAM 23296 +system.mem_ctrl.bytesReadWrQ 0 +system.mem_ctrl.bytesWritten 0 +system.mem_ctrl.bytesReadSys 23296 +system.mem_ctrl.bytesWrittenSys 0 +system.mem_ctrl.servicedByWrQ 0 +system.mem_ctrl.mergedWrBursts 0 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 30 +system.mem_ctrl.perBankRdBursts::1 1 +system.mem_ctrl.perBankRdBursts::2 5 +system.mem_ctrl.perBankRdBursts::3 8 +system.mem_ctrl.perBankRdBursts::4 43 +system.mem_ctrl.perBankRdBursts::5 40 +system.mem_ctrl.perBankRdBursts::6 13 +system.mem_ctrl.perBankRdBursts::7 24 +system.mem_ctrl.perBankRdBursts::8 17 +system.mem_ctrl.perBankRdBursts::9 71 +system.mem_ctrl.perBankRdBursts::10 62 +system.mem_ctrl.perBankRdBursts::11 14 +system.mem_ctrl.perBankRdBursts::12 2 +system.mem_ctrl.perBankRdBursts::13 14 +system.mem_ctrl.perBankRdBursts::14 4 +system.mem_ctrl.perBankRdBursts::15 16 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 0 +system.mem_ctrl.perBankWrBursts::10 0 +system.mem_ctrl.perBankWrBursts::11 0 +system.mem_ctrl.perBankWrBursts::12 0 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 0 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 58376000 +system.mem_ctrl.readPktSize::0 0 +system.mem_ctrl.readPktSize::1 0 +system.mem_ctrl.readPktSize::2 0 +system.mem_ctrl.readPktSize::3 0 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 364 +system.mem_ctrl.writePktSize::0 0 +system.mem_ctrl.writePktSize::1 0 +system.mem_ctrl.writePktSize::2 0 +system.mem_ctrl.writePktSize::3 0 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 364 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 0 +system.mem_ctrl.wrQLenPdf::1 0 +system.mem_ctrl.wrQLenPdf::2 0 +system.mem_ctrl.wrQLenPdf::3 0 +system.mem_ctrl.wrQLenPdf::4 0 +system.mem_ctrl.wrQLenPdf::5 0 +system.mem_ctrl.wrQLenPdf::6 0 +system.mem_ctrl.wrQLenPdf::7 0 +system.mem_ctrl.wrQLenPdf::8 0 +system.mem_ctrl.wrQLenPdf::9 0 +system.mem_ctrl.wrQLenPdf::10 0 +system.mem_ctrl.wrQLenPdf::11 0 +system.mem_ctrl.wrQLenPdf::12 0 +system.mem_ctrl.wrQLenPdf::13 0 +system.mem_ctrl.wrQLenPdf::14 0 +system.mem_ctrl.wrQLenPdf::15 0 +system.mem_ctrl.wrQLenPdf::16 0 +system.mem_ctrl.wrQLenPdf::17 0 +system.mem_ctrl.wrQLenPdf::18 0 +system.mem_ctrl.wrQLenPdf::19 0 +system.mem_ctrl.wrQLenPdf::20 0 +system.mem_ctrl.wrQLenPdf::21 0 +system.mem_ctrl.wrQLenPdf::22 0 +system.mem_ctrl.wrQLenPdf::23 0 +system.mem_ctrl.wrQLenPdf::24 0 +system.mem_ctrl.wrQLenPdf::25 0 +system.mem_ctrl.wrQLenPdf::26 0 +system.mem_ctrl.wrQLenPdf::27 0 +system.mem_ctrl.wrQLenPdf::28 0 +system.mem_ctrl.wrQLenPdf::29 0 +system.mem_ctrl.wrQLenPdf::30 0 +system.mem_ctrl.wrQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::32 0 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 108 +system.mem_ctrl.bytesPerActivate::mean 199.703704 +system.mem_ctrl.bytesPerActivate::gmean 135.091179 +system.mem_ctrl.bytesPerActivate::stdev 199.282229 +system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% +system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% +system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% +system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% +system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% +system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% +system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% +system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% +system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% +system.mem_ctrl.bytesPerActivate::total 108 +system.mem_ctrl.totQLat 5858750 +system.mem_ctrl.totMemAccLat 12683750 +system.mem_ctrl.totBusLat 1820000 +system.mem_ctrl.avgQLat 16095.47 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 34845.47 +system.mem_ctrl.avgRdBW 398.13 +system.mem_ctrl.avgWrBW 0.00 +system.mem_ctrl.avgRdBWSys 398.13 +system.mem_ctrl.avgWrBWSys 0.00 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 3.11 +system.mem_ctrl.busUtilRead 3.11 +system.mem_ctrl.busUtilWrite 0.00 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 0.00 +system.mem_ctrl.readRowHits 248 +system.mem_ctrl.writeRowHits 0 +system.mem_ctrl.readRowHitRate 68.13 +system.mem_ctrl.writeRowHitRate nan +system.mem_ctrl.avgGap 160373.63 +system.mem_ctrl.pageHitRate 68.13 +system.mem_ctrl_0.actEnergy 292740 +system.mem_ctrl_0.preEnergy 136620 +system.mem_ctrl_0.readEnergy 1170960 +system.mem_ctrl_0.writeEnergy 0 +system.mem_ctrl_0.refreshEnergy 4302480.000000 +system.mem_ctrl_0.actBackEnergy 2975970 +system.mem_ctrl_0.preBackEnergy 96960 +system.mem_ctrl_0.actPowerDownEnergy 20164320 +system.mem_ctrl_0.prePowerDownEnergy 2885760 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 32025810 +system.mem_ctrl_0.averagePower 547.321100 +system.mem_ctrl_0.totalIdleTime 51467750 +system.mem_ctrl_0.memoryStateTime::IDLE 59000 +system.mem_ctrl_0.memoryStateTime::REF 1820000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 +system.mem_ctrl_0.memoryStateTime::ACT 4902000 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 +system.mem_ctrl_1.actEnergy 535500 +system.mem_ctrl_1.preEnergy 273240 +system.mem_ctrl_1.readEnergy 1428000 +system.mem_ctrl_1.writeEnergy 0 +system.mem_ctrl_1.refreshEnergy 4302480.000000 +system.mem_ctrl_1.actBackEnergy 3735210 +system.mem_ctrl_1.preBackEnergy 150720 +system.mem_ctrl_1.actPowerDownEnergy 22328040 +system.mem_ctrl_1.prePowerDownEnergy 370560 +system.mem_ctrl_1.selfRefreshEnergy 0 +system.mem_ctrl_1.totalEnergy 33123750 +system.mem_ctrl_1.averagePower 566.084895 +system.mem_ctrl_1.totalIdleTime 49870500 +system.mem_ctrl_1.memoryStateTime::IDLE 184000 +system.mem_ctrl_1.memoryStateTime::REF 1820000 +system.mem_ctrl_1.memoryStateTime::SREF 0 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 +system.mem_ctrl_1.memoryStateTime::ACT 6563000 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 +system.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.apic_clk_domain.clock 16000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 58513000 +system.cpu.numCycles 58513 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5712 +system.cpu.committedOps 10314 +system.cpu.num_int_alu_accesses 10205 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 221 +system.cpu.num_conditional_control_insts 986 +system.cpu.num_int_insts 10205 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 19296 +system.cpu.num_int_register_writes 7977 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 7020 +system.cpu.num_cc_register_writes 3825 +system.cpu.num_mem_refs 2025 +system.cpu.num_load_insts 1084 +system.cpu.num_store_insts 941 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 58513 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1306 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 8275 80.23% 80.24% +system.cpu.op_class::IntMult 6 0.06% 80.30% +system.cpu.op_class::IntDiv 7 0.07% 80.37% +system.cpu.op_class::FloatAdd 0 0.00% 80.37% +system.cpu.op_class::FloatCmp 0 0.00% 80.37% +system.cpu.op_class::FloatCvt 0 0.00% 80.37% +system.cpu.op_class::FloatMult 0 0.00% 80.37% +system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::FloatDiv 0 0.00% 80.37% +system.cpu.op_class::FloatMisc 0 0.00% 80.37% +system.cpu.op_class::FloatSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdAdd 0 0.00% 80.37% +system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% +system.cpu.op_class::SimdAlu 0 0.00% 80.37% +system.cpu.op_class::SimdCmp 0 0.00% 80.37% +system.cpu.op_class::SimdCvt 0 0.00% 80.37% +system.cpu.op_class::SimdMisc 0 0.00% 80.37% +system.cpu.op_class::SimdMult 0 0.00% 80.37% +system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdShift 0 0.00% 80.37% +system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% +system.cpu.op_class::SimdSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% +system.cpu.op_class::MemRead 1084 10.51% 90.88% +system.cpu.op_class::MemWrite 941 9.12% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 10314 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.dcache.tags.replacements 0 +system.cpu.dcache.tags.tagsinuse 81.299644 +system.cpu.dcache.tags.total_refs 1890 +system.cpu.dcache.tags.sampled_refs 135 +system.cpu.dcache.tags.avg_refs 14 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 +system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 +system.cpu.dcache.tags.occ_percent::total 0.079394 +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 +system.cpu.dcache.tags.tag_accesses 4185 +system.cpu.dcache.tags.data_accesses 4185 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.dcache.ReadReq_hits::cpu.data 1028 +system.cpu.dcache.ReadReq_hits::total 1028 +system.cpu.dcache.WriteReq_hits::cpu.data 862 +system.cpu.dcache.WriteReq_hits::total 862 +system.cpu.dcache.demand_hits::cpu.data 1890 +system.cpu.dcache.demand_hits::total 1890 +system.cpu.dcache.overall_hits::cpu.data 1890 +system.cpu.dcache.overall_hits::total 1890 +system.cpu.dcache.ReadReq_misses::cpu.data 56 +system.cpu.dcache.ReadReq_misses::total 56 +system.cpu.dcache.WriteReq_misses::cpu.data 79 +system.cpu.dcache.WriteReq_misses::total 79 +system.cpu.dcache.demand_misses::cpu.data 135 +system.cpu.dcache.demand_misses::total 135 +system.cpu.dcache.overall_misses::cpu.data 135 +system.cpu.dcache.overall_misses::total 135 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 +system.cpu.dcache.ReadReq_miss_latency::total 6406000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 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0.066667 +system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 +system.cpu.dcache.overall_miss_rate::total 0.066667 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 +system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 +system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 +system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 +system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 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