diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/quick/se/03.learning-gem5 | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/quick/se/03.learning-gem5')
5 files changed, 415 insertions, 385 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 849193946..5eff3b495 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000062 # Number of seconds simulated -sim_ticks 61608000 # Number of ticks simulated -final_tick 61608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 61610000 # Number of ticks simulated +final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 214452 # Simulator instruction rate (inst/s) -host_op_rate 214360 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2049936831 # Simulator tick rate (ticks/s) -host_mem_usage 674692 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 402374 # Simulator instruction rate (inst/s) +host_op_rate 402048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3843418590 # Simulator tick rate (ticks/s) +host_mem_usage 682268 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 6440 # Number of instructions simulated sim_ops 6440 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 288793663 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 174522789 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 463316452 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 288793663 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 288793663 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 288793663 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 174522789 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 463316452 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 446 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 61358000 # Total gap between requests +system.mem_ctrl.totGap 61360000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -205,9 +205,9 @@ system.mem_ctrl.totBusLat 2230000 # To system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 463.32 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 463.32 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage @@ -219,7 +219,7 @@ system.mem_ctrl.readRowHits 340 # Nu system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 137573.99 # Average gap between requests +system.mem_ctrl.avgGap 137578.48 # Average gap between requests system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) @@ -282,7 +282,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 61608 # number of cpu cycles simulated +system.cpu.numCycles 61610 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6440 # Number of instructions committed @@ -301,7 +301,7 @@ system.cpu.num_mem_refs 2063 # nu system.cpu.num_load_insts 1195 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61608 # Number of busy cycles +system.cpu.num_busy_cycles 61610 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1054 # Number of branches fetched @@ -341,14 +341,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6450 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.300595 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.300595 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.101856 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.101856 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id @@ -445,14 +445,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.923956 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.923956 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.445015 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.445015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id @@ -471,12 +471,12 @@ system.cpu.icache.demand_misses::cpu.inst 281 # n system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28179000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28179000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28179000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28179000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28179000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28179000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses @@ -489,12 +489,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043559 system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100281.138790 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100281.138790 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100281.138790 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100281.138790 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,25 +509,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281 system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27617000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27617000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27617000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27617000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27617000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27617000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98281.138790 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98281.138790 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 376 # Transaction distribution system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -541,14 +547,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 511 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.001957 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.044237 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 511 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 510 99.80% 99.80% # Request fanout histogram +system.l2bus.snoop_fanout::1 1 0.20% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 511 # Request fanout histogram system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) @@ -558,16 +564,16 @@ system.l2bus.respLayer0.utilization 1.4 # La system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 185.387550 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.677366 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 56.710184 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031415 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045261 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index dde0dd6ed..727647065 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79800 # Simulator instruction rate (inst/s) -host_op_rate 92294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 797317444 # Simulator tick rate (ticks/s) -host_mem_usage 690160 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 351391 # Simulator instruction rate (inst/s) +host_op_rate 406109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3506224066 # Simulator tick rate (ticks/s) +host_mem_usage 699088 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -199,12 +199,12 @@ system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # B system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2542000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 9123250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7242.17 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 25992.17 # Average memory access latency per DRAM burst +system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s @@ -226,28 +226,28 @@ system.mem_ctrl_0.preEnergy 189750 # En system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 31478535 # Energy for active background per rank (pJ) +system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ) system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37466355 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 797.538290 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 1053000 # Time in different power states +system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 44628000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 30270420 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1633500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 35988405 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 766.077484 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2556000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 42875250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -427,14 +427,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.307513 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.307513 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082332 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id @@ -461,14 +461,14 @@ system.cpu.dcache.demand_misses::cpu.data 142 # n system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8771000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8771000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4421000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4421000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13192000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13192000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -489,14 +489,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88595.959596 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 88595.959596 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102813.953488 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102813.953488 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92901.408451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92901.408451 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,14 +513,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4335000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4335000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12908000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12908000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses @@ -529,24 +529,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86595.959596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86595.959596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100813.953488 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100813.953488 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.491667 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.491667 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id @@ -565,12 +565,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23407000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23407000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23407000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23407000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23407000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23407000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses @@ -583,12 +583,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94004.016064 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 94004.016064 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 94004.016064 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 94004.016064 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,25 +603,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 249 system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22909000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22909000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22909000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22909000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22909000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22909000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92004.016064 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92004.016064 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -635,14 +641,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 461 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 461 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram +system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 461 # Request fanout histogram system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) @@ -652,16 +658,16 @@ system.l2bus.respLayer0.utilization 1.5 # La system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 156.235366 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.216430 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 49.018936 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026176 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.011968 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.038143 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id @@ -688,17 +694,17 @@ system.l2cache.demand_misses::total 351 # nu system.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.l2cache.overall_misses::cpu.data 126 # number of overall misses system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4206000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4206000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21658000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 7940000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 29598000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 21658000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 12146000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 33804000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 21658000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 12146000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 33804000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) @@ -721,17 +727,17 @@ system.l2cache.demand_miss_rate::total 0.897698 # mi system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97813.953488 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97813.953488 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96257.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95662.650602 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96097.402597 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96307.692308 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96307.692308 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,17 +757,17 @@ system.l2cache.demand_mshr_misses::total 351 # nu system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3346000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3346000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6280000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23438000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 9626000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 26784000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 9626000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 26784000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses @@ -773,17 +779,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.897698 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77813.953488 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77813.953488 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75662.650602 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76097.402597 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 00ce95d37..5eab4cd6f 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 807198 # Simulator instruction rate (inst/s) -host_op_rate 805914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8425106508 # Simulator tick rate (ticks/s) -host_mem_usage 672980 # Number of bytes of host memory used +host_inst_rate 489554 # Simulator instruction rate (inst/s) +host_op_rate 489001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5114816745 # Simulator tick rate (ticks/s) +host_mem_usage 679136 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated @@ -514,6 +514,12 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 99919.191919 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 384 # Transaction distribution system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -527,15 +533,15 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 528 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 528 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 528 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram system.l2bus.snoop_fanout::total 528 # Request fanout histogram system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 279d13e98..82b97827e 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000053 # Number of seconds simulated -sim_ticks 53332000 # Number of ticks simulated -final_tick 53332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 53334000 # Number of ticks simulated +final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 257745 # Simulator instruction rate (inst/s) -host_op_rate 257613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2475242240 # Simulator tick rate (ticks/s) -host_mem_usage 673312 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 497623 # Simulator instruction rate (inst/s) +host_op_rate 497044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4772617450 # Simulator tick rate (ticks/s) +host_mem_usage 679800 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 16448 # Nu system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 308407710 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 164404110 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 472811820 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 308407710 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 308407710 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 308407710 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 164404110 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 472811820 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 394 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 53236000 # Total gap between requests +system.mem_ctrl.totGap 53238000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -204,15 +204,15 @@ system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # B system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3014250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10401750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7650.38 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26400.38 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 472.81 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 472.81 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage @@ -224,21 +224,21 @@ system.mem_ctrl.readRowHits 295 # Nu system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 135116.75 # Average gap between requests +system.mem_ctrl.avgGap 135121.83 # Average gap between requests system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ) system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 30542310 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1395000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37207005 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 792.017562 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 2172750 # Time in different power states +system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 43258500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ) @@ -255,7 +255,7 @@ system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 53332 # number of cpu cycles simulated +system.cpu.numCycles 53334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -274,7 +274,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 53331.999000 # Number of busy cycles +system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -314,12 +314,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.742557 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.742557 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id @@ -344,10 +344,10 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5532000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5532000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8433000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8433000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles @@ -368,10 +368,10 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98785.714286 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 98785.714286 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102841.463415 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102841.463415 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency @@ -392,10 +392,10 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles @@ -408,24 +408,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100841.463415 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100841.463415 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.062197 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.062197 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.383055 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.383055 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id @@ -444,12 +444,12 @@ system.cpu.icache.demand_misses::cpu.inst 259 # n system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26197000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26197000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26197000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26197000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26197000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26197000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses @@ -462,12 +462,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101146.718147 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101146.718147 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101146.718147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101146.718147 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,25 +482,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 259 system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25679000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25679000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99146.718147 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99146.718147 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 315 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution @@ -514,14 +520,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 468 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.008547 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.092153 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 464 99.15% 99.15% # Request fanout histogram +system.l2bus.snoop_fanout::1 4 0.85% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 468 # Request fanout histogram system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) @@ -531,13 +537,13 @@ system.l2bus.respLayer0.utilization 1.5 # La system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 143.999291 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 117.698664 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 26.300627 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy @@ -567,17 +573,17 @@ system.l2cache.demand_misses::total 394 # nu system.l2cache.overall_misses::cpu.inst 257 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8023000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8023000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24860000 # number of ReadSharedReq miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30091000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24860000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13254000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38114000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24860000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13254000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38114000 # number of overall miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) @@ -600,17 +606,17 @@ system.l2cache.demand_miss_rate::total 0.992443 # mi system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97841.463415 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97841.463415 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96731.517510 # average ReadSharedReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96445.512821 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96736.040609 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96736.040609 # average overall miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -630,17 +636,17 @@ system.l2cache.demand_mshr_misses::total 394 # nu system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6383000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6383000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23851000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10514000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 30234000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10514000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 30234000 # number of overall MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses @@ -652,17 +658,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.992443 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77841.463415 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77841.463415 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76731.517510 # average ReadSharedReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76445.512821 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index eeac393c4..29a5c5d19 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000056 # Nu sim_ticks 55844000 # Number of ticks simulated final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212931 # Simulator instruction rate (inst/s) -host_op_rate 384017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2076955895 # Simulator tick rate (ticks/s) -host_mem_usage 693340 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 284010 # Simulator instruction rate (inst/s) +host_op_rate 512497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2773065846 # Simulator tick rate (ticks/s) +host_mem_usage 698700 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # B system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3554250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10379250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9764.42 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28514.42 # Average memory access latency per DRAM burst +system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s @@ -313,14 +313,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.671962 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.671962 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079758 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079758 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id @@ -417,14 +417,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 91.240171 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.240171 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.356407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.356407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -500,6 +500,12 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -513,14 +519,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 428 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.002336 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.048337 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 428 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 427 99.77% 99.77% # Request fanout histogram +system.l2bus.snoop_fanout::1 1 0.23% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 428 # Request fanout histogram system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) @@ -530,13 +536,13 @@ system.l2bus.respLayer0.utilization 1.3 # La system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 135.849297 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.899114 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 28.950183 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy @@ -565,15 +571,15 @@ system.l2cache.overall_misses::cpu.data 135 # nu system.l2cache.overall_misses::total 364 # number of overall misses system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22401000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 28127000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22401000 # number of demand (read+write) miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 35992000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22401000 # number of overall miss cycles +system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 35992000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) @@ -598,15 +604,15 @@ system.l2cache.overall_miss_rate::cpu.data 1 # system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97820.960699 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 98691.228070 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98879.120879 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98879.120879 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,15 +634,15 @@ system.l2cache.overall_mshr_misses::cpu.data 135 system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17821000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 22427000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17821000 # number of demand (read+write) MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 28712000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17821000 # number of overall MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 28712000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses @@ -650,15 +656,15 @@ system.l2cache.overall_mshr_miss_rate::cpu.data 1 system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77820.960699 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78691.228070 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution |