diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
| commit | 607c2772915628c2c67c1c5bfdefaa33ae66a06e (patch) | |
| tree | f8f23fd4012f9a0053d65ac91792a7dc61d6baff /tests/quick/se/10.mcf/ref/arm/linux/simple-timing | |
| parent | 71c982ff708cc3adc7c0eccf536fea34c20cc5f0 (diff) | |
| download | gem5-607c2772915628c2c67c1c5bfdefaa33ae66a06e.tar.xz | |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
Diffstat (limited to 'tests/quick/se/10.mcf/ref/arm/linux/simple-timing')
| -rw-r--r-- | tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 699231bfd..e4e6e6d7c 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147164 # Nu sim_ticks 147164058500 # Number of ticks simulated final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 748296 # Simulator instruction rate (inst/s) -host_op_rate 752015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1215788381 # Simulator tick rate (ticks/s) -host_mem_usage 404056 # Number of bytes of host memory used -host_seconds 121.04 # Real time elapsed on the host +host_inst_rate 1482184 # Simulator instruction rate (inst/s) +host_op_rate 1489549 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2408165715 # Simulator tick rate (ticks/s) +host_mem_usage 404112 # Number of bytes of host memory used +host_seconds 61.11 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -187,7 +187,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Cl system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction @@ -209,8 +211,10 @@ system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction |