diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
| commit | 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce (patch) | |
| tree | 8dc7be3b13f98b2f6d082dc7424335d9ddfe764d /tests/quick/se/10.mcf/ref/arm | |
| parent | 71a02f624e9c406ad37a1ed7030f98a36da6e59f (diff) | |
| download | gem5-62b6ff22ec1f90014b1d0fc778014bdb38cc09ce.tar.xz | |
stats: update for snoop filter tweak
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
Diffstat (limited to 'tests/quick/se/10.mcf/ref/arm')
| -rw-r--r-- | tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt | 243 | ||||
| -rw-r--r-- | tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt | 648 |
2 files changed, 0 insertions, 891 deletions
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index f57e8a542..e69de29bb 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,243 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.054141 # Number of seconds simulated -sim_ticks 54141000500 # Number of ticks simulated -final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 763855 # Simulator instruction rate (inst/s) -host_op_rate 767659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 456454296 # Simulator tick rate (ticks/s) -host_mem_usage 371948 # Number of bytes of host memory used -host_seconds 118.61 # Real time elapsed on the host -sim_insts 90602408 # Number of instructions simulated -sim_ops 91053639 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory -system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory -system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory -system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 108282002 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90602408 # Number of instructions committed -system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732305 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054081 # Class of executed instruction -system.membus.trans_dist::ReadReq 130287906 # Transaction distribution -system.membus.trans_dist::ReadResp 130291793 # Transaction distribution -system.membus.trans_dist::WriteReq 4734981 # Transaction distribution -system.membus.trans_dist::WriteResp 4734981 # Transaction distribution -system.membus.trans_dist::SoftPFReq 510 # Transaction distribution -system.membus.trans_dist::SoftPFResp 510 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 135031171 # Request fanout histogram -system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 135031171 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 93c64ae72..e69de29bb 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,648 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.147149 # Number of seconds simulated -sim_ticks 147148719500 # Number of ticks simulated -final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1067474 # Simulator instruction rate (inst/s) -host_op_rate 1072778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1734188097 # Simulator tick rate (ticks/s) -host_mem_usage 402040 # Number of bytes of host memory used -host_seconds 84.85 # Real time elapsed on the host -sim_insts 90576862 # Number of instructions simulated -sim_ops 91026991 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory -system.physmem.bytes_read::total 981760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294297439 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90576862 # Number of instructions committed -system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732305 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054081 # Class of executed instruction -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits -system.cpu.dcache.overall_hits::total 26245827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses -system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks -system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses -system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits -system.cpu.icache.overall_hits::total 107830173 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses -system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2 # number of writebacks -system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits -system.cpu.l2cache.overall_hits::total 932057 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses -system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 792 # Transaction distribution -system.membus.trans_dist::ReadExReq 14548 # Transaction distribution -system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15340 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |