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authorAndreas Hansson <andreas.hansson@arm.com>2015-03-23 06:57:31 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-03-23 06:57:31 -0400
commited08dc31babd83c5c4a439b4d189599dfeea33d1 (patch)
treef66ff8891d7ae7caf95c10272606b929c866cda9 /tests/quick/se/10.mcf/ref/sparc
parent1483496803f8a8618f62adc5439ce435359b36fe (diff)
downloadgem5-ed08dc31babd83c5c4a439b4d189599dfeea33d1.tar.xz
tests: Final reclassification of quick regressions
A few regressions were still considered long, but finished well within the 180 seconds. They are only a handful (mostly mcf in atomic). --HG-- rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/test.py => tests/quick/se/10.mcf/test.py rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/se/30.eon/test.py => tests/quick/se/30.eon/test.py
Diffstat (limited to 'tests/quick/se/10.mcf/ref/sparc')
-rw-r--r--tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini171
-rw-r--r--tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out999
-rwxr-xr-xtests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout26
-rw-r--r--tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt124
5 files changed, 1321 insertions, 0 deletions
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..5a8877655
--- /dev/null
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -0,0 +1,171 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.interrupts]
+type=SparcInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=SparcISA
+eventq_index=0
+
+[system.cpu.itb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
+gid=100
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
@@ -0,0 +1,999 @@
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+***
+95
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
new file mode 100755
index 000000000..1a4f96712
--- /dev/null
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
@@ -0,0 +1 @@
+warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout
new file mode 100755
index 000000000..a8897be0c
--- /dev/null
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:41:52
+gem5 executing on u200540-lin
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 122215823500 because target called exit()
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..c1c851704
--- /dev/null
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -0,0 +1,124 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.122216 # Number of seconds simulated
+sim_ticks 122215823500 # Number of ticks simulated
+final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2069444 # Simulator instruction rate (inst/s)
+host_op_rate 2069529 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1037295392 # Simulator tick rate (ticks/s)
+host_mem_usage 412436 # Number of bytes of host memory used
+host_seconds 117.82 # Real time elapsed on the host
+sim_insts 243825150 # Number of instructions simulated
+sim_ops 243835265 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory
+system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory
+system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory
+system.physmem.num_other::total 3886 # Number of other requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 326641931 # Transaction distribution
+system.membus.trans_dist::ReadResp 326641931 # Transaction distribution
+system.membus.trans_dist::WriteReq 22901951 # Transaction distribution
+system.membus.trans_dist::WriteResp 22901951 # Transaction distribution
+system.membus.trans_dist::SwapReq 3886 # Transaction distribution
+system.membus.trans_dist::SwapResp 3886 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 349547768 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram
+system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 349547768 # Request fanout histogram
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.workload.num_syscalls 443 # Number of system calls
+system.cpu.numCycles 244431648 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 243825150 # Number of instructions committed
+system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
+system.cpu.num_func_calls 4252956 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
+system.cpu.num_int_insts 194726494 # number of integer instructions
+system.cpu.num_fp_insts 11630 # number of float instructions
+system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
+system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
+system.cpu.num_mem_refs 105711441 # number of memory refs
+system.cpu.num_load_insts 82803521 # Number of load instructions
+system.cpu.num_store_insts 22907920 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 29302884 # Number of branches fetched
+system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
+system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
+system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
+system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
+system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 244431613 # Class of executed instruction
+
+---------- End Simulation Statistics ----------