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| author | Steve Reinhardt <stever@gmail.com> | 2013-09-28 15:25:17 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2013-09-28 15:25:17 -0400 |
| commit | fbc1feb39ac19379983ca714f4c7fadcd9fdabf6 (patch) | |
| tree | 59e49142d5930eb044e9fc09d94c5060a810d545 /tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini | |
| parent | e5c319db43751f45b2bcca1d018fc39d4561ef9c (diff) | |
| download | gem5-fbc1feb39ac19379983ca714f4c7fadcd9fdabf6.tar.xz | |
tests: update reference outputs
Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes. There are a few stats.txt updates too, but
they are in the minority.
Diffstat (limited to 'tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini')
| -rw-r--r-- | tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 1686f16ad..b2863a63a 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -94,10 +99,14 @@ max_stack_size=67108864 output=cout system=system +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -108,8 +117,8 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 @@ -117,3 +126,7 @@ null=false range=0:134217727 port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + |