diff options
author | Steve Reinhardt <stever@gmail.com> | 2012-02-29 01:51:39 -0500 |
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committer | Steve Reinhardt <stever@gmail.com> | 2012-02-29 01:51:39 -0500 |
commit | 13e14ba93c8bc40c861d06b30f7a02f5c44514e4 (patch) | |
tree | bd8db6c3f29995ac10ea54e46d333eeb8d9bf86b /tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt | |
parent | 5917fb3292e359fcc53bb9c4a187cc2e8eb67bbd (diff) | |
download | gem5-13e14ba93c8bc40c861d06b30f7a02f5c44514e4.tar.xz |
EIO: update stats (mostly order change, some renames)
Diffstat (limited to 'tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt')
-rw-r--r-- | tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt | 92 |
1 files changed, 53 insertions, 39 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index aaf712409..5065b3dff 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -1,66 +1,80 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5358491 # Simulator instruction rate (inst/s) -host_mem_usage 194108 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 2674844665 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated sim_ticks 250015500 # Number of ticks simulated -system.cpu.dtb.data_accesses 180793 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 180775 # DTB hits -system.cpu.dtb.data_misses 18 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 3174528 # Simulator instruction rate (inst/s) +host_op_rate 3174125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1586983445 # Simulator tick rate (ticks/s) +host_mem_usage 203780 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +sim_insts 500001 # Number of instructions simulated +sim_ops 500001 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 2872676 # Number of bytes read from this memory +system.physmem.bytes_inst_read 2000076 # Number of instructions bytes read from this memory +system.physmem.bytes_written 417562 # Number of bytes written to this memory +system.physmem.num_reads 624454 # Number of read requests responded to by this memory +system.physmem.num_writes 56340 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 11489991621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 7999808012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1670144451 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 13160136072 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 124435 # DTB read hits system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 124443 # DTB read accesses system.cpu.dtb.write_hits 56340 # DTB write hits system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 500032 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 56350 # DTB write accesses +system.cpu.dtb.data_hits 180775 # DTB hits +system.cpu.dtb.data_misses 18 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 180793 # DTB accesses system.cpu.itb.fetch_hits 500019 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 500032 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 500032 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 500032 # Number of busy cycles -system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 500001 # Number of instructions committed +system.cpu.committedOps 500001 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu.num_fp_insts 32 # number of float instructions -system.cpu.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written system.cpu.num_func_calls 14357 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 500001 # Number of instructions executed -system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses +system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls system.cpu.num_int_insts 474689 # number of integer instructions +system.cpu.num_fp_insts 32 # number of float instructions system.cpu.num_int_register_reads 654286 # number of times the integer registers were read system.cpu.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu.num_load_insts 124443 # Number of load instructions +system.cpu.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written system.cpu.num_mem_refs 180793 # number of memory refs +system.cpu.num_load_insts 124443 # Number of load instructions system.cpu.num_store_insts 56350 # Number of store instructions -system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 500032 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- |