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authorSteve Reinhardt <stever@gmail.com>2012-07-23 00:33:05 -0400
committerSteve Reinhardt <stever@gmail.com>2012-07-23 00:33:05 -0400
commit882a4b65bd768de48efca51fb5477f70517a2bfa (patch)
treedf3348aaff02c01c2d119ecd9f4c14d0b861496d /tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic
parent2590a7dd0a563d8548ba13a62c9ea8b82fa464ad (diff)
downloadgem5-882a4b65bd768de48efca51fb5477f70517a2bfa.tar.xz
test: Restore eio ref files clobbered in rev 8800b05e1cb3.
Apparently Nate did a wholesale update of stats files using a binary compiled without eio, resulting in broken refernce outputs.
Diffstat (limited to 'tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic')
-rwxr-xr-xtests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr15
-rwxr-xr-xtests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout11
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt80
3 files changed, 94 insertions, 12 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
index 2ed8852ac..850fc5669 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
@@ -1,9 +1,6 @@
-Traceback (most recent call last):
- File "<string>", line 1, in <module>
- File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
- exec filecode in scope
- File "tests/run.py", line 78, in <module>
- execfile(joinpath(tests_root, category, mode, name, 'test.py'))
- File "tests/quick/se/20.eio-short/test.py", line 29, in <module>
- root.system.cpu.workload = EioProcess(file = binpath('anagram',
-NameError: name 'EioProcess' is not defined
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
index a0bfbf546..94e5c0a9b 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -1,7 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:36:31
-gem5 started May 8 2012 15:37:08
-gem5 executing on piton
+gem5 compiled Feb 29 2012 00:47:21
+gem5 started Feb 29 2012 00:51:57
+gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 250015500 because a thread reached the max instruction count
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index e69de29bb..5065b3dff 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -0,0 +1,80 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000250 # Number of seconds simulated
+sim_ticks 250015500 # Number of ticks simulated
+final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3174528 # Simulator instruction rate (inst/s)
+host_op_rate 3174125 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1586983445 # Simulator tick rate (ticks/s)
+host_mem_usage 203780 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
+sim_insts 500001 # Number of instructions simulated
+sim_ops 500001 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 2872676 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 2000076 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 417562 # Number of bytes written to this memory
+system.physmem.num_reads 624454 # Number of read requests responded to by this memory
+system.physmem.num_writes 56340 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11489991621 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999808012 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1670144451 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13160136072 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 124435 # DTB read hits
+system.cpu.dtb.read_misses 8 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 124443 # DTB read accesses
+system.cpu.dtb.write_hits 56340 # DTB write hits
+system.cpu.dtb.write_misses 10 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 56350 # DTB write accesses
+system.cpu.dtb.data_hits 180775 # DTB hits
+system.cpu.dtb.data_misses 18 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 180793 # DTB accesses
+system.cpu.itb.fetch_hits 500019 # ITB hits
+system.cpu.itb.fetch_misses 13 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 500032 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 18 # Number of system calls
+system.cpu.numCycles 500032 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 500001 # Number of instructions committed
+system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
+system.cpu.num_func_calls 14357 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
+system.cpu.num_int_insts 474689 # number of integer instructions
+system.cpu.num_fp_insts 32 # number of float instructions
+system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
+system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
+system.cpu.num_mem_refs 180793 # number of memory refs
+system.cpu.num_load_insts 124443 # Number of load instructions
+system.cpu.num_store_insts 56350 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 500032 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------