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authorSteve Reinhardt <stever@gmail.com>2012-07-23 00:39:12 -0400
committerSteve Reinhardt <stever@gmail.com>2012-07-23 00:39:12 -0400
commit42596d27e95696e1c9bb0b421ad910091860d11e (patch)
tree90e23bbb23816cbca0c92bf6772ead6f848ae59b /tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
parent882a4b65bd768de48efca51fb5477f70517a2bfa (diff)
downloadgem5-42596d27e95696e1c9bb0b421ad910091860d11e.tar.xz
test: Update eio ref outputs due to recent changes
Actual stats updates covering period since original ref outputs were clobbered.
Diffstat (limited to 'tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini')
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini23
1 files changed, 11 insertions, 12 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 4fea94adf..b45e06437 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
-physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -88,7 +87,7 @@ size=64
[system.cpu.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -120,7 +119,7 @@ size=48
[system.cpu.l2cache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -144,13 +143,12 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -168,19 +166,20 @@ output=cout
system=system
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
file=
+in_addr_map=true
latency=30000
latency_var=0
null=false