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authorSteve Reinhardt <stever@gmail.com>2013-08-24 12:03:10 -0400
committerSteve Reinhardt <stever@gmail.com>2013-08-24 12:03:10 -0400
commitdc18352e3c5f35352341bb783e1d630eb1e810f4 (patch)
tree09e6a33c9db072fa58c4e87f3dea789aec93a7b0 /tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
parentecfe7dc3efb2622fef10a8be39c477148ded3d29 (diff)
downloadgem5-dc18352e3c5f35352341bb783e1d630eb1e810f4.tar.xz
stats: update eio stats
Diffstat (limited to 'tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini')
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini70
1 files changed, 55 insertions, 15 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index dc819fce5..c06c84e34 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -29,12 +30,17 @@ work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
@@ -62,10 +68,10 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -76,22 +82,31 @@ prefetcher=Null
response_latency=2
size=262144
system=system
+tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -102,12 +117,21 @@ prefetcher=Null
response_latency=2
size=131072
system=system
+tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
[system.cpu.interrupts]
type=AlphaInterrupts
@@ -120,10 +144,10 @@ size=48
[system.cpu.l2cache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -134,16 +158,24 @@ prefetcher=Null
response_latency=20
size=2097152
system=system
+tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
[system.cpu.toL2Bus]
type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -164,10 +196,14 @@ max_stack_size=67108864
output=cout
system=system
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
[system.membus]
type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -178,8 +214,8 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
@@ -187,3 +223,7 @@ null=false
range=0:134217727
port=system.membus.master[0]
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+