stats: updates due to recent ruby and x86 changes

Also updates many out of date config files.

4 files changed, 76 insertions, 26 deletions

diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index c59537dfb..dc93f63bb 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -10,13 +10,14 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 init_param=0
 kernel=
+kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=atomic
@@ -37,7 +38,9 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -108,7 +111,7 @@ type=EioProcess
 chkpt=
 errout=cerr
 eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/scratch/nilay/GEM5/gem5/tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
@@ -117,9 +120,19 @@ system=system
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
index f16d8f1f9..b54ad9151 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
@@ -26,13 +26,7 @@
             "type": "CoherentBus", 
             "use_default_range": false
         }, 
-        "voltage_domain": {
-            "eventq_index": 0, 
-            "path": "system.voltage_domain", 
-            "type": "VoltageDomain", 
-            "name": "voltage_domain", 
-            "cxx_class": "VoltageDomain"
-        }, 
+        "kernel_addr_check": true, 
         "physmem": {
             "latency": 3.0000000000000004e-08, 
             "name": "physmem", 
@@ -55,26 +49,44 @@
         "work_begin_ckpt_count": 0, 
         "clk_domain": {
             "name": "clk_domain", 
-            "clock": 1e-09, 
+            "init_perf_level": 0, 
             "eventq_index": 0, 
             "cxx_class": "SrcClockDomain", 
             "path": "system.clk_domain", 
-            "type": "SrcClockDomain"
+            "type": "SrcClockDomain", 
+            "domain_id": -1
         }, 
         "eventq_index": 0, 
+        "dvfs_handler": {
+            "enable": false, 
+            "name": "dvfs_handler", 
+            "transition_latency": 9.999999999999999e-05, 
+            "eventq_index": 0, 
+            "cxx_class": "DVFSHandler", 
+            "path": "system.dvfs_handler", 
+            "type": "DVFSHandler"
+        }, 
         "work_end_exit_count": 0, 
         "type": "System", 
+        "voltage_domain": {
+            "eventq_index": 0, 
+            "path": "system.voltage_domain", 
+            "type": "VoltageDomain", 
+            "name": "voltage_domain", 
+            "cxx_class": "VoltageDomain"
+        }, 
         "cache_line_size": 64, 
         "work_cpus_ckpt_count": 0, 
         "work_begin_exit_count": 0, 
         "path": "system", 
         "cpu_clk_domain": {
             "name": "cpu_clk_domain", 
-            "clock": 5e-10, 
+            "init_perf_level": 0, 
             "eventq_index": 0, 
             "cxx_class": "SrcClockDomain", 
             "path": "system.cpu_clk_domain", 
-            "type": "SrcClockDomain"
+            "type": "SrcClockDomain", 
+            "domain_id": -1
         }, 
         "mem_mode": "atomic", 
         "name": "system", 
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 1136d541a..b2f16aef7 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -10,13 +10,14 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 init_param=0
 kernel=
+kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
@@ -37,7 +38,9 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -217,7 +220,7 @@ type=EioProcess
 chkpt=
 errout=cerr
 eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/scratch/nilay/GEM5/gem5/tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
@@ -226,9 +229,19 @@ system=system
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
index 32695de47..650315faa 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
@@ -25,13 +25,7 @@
             "type": "CoherentBus", 
             "use_default_range": false
         }, 
-        "voltage_domain": {
-            "eventq_index": 0, 
-            "path": "system.voltage_domain", 
-            "type": "VoltageDomain", 
-            "name": "voltage_domain", 
-            "cxx_class": "VoltageDomain"
-        }, 
+        "kernel_addr_check": true, 
         "physmem": {
             "latency": 3.0000000000000004e-08, 
             "name": "physmem", 
@@ -54,26 +48,44 @@
         "work_begin_ckpt_count": 0, 
         "clk_domain": {
             "name": "clk_domain", 
-            "clock": 1e-09, 
+            "init_perf_level": 0, 
             "eventq_index": 0, 
             "cxx_class": "SrcClockDomain", 
             "path": "system.clk_domain", 
-            "type": "SrcClockDomain"
+            "type": "SrcClockDomain", 
+            "domain_id": -1
         }, 
         "eventq_index": 0, 
+        "dvfs_handler": {
+            "enable": false, 
+            "name": "dvfs_handler", 
+            "transition_latency": 9.999999999999999e-05, 
+            "eventq_index": 0, 
+            "cxx_class": "DVFSHandler", 
+            "path": "system.dvfs_handler", 
+            "type": "DVFSHandler"
+        }, 
         "work_end_exit_count": 0, 
         "type": "System", 
+        "voltage_domain": {
+            "eventq_index": 0, 
+            "path": "system.voltage_domain", 
+            "type": "VoltageDomain", 
+            "name": "voltage_domain", 
+            "cxx_class": "VoltageDomain"
+        }, 
         "cache_line_size": 64, 
         "work_cpus_ckpt_count": 0, 
         "work_begin_exit_count": 0, 
         "path": "system", 
         "cpu_clk_domain": {
             "name": "cpu_clk_domain", 
-            "clock": 5e-10, 
+            "init_perf_level": 0, 
             "eventq_index": 0, 
             "cxx_class": "SrcClockDomain", 
             "path": "system.cpu_clk_domain", 
-            "type": "SrcClockDomain"
+            "type": "SrcClockDomain", 
+            "domain_id": -1
         }, 
         "mem_mode": "timing", 
         "name": "system",