stats: update EIO stats

10 files changed, 296 insertions, 129 deletions

diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index ba7d7af16..00511e03a 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=500000
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -140,10 +150,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -158,11 +173,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
index c422d4513..30e912e31 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
@@ -6,43 +6,49 @@
         "mmap_using_noreserve": false, 
         "kernel_addr_check": true, 
         "membus": {
-            "slave": {
-                "peer": [
-                    "system.system_port", 
-                    "system.cpu.icache_port", 
-                    "system.cpu.dcache_port"
-                ], 
-                "role": "SLAVE"
-            }, 
-            "name": "membus", 
             "point_of_coherency": true, 
-            "snoop_filter": null, 
+            "system": "system", 
+            "response_latency": 2, 
+            "cxx_class": "CoherentXBar", 
             "forward_latency": 4, 
             "clk_domain": "system.clk_domain", 
-            "system": "system", 
             "width": 16, 
             "eventq_index": 0, 
+            "default_p_state": "UNDEFINED", 
+            "p_state_clk_gate_max": 1000000000000, 
             "master": {
                 "peer": [
                     "system.physmem.port"
                 ], 
                 "role": "MASTER"
             }, 
-            "response_latency": 2, 
-            "cxx_class": "CoherentXBar", 
+            "type": "CoherentXBar", 
+            "frontend_latency": 3, 
+            "slave": {
+                "peer": [
+                    "system.system_port", 
+                    "system.cpu.icache_port", 
+                    "system.cpu.dcache_port"
+                ], 
+                "role": "SLAVE"
+            }, 
+            "p_state_clk_gate_min": 1000, 
+            "snoop_filter": null, 
+            "power_model": null, 
             "path": "system.membus", 
             "snoop_response_latency": 4, 
-            "type": "CoherentXBar", 
-            "use_default_range": false, 
-            "frontend_latency": 3
+            "name": "membus", 
+            "p_state_clk_gate_bins": 20, 
+            "use_default_range": false
         }, 
         "symbolfile": "", 
         "readfile": "", 
         "thermal_model": null, 
         "cxx_class": "System", 
+        "work_begin_cpu_id_exit": -1, 
         "load_offset": 0, 
         "work_begin_exit_count": 0, 
-        "work_end_ckpt_count": 0, 
+        "p_state_clk_gate_min": 1000, 
         "memories": [
             "system.physmem"
         ], 
@@ -62,7 +68,8 @@
         }, 
         "mem_ranges": [], 
         "eventq_index": 0, 
-        "work_begin_cpu_id_exit": -1, 
+        "default_p_state": "UNDEFINED", 
+        "p_state_clk_gate_max": 1000000000000, 
         "dvfs_handler": {
             "enable": false, 
             "name": "dvfs_handler", 
@@ -88,16 +95,25 @@
         }, 
         "cache_line_size": 64, 
         "boot_osflags": "a", 
+        "system_port": {
+            "peer": "system.membus.slave[0]", 
+            "role": "MASTER"
+        }, 
         "physmem": {
             "range": "0:134217727", 
             "latency": 30000, 
             "name": "physmem", 
+            "p_state_clk_gate_min": 1000, 
             "eventq_index": 0, 
+            "p_state_clk_gate_bins": 20, 
+            "default_p_state": "UNDEFINED", 
             "clk_domain": "system.clk_domain", 
+            "power_model": null, 
             "latency_var": 0, 
             "bandwidth": "73.000000", 
             "conf_table_reported": true, 
             "cxx_class": "SimpleMemory", 
+            "p_state_clk_gate_max": 1000000000000, 
             "path": "system.physmem", 
             "null": false, 
             "type": "SimpleMemory", 
@@ -107,6 +123,7 @@
             }, 
             "in_addr_map": true
         }, 
+        "power_model": null, 
         "work_cpus_ckpt_count": 0, 
         "thermal_components": [], 
         "path": "system", 
@@ -123,13 +140,11 @@
             "type": "SrcClockDomain", 
             "domain_id": -1
         }, 
+        "work_end_ckpt_count": 0, 
         "mem_mode": "atomic", 
         "name": "system", 
         "init_param": 0, 
-        "system_port": {
-            "peer": "system.membus.slave[0]", 
-            "role": "MASTER"
-        }, 
+        "p_state_clk_gate_bins": 20, 
         "load_addr_mask": 1099511627775, 
         "cpu": [
             {
@@ -155,6 +170,8 @@
                 "width": 1, 
                 "checker": null, 
                 "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 1000000000000, 
                 "do_quiesce": true, 
                 "type": "AtomicSimpleCPU", 
                 "fastmem": false, 
@@ -163,6 +180,8 @@
                     "peer": "system.membus.slave[1]", 
                     "role": "MASTER"
                 }, 
+                "p_state_clk_gate_bins": 20, 
+                "p_state_clk_gate_min": 1000, 
                 "interrupts": [
                     {
                         "eventq_index": 0, 
@@ -177,6 +196,7 @@
                     "role": "MASTER"
                 }, 
                 "socket_id": 0, 
+                "power_model": null, 
                 "max_insts_all_threads": 0, 
                 "path": "system.cpu", 
                 "max_loads_any_thread": 0, 
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
index 8af5388f9..d8d1b5864 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
index 0fe3a69ca..deedc77e0 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simp
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  5 2016 19:50:43
-gem5 started Jun  5 2016 20:05:34
-gem5 executing on zizzer, pid 54386
+gem5 compiled Jun 12 2016 19:14:13
+gem5 started Jun 12 2016 19:14:37
+gem5 executing on zizzer, pid 29746
 command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index 2649f373d..de388c316 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.000250                       # Nu
 sim_ticks                                   250015500                       # Number of ticks simulated
 final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1086021                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1085950                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              542974724                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223156                       # Number of bytes of host memory used
-host_seconds                                     0.46                       # Real time elapsed on the host
+host_inst_rate                                1177687                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1177628                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              588821738                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224108                       # Number of bytes of host memory used
+host_seconds                                     0.42                       # Real time elapsed on the host
 sim_insts                                      500001                       # Number of instructions simulated
 sim_ops                                        500001                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED    250015500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst           2000076                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            872600                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              2872676                       # Number of bytes read from this memory
@@ -35,6 +36,7 @@ system.physmem.bw_write::total             1670144451                       # Wr
 system.physmem.bw_total::cpu.inst          7999808012                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          5160328060                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            13160136072                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED    250015500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -69,6 +71,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON       250015500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                           500032                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite                   56350     11.27%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                     500019                       # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED    250015500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq              624454                       # Transaction distribution
 system.membus.trans_dist::ReadResp             624454                       # Transaction distribution
 system.membus.trans_dist::WriteReq              56340                       # Transaction distribution
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 40d27177c..08ecd7e06 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=500000
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -179,12 +209,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -203,8 +238,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -212,10 +252,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -268,10 +313,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -286,11 +336,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
index b426b3129..7a602fb3c 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
@@ -6,42 +6,48 @@
         "mmap_using_noreserve": false, 
         "kernel_addr_check": true, 
         "membus": {
-            "slave": {
-                "peer": [
-                    "system.system_port", 
-                    "system.cpu.l2cache.mem_side"
-                ], 
-                "role": "SLAVE"
-            }, 
-            "name": "membus", 
             "point_of_coherency": true, 
-            "snoop_filter": null, 
+            "system": "system", 
+            "response_latency": 2, 
+            "cxx_class": "CoherentXBar", 
             "forward_latency": 4, 
             "clk_domain": "system.clk_domain", 
-            "system": "system", 
             "width": 16, 
             "eventq_index": 0, 
+            "default_p_state": "UNDEFINED", 
+            "p_state_clk_gate_max": 1000000000000, 
             "master": {
                 "peer": [
                     "system.physmem.port"
                 ], 
                 "role": "MASTER"
             }, 
-            "response_latency": 2, 
-            "cxx_class": "CoherentXBar", 
+            "type": "CoherentXBar", 
+            "frontend_latency": 3, 
+            "slave": {
+                "peer": [
+                    "system.system_port", 
+                    "system.cpu.l2cache.mem_side"
+                ], 
+                "role": "SLAVE"
+            }, 
+            "p_state_clk_gate_min": 1000, 
+            "snoop_filter": null, 
+            "power_model": null, 
             "path": "system.membus", 
             "snoop_response_latency": 4, 
-            "type": "CoherentXBar", 
-            "use_default_range": false, 
-            "frontend_latency": 3
+            "name": "membus", 
+            "p_state_clk_gate_bins": 20, 
+            "use_default_range": false
         }, 
         "symbolfile": "", 
         "readfile": "", 
         "thermal_model": null, 
         "cxx_class": "System", 
+        "work_begin_cpu_id_exit": -1, 
         "load_offset": 0, 
         "work_begin_exit_count": 0, 
-        "work_end_ckpt_count": 0, 
+        "p_state_clk_gate_min": 1000, 
         "memories": [
             "system.physmem"
         ], 
@@ -61,7 +67,8 @@
         }, 
         "mem_ranges": [], 
         "eventq_index": 0, 
-        "work_begin_cpu_id_exit": -1, 
+        "default_p_state": "UNDEFINED", 
+        "p_state_clk_gate_max": 1000000000000, 
         "dvfs_handler": {
             "enable": false, 
             "name": "dvfs_handler", 
@@ -87,16 +94,25 @@
         }, 
         "cache_line_size": 64, 
         "boot_osflags": "a", 
+        "system_port": {
+            "peer": "system.membus.slave[0]", 
+            "role": "MASTER"
+        }, 
         "physmem": {
             "range": "0:134217727", 
             "latency": 30000, 
             "name": "physmem", 
+            "p_state_clk_gate_min": 1000, 
             "eventq_index": 0, 
+            "p_state_clk_gate_bins": 20, 
+            "default_p_state": "UNDEFINED", 
             "clk_domain": "system.clk_domain", 
+            "power_model": null, 
             "latency_var": 0, 
             "bandwidth": "73.000000", 
             "conf_table_reported": true, 
             "cxx_class": "SimpleMemory", 
+            "p_state_clk_gate_max": 1000000000000, 
             "path": "system.physmem", 
             "null": false, 
             "type": "SimpleMemory", 
@@ -106,6 +122,7 @@
             }, 
             "in_addr_map": true
         }, 
+        "power_model": null, 
         "work_cpus_ckpt_count": 0, 
         "thermal_components": [], 
         "path": "system", 
@@ -122,13 +139,11 @@
             "type": "SrcClockDomain", 
             "domain_id": -1
         }, 
+        "work_end_ckpt_count": 0, 
         "mem_mode": "timing", 
         "name": "system", 
         "init_param": 0, 
-        "system_port": {
-            "peer": "system.membus.slave[0]", 
-            "role": "MASTER"
-        }, 
+        "p_state_clk_gate_bins": 20, 
         "load_addr_mask": 1099511627775, 
         "cpu": [
             {
@@ -143,61 +158,6 @@
                     "size": 48
                 }, 
                 "system": "system", 
-                "function_trace": false, 
-                "do_checkpoint_insts": true, 
-                "cxx_class": "TimingSimpleCPU", 
-                "max_loads_all_threads": 0, 
-                "clk_domain": "system.cpu_clk_domain", 
-                "function_trace_start": 0, 
-                "cpu_id": 0, 
-                "checker": null, 
-                "eventq_index": 0, 
-                "toL2Bus": {
-                    "slave": {
-                        "peer": [
-                            "system.cpu.icache.mem_side", 
-                            "system.cpu.dcache.mem_side"
-                        ], 
-                        "role": "SLAVE"
-                    }, 
-                    "name": "toL2Bus", 
-                    "point_of_coherency": false, 
-                    "snoop_filter": {
-                        "name": "snoop_filter", 
-                        "system": "system", 
-                        "max_capacity": 8388608, 
-                        "eventq_index": 0, 
-                        "cxx_class": "SnoopFilter", 
-                        "path": "system.cpu.toL2Bus.snoop_filter", 
-                        "type": "SnoopFilter", 
-                        "lookup_latency": 0
-                    }, 
-                    "forward_latency": 0, 
-                    "clk_domain": "system.cpu_clk_domain", 
-                    "system": "system", 
-                    "width": 32, 
-                    "eventq_index": 0, 
-                    "master": {
-                        "peer": [
-                            "system.cpu.l2cache.cpu_side"
-                        ], 
-                        "role": "MASTER"
-                    }, 
-                    "response_latency": 1, 
-                    "cxx_class": "CoherentXBar", 
-                    "path": "system.cpu.toL2Bus", 
-                    "snoop_response_latency": 1, 
-                    "type": "CoherentXBar", 
-                    "use_default_range": false, 
-                    "frontend_latency": 1
-                }, 
-                "do_quiesce": true, 
-                "type": "TimingSimpleCPU", 
-                "profile": 0, 
-                "icache_port": {
-                    "peer": "system.cpu.icache.cpu_side", 
-                    "role": "MASTER"
-                }, 
                 "icache": {
                     "cpu_side": {
                         "peer": "system.cpu.icache_port", 
@@ -205,47 +165,121 @@
                     }, 
                     "clusivity": "mostly_incl", 
                     "prefetcher": null, 
-                    "clk_domain": "system.cpu_clk_domain", 
+                    "system": "system", 
                     "write_buffers": 8, 
                     "response_latency": 2, 
                     "cxx_class": "Cache", 
                     "size": 131072, 
                     "tags": {
                         "name": "tags", 
+                        "p_state_clk_gate_min": 1000, 
                         "eventq_index": 0, 
-                        "hit_latency": 2, 
+                        "p_state_clk_gate_bins": 20, 
+                        "default_p_state": "UNDEFINED", 
                         "clk_domain": "system.cpu_clk_domain", 
+                        "power_model": null, 
                         "sequential_access": false, 
                         "assoc": 2, 
                         "cxx_class": "LRU", 
+                        "p_state_clk_gate_max": 1000000000000, 
                         "path": "system.cpu.icache.tags", 
+                        "hit_latency": 2, 
                         "block_size": 64, 
                         "type": "LRU", 
                         "size": 131072
                     }, 
-                    "system": "system", 
+                    "clk_domain": "system.cpu_clk_domain", 
                     "max_miss_count": 0, 
                     "eventq_index": 0, 
+                    "default_p_state": "UNDEFINED", 
+                    "p_state_clk_gate_max": 1000000000000, 
                     "mem_side": {
                         "peer": "system.cpu.toL2Bus.slave[0]", 
                         "role": "MASTER"
                     }, 
                     "type": "Cache", 
                     "writeback_clean": true, 
+                    "p_state_clk_gate_min": 1000, 
                     "hit_latency": 2, 
-                    "demand_mshr_reserve": 1, 
                     "tgts_per_mshr": 20, 
+                    "demand_mshr_reserve": 1, 
+                    "power_model": null, 
                     "addr_ranges": [
                         "0:18446744073709551615"
                     ], 
                     "is_read_only": true, 
                     "prefetch_on_access": false, 
                     "path": "system.cpu.icache", 
-                    "name": "icache", 
                     "mshrs": 4, 
+                    "name": "icache", 
+                    "p_state_clk_gate_bins": 20, 
                     "sequential_access": false, 
                     "assoc": 2
                 }, 
+                "function_trace": false, 
+                "do_checkpoint_insts": true, 
+                "cxx_class": "TimingSimpleCPU", 
+                "max_loads_all_threads": 0, 
+                "clk_domain": "system.cpu_clk_domain", 
+                "function_trace_start": 0, 
+                "cpu_id": 0, 
+                "checker": null, 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 1000000000000, 
+                "toL2Bus": {
+                    "point_of_coherency": false, 
+                    "system": "system", 
+                    "response_latency": 1, 
+                    "cxx_class": "CoherentXBar", 
+                    "forward_latency": 0, 
+                    "clk_domain": "system.cpu_clk_domain", 
+                    "width": 32, 
+                    "eventq_index": 0, 
+                    "default_p_state": "UNDEFINED", 
+                    "p_state_clk_gate_max": 1000000000000, 
+                    "master": {
+                        "peer": [
+                            "system.cpu.l2cache.cpu_side"
+                        ], 
+                        "role": "MASTER"
+                    }, 
+                    "type": "CoherentXBar", 
+                    "frontend_latency": 1, 
+                    "slave": {
+                        "peer": [
+                            "system.cpu.icache.mem_side", 
+                            "system.cpu.dcache.mem_side"
+                        ], 
+                        "role": "SLAVE"
+                    }, 
+                    "p_state_clk_gate_min": 1000, 
+                    "snoop_filter": {
+                        "name": "snoop_filter", 
+                        "system": "system", 
+                        "max_capacity": 8388608, 
+                        "eventq_index": 0, 
+                        "cxx_class": "SnoopFilter", 
+                        "path": "system.cpu.toL2Bus.snoop_filter", 
+                        "type": "SnoopFilter", 
+                        "lookup_latency": 0
+                    }, 
+                    "power_model": null, 
+                    "path": "system.cpu.toL2Bus", 
+                    "snoop_response_latency": 1, 
+                    "name": "toL2Bus", 
+                    "p_state_clk_gate_bins": 20, 
+                    "use_default_range": false
+                }, 
+                "do_quiesce": true, 
+                "type": "TimingSimpleCPU", 
+                "profile": 0, 
+                "icache_port": {
+                    "peer": "system.cpu.icache.cpu_side", 
+                    "role": "MASTER"
+                }, 
+                "p_state_clk_gate_bins": 20, 
+                "p_state_clk_gate_min": 1000, 
                 "interrupts": [
                     {
                         "eventq_index": 0, 
@@ -260,6 +294,7 @@
                     "role": "MASTER"
                 }, 
                 "socket_id": 0, 
+                "power_model": null, 
                 "max_insts_all_threads": 0, 
                 "l2cache": {
                     "cpu_side": {
@@ -268,44 +303,54 @@
                     }, 
                     "clusivity": "mostly_incl", 
                     "prefetcher": null, 
-                    "clk_domain": "system.cpu_clk_domain", 
+                    "system": "system", 
                     "write_buffers": 8, 
                     "response_latency": 20, 
                     "cxx_class": "Cache", 
                     "size": 2097152, 
                     "tags": {
                         "name": "tags", 
+                        "p_state_clk_gate_min": 1000, 
                         "eventq_index": 0, 
-                        "hit_latency": 20, 
+                        "p_state_clk_gate_bins": 20, 
+                        "default_p_state": "UNDEFINED", 
                         "clk_domain": "system.cpu_clk_domain", 
+                        "power_model": null, 
                         "sequential_access": false, 
                         "assoc": 8, 
                         "cxx_class": "LRU", 
+                        "p_state_clk_gate_max": 1000000000000, 
                         "path": "system.cpu.l2cache.tags", 
+                        "hit_latency": 20, 
                         "block_size": 64, 
                         "type": "LRU", 
                         "size": 2097152
                     }, 
-                    "system": "system", 
+                    "clk_domain": "system.cpu_clk_domain", 
                     "max_miss_count": 0, 
                     "eventq_index": 0, 
+                    "default_p_state": "UNDEFINED", 
+                    "p_state_clk_gate_max": 1000000000000, 
                     "mem_side": {
                         "peer": "system.membus.slave[1]", 
                         "role": "MASTER"
                     }, 
                     "type": "Cache", 
                     "writeback_clean": false, 
+                    "p_state_clk_gate_min": 1000, 
                     "hit_latency": 20, 
-                    "demand_mshr_reserve": 1, 
                     "tgts_per_mshr": 12, 
+                    "demand_mshr_reserve": 1, 
+                    "power_model": null, 
                     "addr_ranges": [
                         "0:18446744073709551615"
                     ], 
                     "is_read_only": false, 
                     "prefetch_on_access": false, 
                     "path": "system.cpu.l2cache", 
-                    "name": "l2cache", 
                     "mshrs": 20, 
+                    "name": "l2cache", 
+                    "p_state_clk_gate_bins": 20, 
                     "sequential_access": false, 
                     "assoc": 8
                 }, 
@@ -350,44 +395,54 @@
                     }, 
                     "clusivity": "mostly_incl", 
                     "prefetcher": null, 
-                    "clk_domain": "system.cpu_clk_domain", 
+                    "system": "system", 
                     "write_buffers": 8, 
                     "response_latency": 2, 
                     "cxx_class": "Cache", 
                     "size": 262144, 
                     "tags": {
                         "name": "tags", 
+                        "p_state_clk_gate_min": 1000, 
                         "eventq_index": 0, 
-                        "hit_latency": 2, 
+                        "p_state_clk_gate_bins": 20, 
+                        "default_p_state": "UNDEFINED", 
                         "clk_domain": "system.cpu_clk_domain", 
+                        "power_model": null, 
                         "sequential_access": false, 
                         "assoc": 2, 
                         "cxx_class": "LRU", 
+                        "p_state_clk_gate_max": 1000000000000, 
                         "path": "system.cpu.dcache.tags", 
+                        "hit_latency": 2, 
                         "block_size": 64, 
                         "type": "LRU", 
                         "size": 262144
                     }, 
-                    "system": "system", 
+                    "clk_domain": "system.cpu_clk_domain", 
                     "max_miss_count": 0, 
                     "eventq_index": 0, 
+                    "default_p_state": "UNDEFINED", 
+                    "p_state_clk_gate_max": 1000000000000, 
                     "mem_side": {
                         "peer": "system.cpu.toL2Bus.slave[1]", 
                         "role": "MASTER"
                     }, 
                     "type": "Cache", 
                     "writeback_clean": false, 
+                    "p_state_clk_gate_min": 1000, 
                     "hit_latency": 2, 
-                    "demand_mshr_reserve": 1, 
                     "tgts_per_mshr": 20, 
+                    "demand_mshr_reserve": 1, 
+                    "power_model": null, 
                     "addr_ranges": [
                         "0:18446744073709551615"
                     ], 
                     "is_read_only": false, 
                     "prefetch_on_access": false, 
                     "path": "system.cpu.dcache", 
-                    "name": "dcache", 
                     "mshrs": 4, 
+                    "name": "dcache", 
+                    "p_state_clk_gate_bins": 20, 
                     "sequential_access": false, 
                     "assoc": 2
                 }, 
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
index 8af5388f9..d8d1b5864 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
index efdd809be..2df966c7a 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simp
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  5 2016 19:50:43
-gem5 started Jun  5 2016 20:04:44
-gem5 executing on zizzer, pid 54380
+gem5 compiled Jun 12 2016 19:14:13
+gem5 started Jun 12 2016 19:14:35
+gem5 executing on zizzer, pid 29706
 command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index b255a768e..bbacb877f 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.000733                       # Nu
 sim_ticks                                   733071500                       # Number of ticks simulated
 final_tick                                  733071500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 528622                       # Simulator instruction rate (inst/s)
-host_op_rate                                   528606                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              774988448                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232700                       # Number of bytes of host memory used
-host_seconds                                     0.95                       # Real time elapsed on the host
+host_inst_rate                                 714823                       # Simulator instruction rate (inst/s)
+host_op_rate                                   714800                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1047966347                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233664                       # Number of bytes of host memory used
+host_seconds                                     0.70                       # Real time elapsed on the host
 sim_insts                                      500001                       # Number of instructions simulated
 sim_ops                                        500001                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             25792                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             29056                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                54848                       # Number of bytes read from this memory
@@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total           35183471                       # In
 system.physmem.bw_total::cpu.inst            35183471                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            39635970                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               74819441                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -63,6 +65,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON       733071500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                          1466143                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -121,6 +124,7 @@ system.cpu.op_class::MemWrite                   56350     11.27%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                     500019                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           286.668758                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs              180321                       # Total number of references to valid blocks.
@@ -137,6 +141,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          426
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.110840                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses            362004                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses           362004                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data       124120                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total          124120                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data        56201                       # number of WriteReq hits
@@ -223,6 +228,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           264.585152                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs              499617                       # Total number of references to valid blocks.
@@ -237,6 +243,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          403
 system.cpu.icache.tags.occ_task_id_percent::1024     0.196777                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses           1000443                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses          1000443                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst       499617                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total          499617                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst        499617                       # number of demand (read+write) hits
@@ -303,6 +310,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61001.240695
 system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          480.680597                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
@@ -321,6 +329,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          714
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.021912                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             7713                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            7713                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadExReq_misses::cpu.data          139                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total          139                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          403                       # number of ReadCleanReq misses
@@ -441,6 +450,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           718                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq          139                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp          139                       # Transaction distribution
@@ -470,6 +480,7 @@ system.cpu.toL2Bus.respLayer0.occupancy        604500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        681000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED    733071500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                718                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               139                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              139                       # Transaction distribution