diff options
author | Steve Reinhardt <stever@gmail.com> | 2013-06-08 10:28:33 -0400 |
---|---|---|
committer | Steve Reinhardt <stever@gmail.com> | 2013-06-08 10:28:33 -0400 |
commit | bd39adfa98a3032410008a8921346bc9c83b8d82 (patch) | |
tree | 665db7241f57edd3b4a4e7cad03e45527791f669 /tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp | |
parent | 2b582ad9bbe262729b5eb48881b56614f084d707 (diff) | |
download | gem5-bd39adfa98a3032410008a8921346bc9c83b8d82.tar.xz |
Updating EIO regression reference outputs for new stats.
Diffstat (limited to 'tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp')
4 files changed, 101 insertions, 90 deletions
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index 0853f81cf..85ac3f7de 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -29,11 +31,11 @@ system_port=system.membus.slave[1] [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -42,17 +44,22 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu0.tracer width=1 @@ -65,21 +72,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -94,21 +98,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -117,6 +118,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=AlphaInterrupts +[system.cpu0.isa] +type=AlphaISA + [system.cpu0.itb] type=AlphaTLB size=48 @@ -136,11 +140,11 @@ system=system [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=1 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -149,17 +153,22 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu1.tracer width=1 @@ -172,21 +181,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -201,21 +207,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -224,6 +227,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=AlphaInterrupts +[system.cpu1.isa] +type=AlphaISA + [system.cpu1.itb] type=AlphaTLB size=48 @@ -243,11 +249,11 @@ system=system [system.cpu2] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=2 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -256,17 +262,22 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu2.interrupts +isa=system.cpu2.isa itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu2.tracer width=1 @@ -279,21 +290,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port @@ -308,21 +316,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port @@ -331,6 +336,9 @@ mem_side=system.toL2Bus.slave[4] [system.cpu2.interrupts] type=AlphaInterrupts +[system.cpu2.isa] +type=AlphaISA + [system.cpu2.itb] type=AlphaTLB size=48 @@ -350,11 +358,11 @@ system=system [system.cpu3] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=3 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -363,17 +371,22 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu3.interrupts +isa=system.cpu3.isa itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu3.tracer width=1 @@ -386,21 +399,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port @@ -415,21 +425,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port @@ -438,6 +445,9 @@ mem_side=system.toL2Bus.slave[6] [system.cpu3.interrupts] type=AlphaInterrupts +[system.cpu3.isa] +type=AlphaISA + [system.cpu3.itb] type=AlphaTLB size=48 @@ -460,21 +470,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=20 size=4194304 -subblock_size=0 system=system -tgts_per_mshr=16 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] @@ -485,6 +492,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -492,21 +500,22 @@ slave=system.l2c.mem_side system.system_port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 null=false range=0:1073741823 -zero=false port=system.membus.master[0] [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr index 8b296506e..b26c03cc4 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -6,5 +6,3 @@ hack: be nice to actually delete the event here gzip: stdout: Broken pipe gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 93473d0a5..6f7f12863 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 20:21:46 -gem5 started Jul 23 2012 00:28:55 +gem5 compiled Jun 8 2013 10:00:13 +gem5 started Jun 8 2013 10:00:28 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 84894234a..8803a901a 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2922206 # Simulator instruction rate (inst/s) -host_op_rate 2922133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 365280152 # Simulator tick rate (ticks/s) -host_mem_usage 1149344 # Number of bytes of host memory used -host_seconds 0.68 # Real time elapsed on the host +host_inst_rate 3032804 # Simulator instruction rate (inst/s) +host_op_rate 3032728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379104441 # Simulator tick rate (ticks/s) +host_mem_usage 1154504 # Number of bytes of host memory used +host_seconds 0.66 # Real time elapsed on the host sim_insts 2000004 # Number of instructions simulated sim_ops 2000004 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory @@ -57,6 +57,12 @@ system.physmem.bw_total::cpu2.data 116216795 # To system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 877513594 # Throughput (bytes/s) +system.membus.data_through_bus 219392 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.toL2Bus.throughput 977859373 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 244480 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv |