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authorSteve Reinhardt <stever@gmail.com>2013-09-28 15:25:17 -0400
committerSteve Reinhardt <stever@gmail.com>2013-09-28 15:25:17 -0400
commitfbc1feb39ac19379983ca714f4c7fadcd9fdabf6 (patch)
tree59e49142d5930eb044e9fc09d94c5060a810d545 /tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp
parente5c319db43751f45b2bcca1d018fc39d4561ef9c (diff)
downloadgem5-fbc1feb39ac19379983ca714f4c7fadcd9fdabf6.tar.xz
tests: update reference outputs
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
Diffstat (limited to 'tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp')
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini4
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr3
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout6
3 files changed, 5 insertions, 8 deletions
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 1b0504991..03af5b9e4 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
@@ -158,7 +157,6 @@ system=system
[system.cpu1]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=1
@@ -278,7 +276,6 @@ system=system
[system.cpu2]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=2
@@ -398,7 +395,6 @@ system=system
[system.cpu3]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=3
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 8b296506e..0997e3f27 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -4,7 +4,6 @@ warn: Prefetch instructions in Alpha do not do anything
hack: be nice to actually delete the event here
gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+stdout: Broken pipe
gzip: stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index 8dc0648e9..0e186045b 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -1,8 +1,10 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 24 2013 11:53:30
-gem5 started Aug 24 2013 12:01:38
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:40
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second