SE/FS: Make both SE and FS tests available all the time.

--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
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rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
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rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py

9 files changed, 2820 insertions, 0 deletions

diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
new file mode 100644
index 000000000..63867abf6
--- /dev/null
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -0,0 +1,538 @@
+[root]
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+time_sync_spin_threshold=100000000
+
+[system]
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+[system.cpu1]
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+[system.cpu2]
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+type=ExeTracer
+
+[system.cpu3.workload]
+type=EioProcess
+chkpt=
+errout=cerr
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+input=None
+max_stack_size=67108864
+output=cout
+system=system
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=4
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[0]
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.mem_side system.physmem.port[0]
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:1073741823
+zero=false
+port=system.membus.port[1]
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
new file mode 100755
index 000000000..c3b5cc937
--- /dev/null
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -0,0 +1,12 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
+stdout: Broken pipe
+
+gzip: stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
new file mode 100755
index 000000000..6bbd017e9
--- /dev/null
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -0,0 +1,22 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+>>>>Exiting @ tick 250015500 because a thread reached the max instruction count
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
new file mode 100644
index 000000000..f73f5744f
--- /dev/null
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -0,0 +1,776 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                5241411                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1126944                       # Number of bytes of host memory used
+host_seconds                                     0.38                       # Real time elapsed on the host
+host_tick_rate                              654880397                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                     2000004                       # Number of instructions simulated
+sim_seconds                                  0.000250                       # Number of seconds simulated
+sim_ticks                                   250015500                       # Number of ticks simulated
+system.cpu0.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_hits                124111                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses                 324                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_accesses            56340                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_hits                56201                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate        0.002467                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses                139                       # number of WriteReq misses
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.demand_accesses             180775                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.dcache.demand_hits                 180312                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate          0.002561                       # miss rate for demand accesses
+system.cpu0.dcache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.occ_blocks::0           276.872320                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.540766                       # Average percentage of cache occupancy
+system.cpu0.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_hits                180312                       # number of overall hits
+system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate         0.002561                       # miss rate for overall accesses
+system.cpu0.dcache.overall_misses                 463                       # number of overall misses
+system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.replacements                    61                       # number of replacements
+system.cpu0.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.tagsinuse               276.872320                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                  180312                       # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks                      29                       # number of writebacks
+system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu0.dtb.data_acv                            0                       # DTB access violations
+system.cpu0.dtb.data_hits                      180775                       # DTB hits
+system.cpu0.dtb.data_misses                        18                       # DTB misses
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
+system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu0.dtb.read_acv                            0                       # DTB read access violations
+system.cpu0.dtb.read_hits                      124435                       # DTB read hits
+system.cpu0.dtb.read_misses                         8                       # DTB read misses
+system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu0.dtb.write_acv                           0                       # DTB write access violations
+system.cpu0.dtb.write_hits                      56340                       # DTB write hits
+system.cpu0.dtb.write_misses                       10                       # DTB write misses
+system.cpu0.icache.ReadReq_accesses            500019                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_hits                499556                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_rate         0.000926                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses                 463                       # number of ReadReq misses
+system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_refs               1078.954644                       # Average number of references to valid blocks.
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.demand_accesses             500019                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.icache.demand_hits                 499556                       # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate          0.000926                       # miss rate for demand accesses
+system.cpu0.icache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.occ_blocks::0           218.086151                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.425950                       # Average percentage of cache occupancy
+system.cpu0.icache.overall_accesses            500019                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_hits                499556                       # number of overall hits
+system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate         0.000926                       # miss rate for overall accesses
+system.cpu0.icache.overall_misses                 463                       # number of overall misses
+system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.replacements                   152                       # number of replacements
+system.cpu0.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.tagsinuse               218.086151                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                  499556                       # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks                       0                       # number of writebacks
+system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu0.itb.fetch_acv                           0                       # ITB acv
+system.cpu0.itb.fetch_hits                     500019                       # ITB hits
+system.cpu0.itb.fetch_misses                       13                       # ITB misses
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu0.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu0.num_fp_insts                           32                       # number of float instructions
+system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu0.num_insts                          500001                       # Number of instructions executed
+system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu0.num_int_insts                      474689                       # number of integer instructions
+system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu0.num_load_insts                     124443                       # Number of load instructions
+system.cpu0.num_mem_refs                       180793                       # number of memory refs
+system.cpu0.num_store_insts                     56350                       # Number of store instructions
+system.cpu0.workload.num_syscalls                  18                       # Number of system calls
+system.cpu1.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_hits                124111                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses                 324                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_accesses            56340                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_hits                56201                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_rate        0.002467                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses                139                       # number of WriteReq misses
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.demand_accesses             180775                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.dcache.demand_hits                 180312                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate          0.002561                       # miss rate for demand accesses
+system.cpu1.dcache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.occ_blocks::0           276.872320                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.540766                       # Average percentage of cache occupancy
+system.cpu1.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_hits                180312                       # number of overall hits
+system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate         0.002561                       # miss rate for overall accesses
+system.cpu1.dcache.overall_misses                 463                       # number of overall misses
+system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.replacements                    61                       # number of replacements
+system.cpu1.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.tagsinuse               276.872320                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                  180312                       # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks                      29                       # number of writebacks
+system.cpu1.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu1.dtb.data_acv                            0                       # DTB access violations
+system.cpu1.dtb.data_hits                      180775                       # DTB hits
+system.cpu1.dtb.data_misses                        18                       # DTB misses
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
+system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu1.dtb.read_acv                            0                       # DTB read access violations
+system.cpu1.dtb.read_hits                      124435                       # DTB read hits
+system.cpu1.dtb.read_misses                         8                       # DTB read misses
+system.cpu1.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu1.dtb.write_acv                           0                       # DTB write access violations
+system.cpu1.dtb.write_hits                      56340                       # DTB write hits
+system.cpu1.dtb.write_misses                       10                       # DTB write misses
+system.cpu1.icache.ReadReq_accesses            500019                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_hits                499556                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_rate         0.000926                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses                 463                       # number of ReadReq misses
+system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_refs               1078.954644                       # Average number of references to valid blocks.
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.demand_accesses             500019                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.icache.demand_hits                 499556                       # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate          0.000926                       # miss rate for demand accesses
+system.cpu1.icache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.occ_blocks::0           218.086151                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.425950                       # Average percentage of cache occupancy
+system.cpu1.icache.overall_accesses            500019                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_hits                499556                       # number of overall hits
+system.cpu1.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate         0.000926                       # miss rate for overall accesses
+system.cpu1.icache.overall_misses                 463                       # number of overall misses
+system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.replacements                   152                       # number of replacements
+system.cpu1.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.tagsinuse               218.086151                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                  499556                       # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks                       0                       # number of writebacks
+system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu1.itb.fetch_acv                           0                       # ITB acv
+system.cpu1.itb.fetch_hits                     500019                       # ITB hits
+system.cpu1.itb.fetch_misses                       13                       # ITB misses
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu1.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu1.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu1.num_fp_insts                           32                       # number of float instructions
+system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu1.num_insts                          500001                       # Number of instructions executed
+system.cpu1.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu1.num_int_insts                      474689                       # number of integer instructions
+system.cpu1.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu1.num_load_insts                     124443                       # Number of load instructions
+system.cpu1.num_mem_refs                       180793                       # number of memory refs
+system.cpu1.num_store_insts                     56350                       # Number of store instructions
+system.cpu1.workload.num_syscalls                  18                       # Number of system calls
+system.cpu2.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_hits                124111                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_misses                 324                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_accesses            56340                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_hits                56201                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_miss_rate        0.002467                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_misses                139                       # number of WriteReq misses
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
+system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.dcache.demand_accesses             180775                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu2.dcache.demand_hits                 180312                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_rate          0.002561                       # miss rate for demand accesses
+system.cpu2.dcache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.dcache.occ_blocks::0           276.872320                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.540766                       # Average percentage of cache occupancy
+system.cpu2.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.dcache.overall_hits                180312                       # number of overall hits
+system.cpu2.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_rate         0.002561                       # miss rate for overall accesses
+system.cpu2.dcache.overall_misses                 463                       # number of overall misses
+system.cpu2.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.dcache.replacements                    61                       # number of replacements
+system.cpu2.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.tagsinuse               276.872320                       # Cycle average of tags in use
+system.cpu2.dcache.total_refs                  180312                       # Total number of references to valid blocks.
+system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.writebacks                      29                       # number of writebacks
+system.cpu2.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu2.dtb.data_acv                            0                       # DTB access violations
+system.cpu2.dtb.data_hits                      180775                       # DTB hits
+system.cpu2.dtb.data_misses                        18                       # DTB misses
+system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu2.dtb.fetch_acv                           0                       # ITB acv
+system.cpu2.dtb.fetch_hits                          0                       # ITB hits
+system.cpu2.dtb.fetch_misses                        0                       # ITB misses
+system.cpu2.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu2.dtb.read_acv                            0                       # DTB read access violations
+system.cpu2.dtb.read_hits                      124435                       # DTB read hits
+system.cpu2.dtb.read_misses                         8                       # DTB read misses
+system.cpu2.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu2.dtb.write_acv                           0                       # DTB write access violations
+system.cpu2.dtb.write_hits                      56340                       # DTB write hits
+system.cpu2.dtb.write_misses                       10                       # DTB write misses
+system.cpu2.icache.ReadReq_accesses            500019                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_hits                499556                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_miss_rate         0.000926                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_misses                 463                       # number of ReadReq misses
+system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_refs               1078.954644                       # Average number of references to valid blocks.
+system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.icache.demand_accesses             500019                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu2.icache.demand_hits                 499556                       # number of demand (read+write) hits
+system.cpu2.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_rate          0.000926                       # miss rate for demand accesses
+system.cpu2.icache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu2.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.icache.occ_blocks::0           218.086151                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.425950                       # Average percentage of cache occupancy
+system.cpu2.icache.overall_accesses            500019                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.icache.overall_hits                499556                       # number of overall hits
+system.cpu2.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_rate         0.000926                       # miss rate for overall accesses
+system.cpu2.icache.overall_misses                 463                       # number of overall misses
+system.cpu2.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.icache.replacements                   152                       # number of replacements
+system.cpu2.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.icache.tagsinuse               218.086151                       # Cycle average of tags in use
+system.cpu2.icache.total_refs                  499556                       # Total number of references to valid blocks.
+system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.writebacks                       0                       # number of writebacks
+system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu2.itb.data_accesses                       0                       # DTB accesses
+system.cpu2.itb.data_acv                            0                       # DTB access violations
+system.cpu2.itb.data_hits                           0                       # DTB hits
+system.cpu2.itb.data_misses                         0                       # DTB misses
+system.cpu2.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu2.itb.fetch_acv                           0                       # ITB acv
+system.cpu2.itb.fetch_hits                     500019                       # ITB hits
+system.cpu2.itb.fetch_misses                       13                       # ITB misses
+system.cpu2.itb.read_accesses                       0                       # DTB read accesses
+system.cpu2.itb.read_acv                            0                       # DTB read access violations
+system.cpu2.itb.read_hits                           0                       # DTB read hits
+system.cpu2.itb.read_misses                         0                       # DTB read misses
+system.cpu2.itb.write_accesses                      0                       # DTB write accesses
+system.cpu2.itb.write_acv                           0                       # DTB write access violations
+system.cpu2.itb.write_hits                          0                       # DTB write hits
+system.cpu2.itb.write_misses                        0                       # DTB write misses
+system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu2.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu2.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu2.num_fp_insts                           32                       # number of float instructions
+system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu2.num_insts                          500001                       # Number of instructions executed
+system.cpu2.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu2.num_int_insts                      474689                       # number of integer instructions
+system.cpu2.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu2.num_load_insts                     124443                       # Number of load instructions
+system.cpu2.num_mem_refs                       180793                       # number of memory refs
+system.cpu2.num_store_insts                     56350                       # Number of store instructions
+system.cpu2.workload.num_syscalls                  18                       # Number of system calls
+system.cpu3.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_hits                124111                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_misses                 324                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_accesses            56340                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_hits                56201                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_miss_rate        0.002467                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_misses                139                       # number of WriteReq misses
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
+system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.dcache.demand_accesses             180775                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu3.dcache.demand_hits                 180312                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_rate          0.002561                       # miss rate for demand accesses
+system.cpu3.dcache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.dcache.occ_blocks::0           276.872320                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.540766                       # Average percentage of cache occupancy
+system.cpu3.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.dcache.overall_hits                180312                       # number of overall hits
+system.cpu3.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_rate         0.002561                       # miss rate for overall accesses
+system.cpu3.dcache.overall_misses                 463                       # number of overall misses
+system.cpu3.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.dcache.replacements                    61                       # number of replacements
+system.cpu3.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.tagsinuse               276.872320                       # Cycle average of tags in use
+system.cpu3.dcache.total_refs                  180312                       # Total number of references to valid blocks.
+system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.writebacks                      29                       # number of writebacks
+system.cpu3.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu3.dtb.data_acv                            0                       # DTB access violations
+system.cpu3.dtb.data_hits                      180775                       # DTB hits
+system.cpu3.dtb.data_misses                        18                       # DTB misses
+system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu3.dtb.fetch_acv                           0                       # ITB acv
+system.cpu3.dtb.fetch_hits                          0                       # ITB hits
+system.cpu3.dtb.fetch_misses                        0                       # ITB misses
+system.cpu3.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu3.dtb.read_acv                            0                       # DTB read access violations
+system.cpu3.dtb.read_hits                      124435                       # DTB read hits
+system.cpu3.dtb.read_misses                         8                       # DTB read misses
+system.cpu3.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu3.dtb.write_acv                           0                       # DTB write access violations
+system.cpu3.dtb.write_hits                      56340                       # DTB write hits
+system.cpu3.dtb.write_misses                       10                       # DTB write misses
+system.cpu3.icache.ReadReq_accesses            500019                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_hits                499556                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_miss_rate         0.000926                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_misses                 463                       # number of ReadReq misses
+system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_refs               1078.954644                       # Average number of references to valid blocks.
+system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.icache.demand_accesses             500019                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu3.icache.demand_hits                 499556                       # number of demand (read+write) hits
+system.cpu3.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_rate          0.000926                       # miss rate for demand accesses
+system.cpu3.icache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu3.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.icache.occ_blocks::0           218.086151                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.425950                       # Average percentage of cache occupancy
+system.cpu3.icache.overall_accesses            500019                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.icache.overall_hits                499556                       # number of overall hits
+system.cpu3.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_rate         0.000926                       # miss rate for overall accesses
+system.cpu3.icache.overall_misses                 463                       # number of overall misses
+system.cpu3.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.icache.replacements                   152                       # number of replacements
+system.cpu3.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.icache.tagsinuse               218.086151                       # Cycle average of tags in use
+system.cpu3.icache.total_refs                  499556                       # Total number of references to valid blocks.
+system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.writebacks                       0                       # number of writebacks
+system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu3.itb.data_accesses                       0                       # DTB accesses
+system.cpu3.itb.data_acv                            0                       # DTB access violations
+system.cpu3.itb.data_hits                           0                       # DTB hits
+system.cpu3.itb.data_misses                         0                       # DTB misses
+system.cpu3.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu3.itb.fetch_acv                           0                       # ITB acv
+system.cpu3.itb.fetch_hits                     500019                       # ITB hits
+system.cpu3.itb.fetch_misses                       13                       # ITB misses
+system.cpu3.itb.read_accesses                       0                       # DTB read accesses
+system.cpu3.itb.read_acv                            0                       # DTB read access violations
+system.cpu3.itb.read_hits                           0                       # DTB read hits
+system.cpu3.itb.read_misses                         0                       # DTB read misses
+system.cpu3.itb.write_accesses                      0                       # DTB write accesses
+system.cpu3.itb.write_acv                           0                       # DTB write access violations
+system.cpu3.itb.write_hits                          0                       # DTB write hits
+system.cpu3.itb.write_misses                        0                       # DTB write misses
+system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu3.numCycles                          500032                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.num_busy_cycles                    500032                       # Number of busy cycles
+system.cpu3.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu3.num_fp_insts                           32                       # number of float instructions
+system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu3.num_insts                          500001                       # Number of instructions executed
+system.cpu3.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu3.num_int_insts                      474689                       # number of integer instructions
+system.cpu3.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu3.num_load_insts                     124443                       # Number of load instructions
+system.cpu3.num_mem_refs                       180793                       # number of memory refs
+system.cpu3.num_store_insts                     56350                       # Number of store instructions
+system.cpu3.workload.num_syscalls                  18                       # Number of system calls
+system.l2c.ReadExReq_accesses::0                  139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                  139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::2                  139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::3                  139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                    139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                    139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::2                    139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::3                    139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0                    787                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                    787                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2                    787                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::3                    787                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits::0                         69                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                         69                       # number of ReadReq hits
+system.l2c.ReadReq_hits::2                         69                       # number of ReadReq hits
+system.l2c.ReadReq_hits::3                         69                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0              0.912325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.912325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2              0.912325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3              0.912325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          3.649301                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                      718                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                      718                       # number of ReadReq misses
+system.l2c.ReadReq_misses::2                      718                       # number of ReadReq misses
+system.l2c.ReadReq_misses::3                      718                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
+system.l2c.Writeback_accesses::0                  116                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                      116                       # number of Writeback hits
+system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_refs                          0.113233                       # Average number of references to valid blocks.
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.demand_accesses::0                     926                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                     926                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                     926                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::3                     926                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::3               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
+system.l2c.demand_hits::0                          69                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                          69                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                          69                       # number of demand (read+write) hits
+system.l2c.demand_hits::3                          69                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.925486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.925486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               0.925486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::3               0.925486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           3.701944                       # miss rate for demand accesses
+system.l2c.demand_misses::0                       857                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                       857                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                       857                       # number of demand (read+write) misses
+system.l2c.demand_misses::3                       857                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::3                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total             0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.occ_blocks::0                   486.328367                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   486.328367                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                   486.328367                       # Average occupied blocks per context
+system.l2c.occ_blocks::3                   486.328367                       # Average occupied blocks per context
+system.l2c.occ_blocks::4                    17.466765                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.007421                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.007421                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.007421                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.007421                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000267                       # Average percentage of cache occupancy
+system.l2c.overall_accesses::0                    926                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                    926                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                    926                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::3                    926                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::3              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.l2c.overall_hits::0                         69                       # number of overall hits
+system.l2c.overall_hits::1                         69                       # number of overall hits
+system.l2c.overall_hits::2                         69                       # number of overall hits
+system.l2c.overall_hits::3                         69                       # number of overall hits
+system.l2c.overall_hits::total                    276                       # number of overall hits
+system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.925486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.925486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              0.925486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::3              0.925486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          3.701944                       # miss rate for overall accesses
+system.l2c.overall_misses::0                      857                       # number of overall misses
+system.l2c.overall_misses::1                      857                       # number of overall misses
+system.l2c.overall_misses::2                      857                       # number of overall misses
+system.l2c.overall_misses::3                      857                       # number of overall misses
+system.l2c.overall_misses::total                 3428                       # number of overall misses
+system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::3                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total            0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.replacements                             0                       # number of replacements
+system.l2c.sampled_refs                          2932                       # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse                      1962.780232                       # Cycle average of tags in use
+system.l2c.total_refs                             332                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                               0                       # number of writebacks
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
new file mode 100644
index 000000000..fcea1bc67
--- /dev/null
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -0,0 +1,526 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+mem_mode=timing
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dcache dtb icache itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu0.tracer
+workload=system.cpu0.workload
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu0.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu0.workload]
+type=EioProcess
+chkpt=
+errout=cerr
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+input=None
+max_stack_size=67108864
+output=cout
+system=system
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dcache dtb icache itb tracer workload
+checker=Null
+clock=500
+cpu_id=1
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu1.tracer
+workload=system.cpu1.workload
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.dcache_port
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu1.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu1.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu1.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu1.workload]
+type=EioProcess
+chkpt=
+errout=cerr
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+input=None
+max_stack_size=67108864
+output=cout
+system=system
+
+[system.cpu2]
+type=TimingSimpleCPU
+children=dcache dtb icache itb tracer workload
+checker=Null
+clock=500
+cpu_id=2
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu2.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu2.tracer
+workload=system.cpu2.workload
+dcache_port=system.cpu2.dcache.cpu_side
+icache_port=system.cpu2.icache.cpu_side
+
+[system.cpu2.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.dcache_port
+mem_side=system.toL2Bus.port[6]
+
+[system.cpu2.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu2.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.icache_port
+mem_side=system.toL2Bus.port[5]
+
+[system.cpu2.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu2.tracer]
+type=ExeTracer
+
+[system.cpu2.workload]
+type=EioProcess
+chkpt=
+errout=cerr
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+input=None
+max_stack_size=67108864
+output=cout
+system=system
+
+[system.cpu3]
+type=TimingSimpleCPU
+children=dcache dtb icache itb tracer workload
+checker=Null
+clock=500
+cpu_id=3
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu3.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu3.itb
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu3.tracer
+workload=system.cpu3.workload
+dcache_port=system.cpu3.dcache.cpu_side
+icache_port=system.cpu3.icache.cpu_side
+
+[system.cpu3.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.dcache_port
+mem_side=system.toL2Bus.port[8]
+
+[system.cpu3.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu3.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.icache_port
+mem_side=system.toL2Bus.port[7]
+
+[system.cpu3.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu3.tracer]
+type=ExeTracer
+
+[system.cpu3.workload]
+type=EioProcess
+chkpt=
+errout=cerr
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+input=None
+max_stack_size=67108864
+output=cout
+system=system
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=4
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[0]
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.mem_side system.physmem.port[0]
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
new file mode 100755
index 000000000..98d9eda34
--- /dev/null
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -0,0 +1,15 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
new file mode 100755
index 000000000..7540f8e27
--- /dev/null
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -0,0 +1,22 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:04:57
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+>>>>Exiting @ tick 728920000 because a thread reached the max instruction count
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
new file mode 100644
index 000000000..16349cad5
--- /dev/null
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -0,0 +1,876 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                2200513                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209452                       # Number of bytes of host memory used
+host_seconds                                     0.91                       # Real time elapsed on the host
+host_tick_rate                              801856981                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                     1999954                       # Number of instructions simulated
+sim_seconds                                  0.000729                       # Number of seconds simulated
+sim_ticks                                   728920000                       # Number of ticks simulated
+system.cpu0.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 54891.975309                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51891.975309                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_hits                124111                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency      17785000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses                 324                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency     16813000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses            324                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses            56340                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 56064.748201                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53064.748201                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_hits                56201                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency      7793000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate        0.002467                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses                139                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency      7376000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses           139                       # number of WriteReq MSHR misses
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.demand_accesses             180775                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 55244.060475                       # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 52244.060475                       # average overall mshr miss latency
+system.cpu0.dcache.demand_hits                 180312                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency       25578000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate          0.002561                       # miss rate for demand accesses
+system.cpu0.dcache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency     24189000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate     0.002561                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses             463                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.occ_blocks::0           273.518805                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.534216                       # Average percentage of cache occupancy
+system.cpu0.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 55244.060475                       # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_hits                180312                       # number of overall hits
+system.cpu0.dcache.overall_miss_latency      25578000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate         0.002561                       # miss rate for overall accesses
+system.cpu0.dcache.overall_misses                 463                       # number of overall misses
+system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency     24189000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate     0.002561                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses            463                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.replacements                    61                       # number of replacements
+system.cpu0.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.tagsinuse               273.518805                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                  180312                       # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks                      29                       # number of writebacks
+system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu0.dtb.data_acv                            0                       # DTB access violations
+system.cpu0.dtb.data_hits                      180775                       # DTB hits
+system.cpu0.dtb.data_misses                        18                       # DTB misses
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
+system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu0.dtb.read_acv                            0                       # DTB read access violations
+system.cpu0.dtb.read_hits                      124435                       # DTB read hits
+system.cpu0.dtb.read_misses                         8                       # DTB read misses
+system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
+system.cpu0.dtb.write_acv                           0                       # DTB write access violations
+system.cpu0.dtb.write_hits                      56340                       # DTB write hits
+system.cpu0.dtb.write_misses                       10                       # DTB write misses
+system.cpu0.icache.ReadReq_accesses            500020                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 50699.784017                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47699.784017                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits                499557                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency      23474000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate         0.000926                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses                 463                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_miss_latency     22085000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses            463                       # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_refs               1078.956803                       # Average number of references to valid blocks.
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.demand_accesses             500020                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 50699.784017                       # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 47699.784017                       # average overall mshr miss latency
+system.cpu0.icache.demand_hits                 499557                       # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency       23474000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate          0.000926                       # miss rate for demand accesses
+system.cpu0.icache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency     22085000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate     0.000926                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses             463                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.occ_blocks::0           216.390931                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.422639                       # Average percentage of cache occupancy
+system.cpu0.icache.overall_accesses            500020                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 50699.784017                       # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_hits                499557                       # number of overall hits
+system.cpu0.icache.overall_miss_latency      23474000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate         0.000926                       # miss rate for overall accesses
+system.cpu0.icache.overall_misses                 463                       # number of overall misses
+system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency     22085000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate     0.000926                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses            463                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.replacements                   152                       # number of replacements
+system.cpu0.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.tagsinuse               216.390931                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                  499557                       # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks                       0                       # number of writebacks
+system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.fetch_accesses                 500033                       # ITB accesses
+system.cpu0.itb.fetch_acv                           0                       # ITB acv
+system.cpu0.itb.fetch_hits                     500020                       # ITB hits
+system.cpu0.itb.fetch_misses                       13                       # ITB misses
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu0.numCycles                         1457840                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.num_busy_cycles                   1457840                       # Number of busy cycles
+system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu0.num_fp_insts                           32                       # number of float instructions
+system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu0.num_insts                          500001                       # Number of instructions executed
+system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
+system.cpu0.num_int_insts                      474689                       # number of integer instructions
+system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
+system.cpu0.num_load_insts                     124443                       # Number of load instructions
+system.cpu0.num_mem_refs                       180793                       # number of memory refs
+system.cpu0.num_store_insts                     56350                       # Number of store instructions
+system.cpu0.workload.num_syscalls                  18                       # Number of system calls
+system.cpu1.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_hits                124111                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency      17785000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses                 324                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency     16813000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses            324                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses            56339                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 56136.690647                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53136.690647                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_hits                56200                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency      7803000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate        0.002467                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses                139                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency      7386000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses           139                       # number of WriteReq MSHR misses
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_refs                389.440605                       # Average number of references to valid blocks.
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.demand_accesses             180774                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 55265.658747                       # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 52265.658747                       # average overall mshr miss latency
+system.cpu1.dcache.demand_hits                 180311                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency       25588000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate          0.002561                       # miss rate for demand accesses
+system.cpu1.dcache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency     24199000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate     0.002561                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses             463                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.occ_blocks::0           273.512548                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.534204                       # Average percentage of cache occupancy
+system.cpu1.dcache.overall_accesses            180774                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 55265.658747                       # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 52265.658747                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_hits                180311                       # number of overall hits
+system.cpu1.dcache.overall_miss_latency      25588000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate         0.002561                       # miss rate for overall accesses
+system.cpu1.dcache.overall_misses                 463                       # number of overall misses
+system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency     24199000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate     0.002561                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses            463                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.replacements                    61                       # number of replacements
+system.cpu1.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.tagsinuse               273.512548                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                  180311                       # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks                      29                       # number of writebacks
+system.cpu1.dtb.data_accesses                  180792                       # DTB accesses
+system.cpu1.dtb.data_acv                            0                       # DTB access violations
+system.cpu1.dtb.data_hits                      180774                       # DTB hits
+system.cpu1.dtb.data_misses                        18                       # DTB misses
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
+system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
+system.cpu1.dtb.read_acv                            0                       # DTB read access violations
+system.cpu1.dtb.read_hits                      124435                       # DTB read hits
+system.cpu1.dtb.read_misses                         8                       # DTB read misses
+system.cpu1.dtb.write_accesses                  56349                       # DTB write accesses
+system.cpu1.dtb.write_acv                           0                       # DTB write access violations
+system.cpu1.dtb.write_hits                      56339                       # DTB write hits
+system.cpu1.dtb.write_misses                       10                       # DTB write misses
+system.cpu1.icache.ReadReq_accesses            500012                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 50697.624190                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47697.624190                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits                499549                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency      23473000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate         0.000926                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses                 463                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_miss_latency     22084000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses            463                       # number of ReadReq MSHR misses
+system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_refs               1078.939525                       # Average number of references to valid blocks.
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.demand_accesses             500012                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 50697.624190                       # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 47697.624190                       # average overall mshr miss latency
+system.cpu1.icache.demand_hits                 499549                       # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency       23473000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate          0.000926                       # miss rate for demand accesses
+system.cpu1.icache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency     22084000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate     0.000926                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses             463                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.occ_blocks::0           216.386658                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.422630                       # Average percentage of cache occupancy
+system.cpu1.icache.overall_accesses            500012                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 50697.624190                       # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 47697.624190                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_hits                499549                       # number of overall hits
+system.cpu1.icache.overall_miss_latency      23473000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate         0.000926                       # miss rate for overall accesses
+system.cpu1.icache.overall_misses                 463                       # number of overall misses
+system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency     22084000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate     0.000926                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses            463                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.replacements                   152                       # number of replacements
+system.cpu1.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.tagsinuse               216.386658                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                  499549                       # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks                       0                       # number of writebacks
+system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.fetch_accesses                 500025                       # ITB accesses
+system.cpu1.itb.fetch_acv                           0                       # ITB acv
+system.cpu1.itb.fetch_hits                     500012                       # ITB hits
+system.cpu1.itb.fetch_misses                       13                       # ITB misses
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu1.numCycles                         1457840                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.num_busy_cycles                   1457840                       # Number of busy cycles
+system.cpu1.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu1.num_fp_insts                           32                       # number of float instructions
+system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu1.num_insts                          499993                       # Number of instructions executed
+system.cpu1.num_int_alu_accesses               474681                       # Number of integer alu accesses
+system.cpu1.num_int_insts                      474681                       # number of integer instructions
+system.cpu1.num_int_register_reads             654273                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            371536                       # number of times the integer registers were written
+system.cpu1.num_load_insts                     124443                       # Number of load instructions
+system.cpu1.num_mem_refs                       180792                       # number of memory refs
+system.cpu1.num_store_insts                     56349                       # Number of store instructions
+system.cpu1.workload.num_syscalls                  18                       # Number of system calls
+system.cpu2.dcache.ReadReq_accesses            124433                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51919.753086                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_hits                124109                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_miss_latency      17794000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_misses                 324                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency     16822000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_misses            324                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_accesses            56339                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_avg_miss_latency 56093.525180                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53093.525180                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_hits                56200                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_miss_latency      7797000                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_rate        0.002467                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_misses                139                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_mshr_miss_latency      7380000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_rate     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_misses           139                       # number of WriteReq MSHR misses
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_refs                389.436285                       # Average number of references to valid blocks.
+system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.dcache.demand_accesses             180772                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_avg_miss_latency 55272.138229                       # average overall miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency 52272.138229                       # average overall mshr miss latency
+system.cpu2.dcache.demand_hits                 180309                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_miss_latency       25591000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_rate          0.002561                       # miss rate for demand accesses
+system.cpu2.dcache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_miss_latency     24202000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_rate     0.002561                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_misses             463                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.dcache.occ_blocks::0           273.508588                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.534196                       # Average percentage of cache occupancy
+system.cpu2.dcache.overall_accesses            180772                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_avg_miss_latency 55272.138229                       # average overall miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency 52272.138229                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.dcache.overall_hits                180309                       # number of overall hits
+system.cpu2.dcache.overall_miss_latency      25591000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_rate         0.002561                       # miss rate for overall accesses
+system.cpu2.dcache.overall_misses                 463                       # number of overall misses
+system.cpu2.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_miss_latency     24202000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_rate     0.002561                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_misses            463                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.dcache.replacements                    61                       # number of replacements
+system.cpu2.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.tagsinuse               273.508588                       # Cycle average of tags in use
+system.cpu2.dcache.total_refs                  180309                       # Total number of references to valid blocks.
+system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.writebacks                      29                       # number of writebacks
+system.cpu2.dtb.data_accesses                  180790                       # DTB accesses
+system.cpu2.dtb.data_acv                            0                       # DTB access violations
+system.cpu2.dtb.data_hits                      180772                       # DTB hits
+system.cpu2.dtb.data_misses                        18                       # DTB misses
+system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu2.dtb.fetch_acv                           0                       # ITB acv
+system.cpu2.dtb.fetch_hits                          0                       # ITB hits
+system.cpu2.dtb.fetch_misses                        0                       # ITB misses
+system.cpu2.dtb.read_accesses                  124441                       # DTB read accesses
+system.cpu2.dtb.read_acv                            0                       # DTB read access violations
+system.cpu2.dtb.read_hits                      124433                       # DTB read hits
+system.cpu2.dtb.read_misses                         8                       # DTB read misses
+system.cpu2.dtb.write_accesses                  56349                       # DTB write accesses
+system.cpu2.dtb.write_acv                           0                       # DTB write access violations
+system.cpu2.dtb.write_hits                      56339                       # DTB write hits
+system.cpu2.dtb.write_misses                       10                       # DTB write misses
+system.cpu2.icache.ReadReq_accesses            500001                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_avg_miss_latency 50719.222462                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47719.222462                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_hits                499538                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_miss_latency      23483000                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_rate         0.000926                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_misses                 463                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_mshr_miss_latency     22094000                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_misses            463                       # number of ReadReq MSHR misses
+system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_refs               1078.915767                       # Average number of references to valid blocks.
+system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.icache.demand_accesses             500001                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_avg_miss_latency 50719.222462                       # average overall miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency 47719.222462                       # average overall mshr miss latency
+system.cpu2.icache.demand_hits                 499538                       # number of demand (read+write) hits
+system.cpu2.icache.demand_miss_latency       23483000                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_rate          0.000926                       # miss rate for demand accesses
+system.cpu2.icache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu2.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_miss_latency     22094000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_rate     0.000926                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_misses             463                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.icache.occ_blocks::0           216.383557                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.422624                       # Average percentage of cache occupancy
+system.cpu2.icache.overall_accesses            500001                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_avg_miss_latency 50719.222462                       # average overall miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency 47719.222462                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.icache.overall_hits                499538                       # number of overall hits
+system.cpu2.icache.overall_miss_latency      23483000                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_rate         0.000926                       # miss rate for overall accesses
+system.cpu2.icache.overall_misses                 463                       # number of overall misses
+system.cpu2.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_miss_latency     22094000                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_rate     0.000926                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_misses            463                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.icache.replacements                   152                       # number of replacements
+system.cpu2.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.icache.tagsinuse               216.383557                       # Cycle average of tags in use
+system.cpu2.icache.total_refs                  499538                       # Total number of references to valid blocks.
+system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.writebacks                       0                       # number of writebacks
+system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu2.itb.data_accesses                       0                       # DTB accesses
+system.cpu2.itb.data_acv                            0                       # DTB access violations
+system.cpu2.itb.data_hits                           0                       # DTB hits
+system.cpu2.itb.data_misses                         0                       # DTB misses
+system.cpu2.itb.fetch_accesses                 500014                       # ITB accesses
+system.cpu2.itb.fetch_acv                           0                       # ITB acv
+system.cpu2.itb.fetch_hits                     500001                       # ITB hits
+system.cpu2.itb.fetch_misses                       13                       # ITB misses
+system.cpu2.itb.read_accesses                       0                       # DTB read accesses
+system.cpu2.itb.read_acv                            0                       # DTB read access violations
+system.cpu2.itb.read_hits                           0                       # DTB read hits
+system.cpu2.itb.read_misses                         0                       # DTB read misses
+system.cpu2.itb.write_accesses                      0                       # DTB write accesses
+system.cpu2.itb.write_acv                           0                       # DTB write access violations
+system.cpu2.itb.write_hits                          0                       # DTB write hits
+system.cpu2.itb.write_misses                        0                       # DTB write misses
+system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu2.numCycles                         1457840                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.num_busy_cycles                   1457840                       # Number of busy cycles
+system.cpu2.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
+system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu2.num_fp_insts                           32                       # number of float instructions
+system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu2.num_insts                          499982                       # Number of instructions executed
+system.cpu2.num_int_alu_accesses               474671                       # Number of integer alu accesses
+system.cpu2.num_int_insts                      474671                       # number of integer instructions
+system.cpu2.num_int_register_reads             654261                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            371526                       # number of times the integer registers were written
+system.cpu2.num_load_insts                     124440                       # Number of load instructions
+system.cpu2.num_mem_refs                       180789                       # number of memory refs
+system.cpu2.num_store_insts                     56349                       # Number of store instructions
+system.cpu2.workload.num_syscalls                  18                       # Number of system calls
+system.cpu3.dcache.ReadReq_accesses            124431                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_hits                124107                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_miss_latency      17791000                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_misses                 324                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency     16819000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate     0.002604                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_misses            324                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_accesses            56339                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_avg_miss_latency 56093.525180                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53093.525180                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_hits                56200                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_miss_latency      7797000                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_rate        0.002467                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_misses                139                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_mshr_miss_latency      7380000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_rate     0.002467                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_misses           139                       # number of WriteReq MSHR misses
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_refs                389.431965                       # Average number of references to valid blocks.
+system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.dcache.demand_accesses             180770                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_avg_miss_latency 55265.658747                       # average overall miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency 52265.658747                       # average overall mshr miss latency
+system.cpu3.dcache.demand_hits                 180307                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_miss_latency       25588000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_rate          0.002561                       # miss rate for demand accesses
+system.cpu3.dcache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_miss_latency     24199000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_rate     0.002561                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_misses             463                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.dcache.occ_blocks::0           273.505617                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.534191                       # Average percentage of cache occupancy
+system.cpu3.dcache.overall_accesses            180770                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_avg_miss_latency 55265.658747                       # average overall miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency 52265.658747                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.dcache.overall_hits                180307                       # number of overall hits
+system.cpu3.dcache.overall_miss_latency      25588000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_rate         0.002561                       # miss rate for overall accesses
+system.cpu3.dcache.overall_misses                 463                       # number of overall misses
+system.cpu3.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_miss_latency     24199000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_rate     0.002561                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_misses            463                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.dcache.replacements                    61                       # number of replacements
+system.cpu3.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.tagsinuse               273.505617                       # Cycle average of tags in use
+system.cpu3.dcache.total_refs                  180307                       # Total number of references to valid blocks.
+system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.writebacks                      29                       # number of writebacks
+system.cpu3.dtb.data_accesses                  180788                       # DTB accesses
+system.cpu3.dtb.data_acv                            0                       # DTB access violations
+system.cpu3.dtb.data_hits                      180770                       # DTB hits
+system.cpu3.dtb.data_misses                        18                       # DTB misses
+system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu3.dtb.fetch_acv                           0                       # ITB acv
+system.cpu3.dtb.fetch_hits                          0                       # ITB hits
+system.cpu3.dtb.fetch_misses                        0                       # ITB misses
+system.cpu3.dtb.read_accesses                  124439                       # DTB read accesses
+system.cpu3.dtb.read_acv                            0                       # DTB read access violations
+system.cpu3.dtb.read_hits                      124431                       # DTB read hits
+system.cpu3.dtb.read_misses                         8                       # DTB read misses
+system.cpu3.dtb.write_accesses                  56349                       # DTB write accesses
+system.cpu3.dtb.write_acv                           0                       # DTB write access violations
+system.cpu3.dtb.write_hits                      56339                       # DTB write hits
+system.cpu3.dtb.write_misses                       10                       # DTB write misses
+system.cpu3.icache.ReadReq_accesses            499997                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_avg_miss_latency 50738.660907                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47738.660907                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_hits                499534                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_miss_latency      23492000                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_rate         0.000926                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_misses                 463                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_mshr_miss_latency     22103000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate     0.000926                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_misses            463                       # number of ReadReq MSHR misses
+system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_refs               1078.907127                       # Average number of references to valid blocks.
+system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.icache.demand_accesses             499997                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_avg_miss_latency 50738.660907                       # average overall miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency 47738.660907                       # average overall mshr miss latency
+system.cpu3.icache.demand_hits                 499534                       # number of demand (read+write) hits
+system.cpu3.icache.demand_miss_latency       23492000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_rate          0.000926                       # miss rate for demand accesses
+system.cpu3.icache.demand_misses                  463                       # number of demand (read+write) misses
+system.cpu3.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_miss_latency     22103000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_rate     0.000926                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_misses             463                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.icache.occ_blocks::0           216.381810                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.422621                       # Average percentage of cache occupancy
+system.cpu3.icache.overall_accesses            499997                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_avg_miss_latency 50738.660907                       # average overall miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.icache.overall_hits                499534                       # number of overall hits
+system.cpu3.icache.overall_miss_latency      23492000                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_rate         0.000926                       # miss rate for overall accesses
+system.cpu3.icache.overall_misses                 463                       # number of overall misses
+system.cpu3.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_miss_latency     22103000                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_rate     0.000926                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_misses            463                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.icache.replacements                   152                       # number of replacements
+system.cpu3.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
+system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.icache.tagsinuse               216.381810                       # Cycle average of tags in use
+system.cpu3.icache.total_refs                  499534                       # Total number of references to valid blocks.
+system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.writebacks                       0                       # number of writebacks
+system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu3.itb.data_accesses                       0                       # DTB accesses
+system.cpu3.itb.data_acv                            0                       # DTB access violations
+system.cpu3.itb.data_hits                           0                       # DTB hits
+system.cpu3.itb.data_misses                         0                       # DTB misses
+system.cpu3.itb.fetch_accesses                 500010                       # ITB accesses
+system.cpu3.itb.fetch_acv                           0                       # ITB acv
+system.cpu3.itb.fetch_hits                     499997                       # ITB hits
+system.cpu3.itb.fetch_misses                       13                       # ITB misses
+system.cpu3.itb.read_accesses                       0                       # DTB read accesses
+system.cpu3.itb.read_acv                            0                       # DTB read access violations
+system.cpu3.itb.read_hits                           0                       # DTB read hits
+system.cpu3.itb.read_misses                         0                       # DTB read misses
+system.cpu3.itb.write_accesses                      0                       # DTB write accesses
+system.cpu3.itb.write_acv                           0                       # DTB write access violations
+system.cpu3.itb.write_hits                          0                       # DTB write hits
+system.cpu3.itb.write_misses                        0                       # DTB write misses
+system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu3.numCycles                         1457840                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.num_busy_cycles                   1457840                       # Number of busy cycles
+system.cpu3.num_conditional_control_insts        38178                       # number of instructions that are conditional controls
+system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
+system.cpu3.num_fp_insts                           32                       # number of float instructions
+system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
+system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
+system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu3.num_insts                          499978                       # Number of instructions executed
+system.cpu3.num_int_alu_accesses               474667                       # Number of integer alu accesses
+system.cpu3.num_int_insts                      474667                       # number of integer instructions
+system.cpu3.num_int_register_reads             654256                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            371523                       # number of times the integer registers were written
+system.cpu3.num_load_insts                     124438                       # Number of load instructions
+system.cpu3.num_mem_refs                       180787                       # number of memory refs
+system.cpu3.num_store_insts                     56349                       # Number of store instructions
+system.cpu3.workload.num_syscalls                  18                       # Number of system calls
+system.l2c.ReadExReq_accesses::0                  139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                  139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::2                  139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::3                  139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 208021.582734                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 208021.582734                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 208021.582734                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::3 208021.582734                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 832086.330935                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40005.395683                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency            28915000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                    139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                    139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::2                    139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::3                    139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency       22243000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0              4                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1              4                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2              4                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::3              4                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total           16                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses                  556                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0                    787                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                    787                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2                    787                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::3                    787                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   208043.175487                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   208043.175487                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2   208043.175487                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3   208043.175487                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 832172.701950                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40010.793872                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_hits::0                         69                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                         69                       # number of ReadReq hits
+system.l2c.ReadReq_hits::2                         69                       # number of ReadReq hits
+system.l2c.ReadReq_hits::3                         69                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency             149375000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.912325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.912325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2              0.912325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3              0.912325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          3.649301                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                      718                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                      718                       # number of ReadReq misses
+system.l2c.ReadReq_misses::2                      718                       # number of ReadReq misses
+system.l2c.ReadReq_misses::3                      718                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency        114911000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         3.649301                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         3.649301                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2         3.649301                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::3         3.649301                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total    14.597205                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                   2872                       # number of ReadReq MSHR misses
+system.l2c.Writeback_accesses::0                  116                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                      116                       # number of Writeback hits
+system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_refs                          0.113233                       # Average number of references to valid blocks.
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.demand_accesses::0                     926                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                     926                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                     926                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::3                     926                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    208039.673279                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    208039.673279                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2    208039.673279                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::3    208039.673279                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 832158.693116                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  40009.918320                       # average overall mshr miss latency
+system.l2c.demand_hits::0                          69                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                          69                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                          69                       # number of demand (read+write) hits
+system.l2c.demand_hits::3                          69                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency              178290000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.925486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.925486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               0.925486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::3               0.925486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           3.701944                       # miss rate for demand accesses
+system.l2c.demand_misses::0                       857                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                       857                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                       857                       # number of demand (read+write) misses
+system.l2c.demand_misses::3                       857                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency         137154000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          3.701944                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          3.701944                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2          3.701944                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::3          3.701944                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total     14.807775                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                    3428                       # number of demand (read+write) MSHR misses
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.occ_blocks::0                   481.530369                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   481.519672                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                   481.512310                       # Average occupied blocks per context
+system.l2c.occ_blocks::3                   481.507730                       # Average occupied blocks per context
+system.l2c.occ_blocks::4                    17.228456                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.007348                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.007347                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.007347                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.007347                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000263                       # Average percentage of cache occupancy
+system.l2c.overall_accesses::0                    926                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                    926                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                    926                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::3                    926                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   208039.673279                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   208039.673279                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2   208039.673279                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::3   208039.673279                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 832158.693116                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.918320                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.l2c.overall_hits::0                         69                       # number of overall hits
+system.l2c.overall_hits::1                         69                       # number of overall hits
+system.l2c.overall_hits::2                         69                       # number of overall hits
+system.l2c.overall_hits::3                         69                       # number of overall hits
+system.l2c.overall_hits::total                    276                       # number of overall hits
+system.l2c.overall_miss_latency             178290000                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.925486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.925486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              0.925486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::3              0.925486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          3.701944                       # miss rate for overall accesses
+system.l2c.overall_misses::0                      857                       # number of overall misses
+system.l2c.overall_misses::1                      857                       # number of overall misses
+system.l2c.overall_misses::2                      857                       # number of overall misses
+system.l2c.overall_misses::3                      857                       # number of overall misses
+system.l2c.overall_misses::total                 3428                       # number of overall misses
+system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency        137154000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         3.701944                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         3.701944                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2         3.701944                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::3         3.701944                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total    14.807775                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                   3428                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.replacements                             0                       # number of replacements
+system.l2c.sampled_refs                          2932                       # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse                      1943.298536                       # Cycle average of tags in use
+system.l2c.total_refs                             332                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                               0                       # number of writebacks
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/30.eio-mp/test.py b/tests/quick/se/30.eio-mp/test.py
new file mode 100644
index 000000000..3dbb7614a
--- /dev/null
+++ b/tests/quick/se/30.eio-mp/test.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Lisa Hsu
+
+process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
+
+for i in xrange(nb_cores):
+    root.system.cpu[i].workload = process()
+    root.system.cpu[i].max_insts_any_thread = 500000