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authorSteve Reinhardt <stever@gmail.com>2012-02-29 01:51:39 -0500
committerSteve Reinhardt <stever@gmail.com>2012-02-29 01:51:39 -0500
commit13e14ba93c8bc40c861d06b30f7a02f5c44514e4 (patch)
treebd8db6c3f29995ac10ea54e46d333eeb8d9bf86b /tests/quick/se/30.eio-mp
parent5917fb3292e359fcc53bb9c4a187cc2e8eb67bbd (diff)
downloadgem5-13e14ba93c8bc40c861d06b30f7a02f5c44514e4.tar.xz
EIO: update stats (mostly order change, some renames)
Diffstat (limited to 'tests/quick/se/30.eio-mp')
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini169
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr10
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout16
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt1331
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini169
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr9
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout16
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt1863
8 files changed, 1896 insertions, 1687 deletions
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index 63867abf6..f80f13394 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,8 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -17,19 +26,22 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.slave[1]
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu0.interrupts
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=500000
@@ -37,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -58,26 +71,19 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
[system.cpu0.dtb]
type=AlphaTLB
@@ -94,26 +100,22 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.interrupts]
+type=AlphaInterrupts
[system.cpu0.itb]
type=AlphaTLB
@@ -134,16 +136,18 @@ system=system
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=1
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu1.interrupts
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=500000
@@ -151,6 +155,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -172,26 +177,19 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
[system.cpu1.dtb]
type=AlphaTLB
@@ -208,26 +206,22 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
+
+[system.cpu1.interrupts]
+type=AlphaInterrupts
[system.cpu1.itb]
type=AlphaTLB
@@ -248,16 +242,18 @@ system=system
[system.cpu2]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=2
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu2.interrupts
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=500000
@@ -265,6 +261,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -286,26 +283,19 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
[system.cpu2.dtb]
type=AlphaTLB
@@ -322,26 +312,22 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
+
+[system.cpu2.interrupts]
+type=AlphaInterrupts
[system.cpu2.itb]
type=AlphaTLB
@@ -362,16 +348,18 @@ system=system
[system.cpu3]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=3
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu3.interrupts
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=500000
@@ -379,6 +367,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -400,26 +389,19 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
[system.cpu3.dtb]
type=AlphaTLB
@@ -436,26 +418,22 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
+
+[system.cpu3.interrupts]
+type=AlphaInterrupts
[system.cpu3.itb]
type=AlphaTLB
@@ -485,26 +463,19 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
[system.membus]
type=Bus
@@ -514,7 +485,8 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.mem_side system.physmem.port[0]
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
[system.physmem]
type=PhysicalMemory
@@ -524,7 +496,7 @@ latency_var=0
null=false
range=0:1073741823
zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
[system.toL2Bus]
type=Bus
@@ -534,5 +506,6 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index c3b5cc937..8b296506e 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -1,12 +1,10 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
hack: be nice to actually delete the event here
gzip: stdout: Broken pipe
-stdout: Broken pipe
+
+gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 6bbd017e9..9e07934a0 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 11:58:24
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
+gem5 compiled Feb 29 2012 00:47:21
+gem5 started Feb 29 2012 00:51:57
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index f73f5744f..8880fe952 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,776 +1,749 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 5241411 # Simulator instruction rate (inst/s)
-host_mem_usage 1126944 # Number of bytes of host memory used
-host_seconds 0.38 # Real time elapsed on the host
-host_tick_rate 654880397 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2000004 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
sim_ticks 250015500 # Number of ticks simulated
-system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.540766 # Average percentage of cache occupancy
-system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180312 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 463 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements 61 # number of replacements
-system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 29 # number of writebacks
-system.cpu0.dtb.data_accesses 180793 # DTB accesses
-system.cpu0.dtb.data_acv 0 # DTB access violations
-system.cpu0.dtb.data_hits 180775 # DTB hits
-system.cpu0.dtb.data_misses 18 # DTB misses
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
+final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3384594 # Simulator instruction rate (inst/s)
+host_op_rate 3384489 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 423074550 # Simulator tick rate (ticks/s)
+host_mem_usage 1140672 # Number of bytes of host memory used
+host_seconds 0.59 # Real time elapsed on the host
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+system.physmem.bytes_read 219392 # Number of bytes read from this memory
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+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 877513594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 412646416 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 877513594 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.read_accesses 124443 # DTB read accesses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
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system.cpu0.dtb.read_hits 124435 # DTB read hits
system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.write_accesses 56350 # DTB write accesses
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system.cpu0.dtb.write_hits 56340 # DTB write hits
system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
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-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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-system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits
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-system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
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-system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
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-system.cpu0.icache.writebacks 0 # number of writebacks
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-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_hits 0 # DTB hits
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-system.cpu0.itb.fetch_accesses 500032 # ITB accesses
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system.cpu0.itb.fetch_hits 500019 # ITB hits
system.cpu0.itb.fetch_misses 13 # ITB misses
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.read_acv 0 # DTB read access violations
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
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system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
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+system.cpu0.itb.data_acv 0 # DTB access violations
+system.cpu0.itb.data_accesses 0 # DTB accesses
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system.cpu0.numCycles 500032 # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.num_busy_cycles 500032 # Number of busy cycles
-system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
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system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu0.num_fp_insts 32 # number of float instructions
-system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu0.num_func_calls 14357 # number of times a function call or return occured
-system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_insts 500001 # Number of instructions executed
-system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
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system.cpu0.num_int_insts 474689 # number of integer instructions
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system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu0.num_load_insts 124443 # Number of load instructions
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system.cpu0.num_mem_refs 180793 # number of memory refs
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system.cpu0.num_store_insts 56350 # Number of store instructions
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-system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
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-system.cpu1.dcache.WriteReq_hits 56201 # number of WriteReq hits
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-system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
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-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.dcache.replacements 61 # number of replacements
-system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
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-system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use
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-system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 29 # number of writebacks
-system.cpu1.dtb.data_accesses 180793 # DTB accesses
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system.cpu1.dtb.fetch_misses 0 # ITB misses
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system.cpu1.dtb.read_hits 124435 # DTB read hits
system.cpu1.dtb.read_misses 8 # DTB read misses
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-system.cpu1.dtb.write_acv 0 # DTB write access violations
+system.cpu1.dtb.read_acv 0 # DTB read access violations
+system.cpu1.dtb.read_accesses 124443 # DTB read accesses
system.cpu1.dtb.write_hits 56340 # DTB write hits
system.cpu1.dtb.write_misses 10 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
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-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits
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-system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
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-system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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-system.cpu1.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
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-system.cpu1.itb.data_hits 0 # DTB hits
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-system.cpu1.itb.fetch_accesses 500032 # ITB accesses
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system.cpu1.itb.fetch_hits 500019 # ITB hits
system.cpu1.itb.fetch_misses 13 # ITB misses
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.read_acv 0 # DTB read access violations
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system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
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system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
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system.cpu1.numCycles 500032 # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
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-system.cpu1.num_conditional_control_insts 38180 # number of instructions that are conditional controls
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+system.cpu1.committedInsts 500001 # Number of instructions committed
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system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu1.num_fp_insts 32 # number of float instructions
-system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu1.num_func_calls 14357 # number of times a function call or return occured
-system.cpu1.num_idle_cycles 0 # Number of idle cycles
-system.cpu1.num_insts 500001 # Number of instructions executed
-system.cpu1.num_int_alu_accesses 474689 # Number of integer alu accesses
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system.cpu1.num_int_insts 474689 # number of integer instructions
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system.cpu1.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu1.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu1.num_load_insts 124443 # Number of load instructions
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system.cpu1.num_mem_refs 180793 # number of memory refs
+system.cpu1.num_load_insts 124443 # Number of load instructions
system.cpu1.num_store_insts 56350 # Number of store instructions
-system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
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-system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
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-system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
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-system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
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-system.cpu2.dcache.replacements 61 # number of replacements
-system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
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-system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use
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-system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.writebacks 29 # number of writebacks
-system.cpu2.dtb.data_accesses 180793 # DTB accesses
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-system.cpu2.dtb.data_misses 18 # DTB misses
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+system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks.
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+system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor
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system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
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-system.cpu2.dtb.read_acv 0 # DTB read access violations
+system.cpu2.dtb.fetch_acv 0 # ITB acv
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system.cpu2.dtb.read_hits 124435 # DTB read hits
system.cpu2.dtb.read_misses 8 # DTB read misses
-system.cpu2.dtb.write_accesses 56350 # DTB write accesses
-system.cpu2.dtb.write_acv 0 # DTB write access violations
+system.cpu2.dtb.read_acv 0 # DTB read access violations
+system.cpu2.dtb.read_accesses 124443 # DTB read accesses
system.cpu2.dtb.write_hits 56340 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits
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-system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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-system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
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-system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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-system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu2.icache.occ_percent::0 0.425950 # Average percentage of cache occupancy
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-system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency
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-system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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-system.cpu2.itb.fetch_accesses 500032 # ITB accesses
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system.cpu2.itb.fetch_hits 500019 # ITB hits
system.cpu2.itb.fetch_misses 13 # ITB misses
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+system.cpu2.itb.fetch_accesses 500032 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
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system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
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system.cpu2.numCycles 500032 # number of cpu cycles simulated
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
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+system.cpu2.committedInsts 500001 # Number of instructions committed
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system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
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-system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu2.num_func_calls 14357 # number of times a function call or return occured
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-system.cpu2.num_insts 500001 # Number of instructions executed
-system.cpu2.num_int_alu_accesses 474689 # Number of integer alu accesses
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system.cpu2.num_int_insts 474689 # number of integer instructions
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system.cpu2.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu2.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu2.num_load_insts 124443 # Number of load instructions
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system.cpu2.num_mem_refs 180793 # number of memory refs
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system.cpu2.num_store_insts 56350 # Number of store instructions
-system.cpu2.workload.num_syscalls 18 # Number of system calls
-system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_hits 56201 # number of WriteReq hits
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-system.cpu3.dcache.writebacks 29 # number of writebacks
-system.cpu3.dtb.data_accesses 180793 # DTB accesses
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+system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
+system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
+system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
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+system.cpu2.dcache.writebacks::total 29 # number of writebacks
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system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
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+system.cpu3.dtb.fetch_acv 0 # ITB acv
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system.cpu3.dtb.read_hits 124435 # DTB read hits
system.cpu3.dtb.read_misses 8 # DTB read misses
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-system.cpu3.dtb.write_acv 0 # DTB write access violations
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system.cpu3.dtb.write_hits 56340 # DTB write hits
system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits
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-system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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-system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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-system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
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-system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use
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-system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.writebacks 0 # number of writebacks
-system.cpu3.idle_fraction 0 # Percentage of idle cycles
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-system.cpu3.itb.data_acv 0 # DTB access violations
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-system.cpu3.itb.fetch_accesses 500032 # ITB accesses
-system.cpu3.itb.fetch_acv 0 # ITB acv
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+system.cpu3.dtb.data_accesses 180793 # DTB accesses
system.cpu3.itb.fetch_hits 500019 # ITB hits
system.cpu3.itb.fetch_misses 13 # ITB misses
-system.cpu3.itb.read_accesses 0 # DTB read accesses
-system.cpu3.itb.read_acv 0 # DTB read access violations
+system.cpu3.itb.fetch_acv 0 # ITB acv
+system.cpu3.itb.fetch_accesses 500032 # ITB accesses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
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+system.cpu3.itb.read_acv 0 # DTB read access violations
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system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
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system.cpu3.numCycles 500032 # number of cpu cycles simulated
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system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu3.num_int_insts 474689 # number of integer instructions
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system.cpu3.num_int_register_writes 371542 # number of times the integer registers were written
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system.cpu3.num_mem_refs 180793 # number of memory refs
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+system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 69 # number of demand (read+write) hits
-system.l2c.demand_hits::1 69 # number of demand (read+write) hits
-system.l2c.demand_hits::2 69 # number of demand (read+write) hits
-system.l2c.demand_hits::3 69 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses
-system.l2c.demand_misses::0 857 # number of demand (read+write) misses
-system.l2c.demand_misses::1 857 # number of demand (read+write) misses
-system.l2c.demand_misses::2 857 # number of demand (read+write) misses
-system.l2c.demand_misses::3 857 # number of demand (read+write) misses
-system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context
-system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context
-system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context
-system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context
-system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_percent::3 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_percent::4 0.000267 # Average percentage of cache occupancy
-system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 69 # number of overall hits
-system.l2c.overall_hits::1 69 # number of overall hits
-system.l2c.overall_hits::2 69 # number of overall hits
-system.l2c.overall_hits::3 69 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses
-system.l2c.overall_misses::0 857 # number of overall misses
-system.l2c.overall_misses::1 857 # number of overall misses
-system.l2c.overall_misses::2 857 # number of overall misses
-system.l2c.overall_misses::3 857 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use
-system.l2c.total_refs 332 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 0 # number of writebacks
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index fcea1bc67..2501d9722 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,8 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -17,19 +26,22 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.slave[1]
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu0.interrupts
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=500000
@@ -37,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu0.tracer
@@ -55,26 +68,19 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
[system.cpu0.dtb]
type=AlphaTLB
@@ -91,26 +97,22 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.interrupts]
+type=AlphaInterrupts
[system.cpu0.itb]
type=AlphaTLB
@@ -131,16 +133,18 @@ system=system
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=1
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu1.interrupts
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=500000
@@ -148,6 +152,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu1.tracer
@@ -166,26 +171,19 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
[system.cpu1.dtb]
type=AlphaTLB
@@ -202,26 +200,22 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
+
+[system.cpu1.interrupts]
+type=AlphaInterrupts
[system.cpu1.itb]
type=AlphaTLB
@@ -242,16 +236,18 @@ system=system
[system.cpu2]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=2
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu2.interrupts
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=500000
@@ -259,6 +255,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu2.tracer
@@ -277,26 +274,19 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
[system.cpu2.dtb]
type=AlphaTLB
@@ -313,26 +303,22 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
+
+[system.cpu2.interrupts]
+type=AlphaInterrupts
[system.cpu2.itb]
type=AlphaTLB
@@ -353,16 +339,18 @@ system=system
[system.cpu3]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=3
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu3.interrupts
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=500000
@@ -370,6 +358,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu3.tracer
@@ -388,26 +377,19 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
[system.cpu3.dtb]
type=AlphaTLB
@@ -424,26 +406,22 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
+
+[system.cpu3.interrupts]
+type=AlphaInterrupts
[system.cpu3.itb]
type=AlphaTLB
@@ -473,26 +451,19 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
[system.membus]
type=Bus
@@ -502,7 +473,8 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.mem_side system.physmem.port[0]
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
[system.physmem]
type=PhysicalMemory
@@ -512,7 +484,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
[system.toL2Bus]
type=Bus
@@ -522,5 +494,6 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 98d9eda34..8b296506e 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -1,9 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
hack: be nice to actually delete the event here
gzip: stdout: Broken pipe
@@ -11,5 +8,3 @@ gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index 7540f8e27..ae6fe41da 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:04:57
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
+gem5 compiled Feb 29 2012 00:47:21
+gem5 started Feb 29 2012 00:51:57
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 16349cad5..08b853160 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,876 +1,1181 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2200513 # Simulator instruction rate (inst/s)
-host_mem_usage 209452 # Number of bytes of host memory used
-host_seconds 0.91 # Real time elapsed on the host
-host_tick_rate 801856981 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1999954 # Number of instructions simulated
sim_seconds 0.000729 # Number of seconds simulated
sim_ticks 728920000 # Number of ticks simulated
-system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 56064.748201 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53064.748201 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 7793000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 7376000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 55244.060475 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 25578000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 24189000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_blocks::0 273.518805 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.534216 # Average percentage of cache occupancy
-system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 55244.060475 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180312 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 25578000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 463 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 24189000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements 61 # number of replacements
-system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 273.518805 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 29 # number of writebacks
-system.cpu0.dtb.data_accesses 180793 # DTB accesses
-system.cpu0.dtb.data_acv 0 # DTB access violations
-system.cpu0.dtb.data_hits 180775 # DTB hits
-system.cpu0.dtb.data_misses 18 # DTB misses
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
+final_tick 728920000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1560894 # Simulator instruction rate (inst/s)
+host_op_rate 1560871 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 568880584 # Simulator tick rate (ticks/s)
+host_mem_usage 223172 # Number of bytes of host memory used
+host_seconds 1.28 # Real time elapsed on the host
+sim_insts 1999954 # Number of instructions simulated
+sim_ops 1999954 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 219392 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 103168 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 3428 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 300982275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 141535422 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 300982275 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.read_accesses 124443 # DTB read accesses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
+system.cpu0.dtb.fetch_acv 0 # ITB acv
+system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 124435 # DTB read hits
system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.write_accesses 56350 # DTB write accesses
-system.cpu0.dtb.write_acv 0 # DTB write access violations
+system.cpu0.dtb.read_acv 0 # DTB read access violations
+system.cpu0.dtb.read_accesses 124443 # DTB read accesses
system.cpu0.dtb.write_hits 56340 # DTB write hits
system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 50699.784017 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47699.784017 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 23474000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 22085000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 50699.784017 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 23474000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 22085000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_blocks::0 216.390931 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.422639 # Average percentage of cache occupancy
-system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 50699.784017 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 499557 # number of overall hits
-system.cpu0.icache.overall_miss_latency 23474000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 463 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 22085000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements 152 # number of replacements
-system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use
-system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_hits 0 # DTB hits
-system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.fetch_accesses 500033 # ITB accesses
-system.cpu0.itb.fetch_acv 0 # ITB acv
+system.cpu0.dtb.write_acv 0 # DTB write access violations
+system.cpu0.dtb.write_accesses 56350 # DTB write accesses
+system.cpu0.dtb.data_hits 180775 # DTB hits
+system.cpu0.dtb.data_misses 18 # DTB misses
+system.cpu0.dtb.data_acv 0 # DTB access violations
+system.cpu0.dtb.data_accesses 180793 # DTB accesses
system.cpu0.itb.fetch_hits 500020 # ITB hits
system.cpu0.itb.fetch_misses 13 # ITB misses
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.read_acv 0 # DTB read access violations
+system.cpu0.itb.fetch_acv 0 # ITB acv
+system.cpu0.itb.fetch_accesses 500033 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.write_acv 0 # DTB write access violations
+system.cpu0.itb.read_acv 0 # DTB read access violations
+system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu0.itb.write_acv 0 # DTB write access violations
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.data_hits 0 # DTB hits
+system.cpu0.itb.data_misses 0 # DTB misses
+system.cpu0.itb.data_acv 0 # DTB access violations
+system.cpu0.itb.data_accesses 0 # DTB accesses
+system.cpu0.workload.num_syscalls 18 # Number of system calls
system.cpu0.numCycles 1457840 # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.num_busy_cycles 1457840 # Number of busy cycles
-system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 500001 # Number of instructions committed
+system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu0.num_fp_insts 32 # number of float instructions
-system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu0.num_func_calls 14357 # number of times a function call or return occured
-system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_insts 500001 # Number of instructions executed
-system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
+system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
system.cpu0.num_int_insts 474689 # number of integer instructions
+system.cpu0.num_fp_insts 32 # number of float instructions
system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu0.num_load_insts 124443 # Number of load instructions
+system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu0.num_mem_refs 180793 # number of memory refs
+system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_store_insts 56350 # Number of store instructions
-system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 56136.690647 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53136.690647 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_hits 56200 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 7803000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency 7386000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 180774 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 180311 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
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+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52244.060475 # average overall mshr miss latency
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system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
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system.cpu1.dtb.read_hits 124435 # DTB read hits
system.cpu1.dtb.read_misses 8 # DTB read misses
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system.cpu1.dtb.write_misses 10 # DTB write misses
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system.cpu1.itb.read_misses 0 # DTB read misses
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system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu1.numCycles 1457840 # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.num_busy_cycles 1457840 # Number of busy cycles
-system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls
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system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu1.num_fp_insts 32 # number of float instructions
-system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu1.num_func_calls 14357 # number of times a function call or return occured
-system.cpu1.num_idle_cycles 0 # Number of idle cycles
-system.cpu1.num_insts 499993 # Number of instructions executed
-system.cpu1.num_int_alu_accesses 474681 # Number of integer alu accesses
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system.cpu1.num_int_insts 474681 # number of integer instructions
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system.cpu1.num_int_register_reads 654273 # number of times the integer registers were read
system.cpu1.num_int_register_writes 371536 # number of times the integer registers were written
-system.cpu1.num_load_insts 124443 # Number of load instructions
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system.cpu1.num_mem_refs 180792 # number of memory refs
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system.cpu1.num_store_insts 56349 # Number of store instructions
-system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu2.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_hits 124109 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_hits 56200 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles
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-system.cpu2.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
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-system.cpu2.dcache.demand_accesses 180772 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_avg_miss_latency 55272.138229 # average overall miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency
-system.cpu2.dcache.demand_hits 180309 # number of demand (read+write) hits
-system.cpu2.dcache.demand_miss_latency 25591000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
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-system.cpu2.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
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-system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.occ_blocks::0 273.508588 # Average occupied blocks per context
-system.cpu2.dcache.occ_percent::0 0.534196 # Average percentage of cache occupancy
-system.cpu2.dcache.overall_accesses 180772 # number of overall (read+write) accesses
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-system.cpu2.dcache.overall_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.overall_hits 180309 # number of overall hits
-system.cpu2.dcache.overall_miss_latency 25591000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
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-system.cpu2.dcache.overall_mshr_misses 463 # number of overall MSHR misses
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-system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
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-system.cpu2.dcache.tagsinuse 273.508588 # Cycle average of tags in use
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-system.cpu2.dcache.writebacks 29 # number of writebacks
-system.cpu2.dtb.data_accesses 180790 # DTB accesses
-system.cpu2.dtb.data_acv 0 # DTB access violations
-system.cpu2.dtb.data_hits 180772 # DTB hits
-system.cpu2.dtb.data_misses 18 # DTB misses
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-system.cpu2.dtb.fetch_acv 0 # ITB acv
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+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47697.624190 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47697.624190 # average overall mshr miss latency
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+system.cpu1.dcache.WriteReq_miss_latency::total 7803000 # number of WriteReq miss cycles
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+system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
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+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 55265.658747 # average overall miss latency
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+system.cpu1.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
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+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52265.658747 # average overall mshr miss latency
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
-system.cpu2.dtb.read_accesses 124441 # DTB read accesses
-system.cpu2.dtb.read_acv 0 # DTB read access violations
+system.cpu2.dtb.fetch_acv 0 # ITB acv
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system.cpu2.dtb.read_hits 124433 # DTB read hits
system.cpu2.dtb.read_misses 8 # DTB read misses
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-system.cpu2.dtb.write_acv 0 # DTB write access violations
+system.cpu2.dtb.read_acv 0 # DTB read access violations
+system.cpu2.dtb.read_accesses 124441 # DTB read accesses
system.cpu2.dtb.write_hits 56339 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.icache.ReadReq_accesses 500001 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_avg_miss_latency 50719.222462 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47719.222462 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_hits 499538 # number of ReadReq hits
-system.cpu2.icache.ReadReq_miss_latency 23483000 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu2.icache.ReadReq_mshr_miss_latency 22094000 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_refs 1078.915767 # Average number of references to valid blocks.
-system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu2.icache.demand_accesses 500001 # number of demand (read+write) accesses
-system.cpu2.icache.demand_avg_miss_latency 50719.222462 # average overall miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency
-system.cpu2.icache.demand_hits 499538 # number of demand (read+write) hits
-system.cpu2.icache.demand_miss_latency 23483000 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_miss_latency 22094000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
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-system.cpu2.itb.data_acv 0 # DTB access violations
-system.cpu2.itb.data_hits 0 # DTB hits
-system.cpu2.itb.data_misses 0 # DTB misses
-system.cpu2.itb.fetch_accesses 500014 # ITB accesses
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system.cpu2.itb.fetch_hits 500001 # ITB hits
system.cpu2.itb.fetch_misses 13 # ITB misses
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system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
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system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
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system.cpu2.numCycles 1457840 # number of cpu cycles simulated
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system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
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system.cpu2.num_func_calls 14357 # number of times a function call or return occured
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-system.cpu2.num_insts 499982 # Number of instructions executed
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system.cpu2.num_int_insts 474671 # number of integer instructions
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system.cpu2.num_int_register_reads 654261 # number of times the integer registers were read
system.cpu2.num_int_register_writes 371526 # number of times the integer registers were written
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system.cpu2.num_mem_refs 180789 # number of memory refs
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system.cpu2.num_store_insts 56349 # Number of store instructions
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-system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
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-system.cpu3.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles
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-system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_hits 56200 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses
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-system.cpu3.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
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-system.cpu3.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
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-system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.occ_blocks::0 273.505617 # Average occupied blocks per context
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-system.cpu3.dcache.overall_accesses 180770 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
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-system.cpu3.dcache.overall_hits 180307 # number of overall hits
-system.cpu3.dcache.overall_miss_latency 25588000 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
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-system.cpu3.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles
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-system.cpu3.dcache.replacements 61 # number of replacements
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-system.cpu3.dcache.tagsinuse 273.505617 # Cycle average of tags in use
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-system.cpu3.dtb.data_accesses 180788 # DTB accesses
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-system.cpu3.dtb.data_hits 180770 # DTB hits
-system.cpu3.dtb.data_misses 18 # DTB misses
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+system.cpu2.idle_fraction 0 # Percentage of idle cycles
+system.cpu2.icache.replacements 152 # number of replacements
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+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 50719.222462 # average overall miss latency
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+system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
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+system.cpu2.icache.demand_mshr_miss_latency::total 22094000 # number of demand (read+write) MSHR miss cycles
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+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47719.222462 # average overall mshr miss latency
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+system.cpu2.dcache.overall_miss_latency::total 25591000 # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data 124433 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data 180772 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data 180772 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 54919.753086 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 56093.525180 # average WriteReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 55272.138229 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 55272.138229 # average overall miss latency
+system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.dcache.fast_writes 0 # number of fast writes performed
+system.cpu2.dcache.cache_copies 0 # number of cache copies performed
+system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
+system.cpu2.dcache.writebacks::total 29 # number of writebacks
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 139 # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16822000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16822000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7380000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7380000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24202000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 24202000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24202000 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 24202000 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51919.753086 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53093.525180 # average WriteReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52272.138229 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52272.138229 # average overall mshr miss latency
+system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
-system.cpu3.dtb.read_accesses 124439 # DTB read accesses
-system.cpu3.dtb.read_acv 0 # DTB read access violations
+system.cpu3.dtb.fetch_acv 0 # ITB acv
+system.cpu3.dtb.fetch_accesses 0 # ITB accesses
system.cpu3.dtb.read_hits 124431 # DTB read hits
system.cpu3.dtb.read_misses 8 # DTB read misses
-system.cpu3.dtb.write_accesses 56349 # DTB write accesses
-system.cpu3.dtb.write_acv 0 # DTB write access violations
+system.cpu3.dtb.read_acv 0 # DTB read access violations
+system.cpu3.dtb.read_accesses 124439 # DTB read accesses
system.cpu3.dtb.write_hits 56339 # DTB write hits
system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.icache.ReadReq_accesses 499997 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_avg_miss_latency 50738.660907 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47738.660907 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_hits 499534 # number of ReadReq hits
-system.cpu3.icache.ReadReq_miss_latency 23492000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu3.icache.ReadReq_mshr_miss_latency 22103000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_refs 1078.907127 # Average number of references to valid blocks.
-system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.demand_accesses 499997 # number of demand (read+write) accesses
-system.cpu3.icache.demand_avg_miss_latency 50738.660907 # average overall miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
-system.cpu3.icache.demand_hits 499534 # number of demand (read+write) hits
-system.cpu3.icache.demand_miss_latency 23492000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_miss_latency 22103000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu3.icache.fast_writes 0 # number of fast writes performed
-system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.occ_blocks::0 216.381810 # Average occupied blocks per context
-system.cpu3.icache.occ_percent::0 0.422621 # Average percentage of cache occupancy
-system.cpu3.icache.overall_accesses 499997 # number of overall (read+write) accesses
-system.cpu3.icache.overall_avg_miss_latency 50738.660907 # average overall miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.icache.overall_hits 499534 # number of overall hits
-system.cpu3.icache.overall_miss_latency 23492000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_misses 463 # number of overall misses
-system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_miss_latency 22103000 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.icache.replacements 152 # number of replacements
-system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.icache.tagsinuse 216.381810 # Cycle average of tags in use
-system.cpu3.icache.total_refs 499534 # Total number of references to valid blocks.
-system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.writebacks 0 # number of writebacks
-system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.itb.data_accesses 0 # DTB accesses
-system.cpu3.itb.data_acv 0 # DTB access violations
-system.cpu3.itb.data_hits 0 # DTB hits
-system.cpu3.itb.data_misses 0 # DTB misses
-system.cpu3.itb.fetch_accesses 500010 # ITB accesses
-system.cpu3.itb.fetch_acv 0 # ITB acv
+system.cpu3.dtb.write_acv 0 # DTB write access violations
+system.cpu3.dtb.write_accesses 56349 # DTB write accesses
+system.cpu3.dtb.data_hits 180770 # DTB hits
+system.cpu3.dtb.data_misses 18 # DTB misses
+system.cpu3.dtb.data_acv 0 # DTB access violations
+system.cpu3.dtb.data_accesses 180788 # DTB accesses
system.cpu3.itb.fetch_hits 499997 # ITB hits
system.cpu3.itb.fetch_misses 13 # ITB misses
-system.cpu3.itb.read_accesses 0 # DTB read accesses
-system.cpu3.itb.read_acv 0 # DTB read access violations
+system.cpu3.itb.fetch_acv 0 # ITB acv
+system.cpu3.itb.fetch_accesses 500010 # ITB accesses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
-system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.write_acv 0 # DTB write access violations
+system.cpu3.itb.read_acv 0 # DTB read access violations
+system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu3.itb.write_acv 0 # DTB write access violations
+system.cpu3.itb.write_accesses 0 # DTB write accesses
+system.cpu3.itb.data_hits 0 # DTB hits
+system.cpu3.itb.data_misses 0 # DTB misses
+system.cpu3.itb.data_acv 0 # DTB access violations
+system.cpu3.itb.data_accesses 0 # DTB accesses
+system.cpu3.workload.num_syscalls 18 # Number of system calls
system.cpu3.numCycles 1457840 # number of cpu cycles simulated
-system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu3.num_busy_cycles 1457840 # Number of busy cycles
-system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls
+system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu3.committedInsts 499978 # Number of instructions committed
+system.cpu3.committedOps 499978 # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses 474667 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu3.num_fp_insts 32 # number of float instructions
-system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu3.num_func_calls 14357 # number of times a function call or return occured
-system.cpu3.num_idle_cycles 0 # Number of idle cycles
-system.cpu3.num_insts 499978 # Number of instructions executed
-system.cpu3.num_int_alu_accesses 474667 # Number of integer alu accesses
+system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls
system.cpu3.num_int_insts 474667 # number of integer instructions
+system.cpu3.num_fp_insts 32 # number of float instructions
system.cpu3.num_int_register_reads 654256 # number of times the integer registers were read
system.cpu3.num_int_register_writes 371523 # number of times the integer registers were written
-system.cpu3.num_load_insts 124438 # Number of load instructions
+system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
+system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu3.num_mem_refs 180787 # number of memory refs
+system.cpu3.num_load_insts 124438 # Number of load instructions
system.cpu3.num_store_insts 56349 # Number of store instructions
-system.cpu3.workload.num_syscalls 18 # Number of system calls
-system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 208021.582734 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 208021.582734 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 208021.582734 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 208021.582734 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 832086.330935 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40005.395683 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 28915000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 22243000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 4 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 4 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2 4 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::3 4 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 16 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 208043.175487 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 208043.175487 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2 208043.175487 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3 208043.175487 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 832172.701950 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40010.793872 # average ReadReq mshr miss latency
-system.l2c.ReadReq_hits::0 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::2 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::3 69 # number of ReadReq hits
+system.cpu3.num_idle_cycles 0 # Number of idle cycles
+system.cpu3.num_busy_cycles 1457840 # Number of busy cycles
+system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu3.idle_fraction 0 # Percentage of idle cycles
+system.cpu3.icache.replacements 152 # number of replacements
+system.cpu3.icache.tagsinuse 216.381810 # Cycle average of tags in use
+system.cpu3.icache.total_refs 499534 # Total number of references to valid blocks.
+system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu3.icache.avg_refs 1078.907127 # Average number of references to valid blocks.
+system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.icache.occ_blocks::cpu3.inst 216.381810 # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst 0.422621 # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total 0.422621 # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits::cpu3.inst 499534 # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total 499534 # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst 499534 # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total 499534 # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst 499534 # number of overall hits
+system.cpu3.icache.overall_hits::total 499534 # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
+system.cpu3.icache.overall_misses::total 463 # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23492000 # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total 23492000 # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst 23492000 # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total 23492000 # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst 23492000 # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total 23492000 # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst 499997 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total 499997 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst 499997 # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total 499997 # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst 499997 # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total 499997 # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 50738.660907 # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 50738.660907 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 50738.660907 # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes 0 # number of fast writes performed
+system.cpu3.icache.cache_copies 0 # number of cache copies performed
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22103000 # number of ReadReq MSHR miss cycles
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-system.l2c.overall_hits::1 69 # number of overall hits
-system.l2c.overall_hits::2 69 # number of overall hits
-system.l2c.overall_hits::3 69 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.overall_miss_latency 178290000 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses
-system.l2c.overall_misses::0 857 # number of overall misses
-system.l2c.overall_misses::1 857 # number of overall misses
-system.l2c.overall_misses::2 857 # number of overall misses
-system.l2c.overall_misses::3 857 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 137154000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 3.701944 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 3.701944 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 3.701944 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3 3.701944 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 14.807775 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1943.298536 # Cycle average of tags in use
-system.l2c.total_refs 332 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 0 # number of writebacks
---------- End Simulation Statistics ----------