diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
| commit | 9954eb74df98c4749651eb78098595f78d642105 (patch) | |
| tree | 74766341f05f999e2ad00626284e09dc6d0a2c58 /tests/quick/se/30.eio-mp | |
| parent | 67925a833445a8b2ddce0fae4c86677ce0f4298d (diff) | |
| download | gem5-9954eb74df98c4749651eb78098595f78d642105.tar.xz | |
stats: update stale config.ini files, eio and few other stats.
Diffstat (limited to 'tests/quick/se/30.eio-mp')
4 files changed, 539 insertions, 539 deletions
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index 8ea14a565..ee3422841 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -91,7 +91,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -102,7 +102,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -132,7 +131,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -143,7 +142,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -236,7 +234,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -247,7 +245,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] @@ -277,7 +274,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -288,7 +285,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] @@ -381,7 +377,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -392,7 +388,6 @@ size=32768 system=system tags=system.cpu2.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] @@ -422,7 +417,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -433,7 +428,6 @@ size=32768 system=system tags=system.cpu2.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] @@ -526,7 +520,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -537,7 +531,6 @@ size=32768 system=system tags=system.cpu3.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] @@ -567,7 +560,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -578,7 +571,6 @@ size=32768 system=system tags=system.cpu3.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] @@ -650,7 +642,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -661,7 +653,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 7a94e3207..8a18a4d03 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1548972 # Simulator instruction rate (inst/s) -host_op_rate 1548948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 193626740 # Simulator tick rate (ticks/s) -host_mem_usage 235568 # Number of bytes of host memory used -host_seconds 1.29 # Real time elapsed on the host +host_inst_rate 2352807 # Simulator instruction rate (inst/s) +host_op_rate 2352743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 294103962 # Simulator tick rate (ticks/s) +host_mem_usage 298060 # Number of bytes of host memory used +host_seconds 0.85 # Real time elapsed on the host sim_insts 2000004 # Number of instructions simulated sim_ops 2000004 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -854,9 +854,9 @@ system.cpu3.icache.cache_copies 0 # nu system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use -system.l2c.tags.total_refs 332 # Total number of references to valid blocks. +system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor @@ -882,19 +882,20 @@ system.l2c.tags.age_task_id_blocks_1024::0 8 # system.l2c.tags.age_task_id_blocks_1024::1 1088 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 1836 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 34048 # Number of tag accesses -system.l2c.tags.data_accesses 34048 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 276 # number of ReadReq hits +system.l2c.tags.tag_accesses 39936 # Number of tag accesses +system.l2c.tags.data_accesses 39936 # Number of data accesses system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits system.l2c.Writeback_hits::total 116 # number of Writeback hits +system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits @@ -913,20 +914,21 @@ system.l2c.overall_hits::cpu2.data 9 # nu system.l2c.overall_hits::cpu3.inst 60 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 1612 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 1260 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses @@ -945,15 +947,6 @@ system.l2c.overall_misses::cpu2.data 454 # nu system.l2c.overall_misses::cpu3.inst 403 # number of overall misses system.l2c.overall_misses::cpu3.data 454 # number of overall misses system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses) @@ -961,6 +954,16 @@ system.l2c.ReadExReq_accesses::cpu1.data 139 # nu system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1852 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1296 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses @@ -979,20 +982,21 @@ system.l2c.overall_accesses::cpu2.data 463 # nu system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.972222 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses @@ -1020,10 +1024,10 @@ system.l2c.avg_blocked_cycles::no_targets nan # a system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 2872 # Transaction distribution system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes) @@ -1039,20 +1043,22 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3428 # Request fanout histogram -system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 736 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) @@ -1063,7 +1069,7 @@ system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1074,11 +1080,11 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4556 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4556 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 098ebf393..7b3ac07e0 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -87,7 +87,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -98,7 +98,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -128,7 +127,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -139,7 +138,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -228,7 +226,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -239,7 +237,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] @@ -269,7 +266,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -280,7 +277,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] @@ -369,7 +365,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -380,7 +376,6 @@ size=32768 system=system tags=system.cpu2.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] @@ -410,7 +405,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -421,7 +416,6 @@ size=32768 system=system tags=system.cpu2.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] @@ -510,7 +504,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -521,7 +515,6 @@ size=32768 system=system tags=system.cpu3.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] @@ -551,7 +544,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -562,7 +555,6 @@ size=32768 system=system tags=system.cpu3.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] @@ -634,7 +626,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -645,7 +637,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 42278656d..640568869 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000728 # Number of seconds simulated -sim_ticks 727903500 # Number of ticks simulated -final_tick 727903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 727902500 # Number of ticks simulated +final_tick 727902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 639540 # Simulator instruction rate (inst/s) -host_op_rate 639535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232760737 # Simulator tick rate (ticks/s) -host_mem_usage 235576 # Number of bytes of host memory used -host_seconds 3.13 # Real time elapsed on the host +host_inst_rate 969116 # Simulator instruction rate (inst/s) +host_op_rate 969107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 352708611 # Simulator tick rate (ticks/s) +host_mem_usage 298060 # Number of bytes of host memory used +host_seconds 2.06 # Real time elapsed on the host sim_insts 1999978 # Number of instructions simulated sim_ops 1999978 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,29 +36,29 @@ system.physmem.num_reads::cpu2.data 454 # Nu system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 35433268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39917379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35433268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 39917379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 35433268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 39917379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 35433268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 39917379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 301402590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 35433268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35433268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 35433268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 35433268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141733073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 35433268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39917379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35433268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 39917379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 35433268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 39917379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 35433268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 39917379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 301402590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 35433317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 39917434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35433317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 39917434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 35433317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 39917434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 35433317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 39917434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 301403004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 35433317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35433317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 35433317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 35433317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141733268 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 35433317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 39917434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35433317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 39917434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 35433317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 39917434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 35433317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 39917434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301403004 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -93,7 +93,7 @@ system.cpu0.itb.data_misses 0 # DT system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.workload.num_syscalls 18 # Number of system calls -system.cpu0.numCycles 1455807 # number of cpu cycles simulated +system.cpu0.numCycles 1455805 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 500001 # Number of instructions committed @@ -112,7 +112,7 @@ system.cpu0.num_mem_refs 180793 # nu system.cpu0.num_load_insts 124443 # Number of load instructions system.cpu0.num_store_insts 56350 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 1455807 # Number of busy cycles +system.cpu0.num_busy_cycles 1455805 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.Branches 59023 # Number of branches fetched @@ -152,14 +152,14 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 500019 # Class of executed instruction system.cpu0.dcache.tags.replacements 61 # number of replacements -system.cpu0.dcache.tags.tagsinuse 273.598283 # Cycle average of tags in use +system.cpu0.dcache.tags.tagsinuse 273.597897 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.598283 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534372 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.534372 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.597897 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534371 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.534371 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id @@ -183,14 +183,14 @@ system.cpu0.dcache.demand_misses::cpu0.data 463 # system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses system.cpu0.dcache.overall_misses::total 463 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17443000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17443000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17442000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17442000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7645000 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 25088000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25088000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 25088000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25088000 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 25087000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 25087000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 25087000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 25087000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses) @@ -207,14 +207,14 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53836.419753 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 53836.419753 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53833.333333 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 53833.333333 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55000 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54185.745140 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 54185.745140 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54185.745140 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 54185.745140 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54183.585313 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 54183.585313 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54183.585313 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 54183.585313 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -233,14 +233,14 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16957000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16957000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7436500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24393500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 24393500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 17118000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 17118000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24624000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 24624000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses @@ -249,24 +249,24 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52336.419753 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53500 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52685.745140 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52685.745140 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52833.333333 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 54000 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 53183.585313 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 53183.585313 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 152 # number of replacements -system.cpu0.icache.tags.tagsinuse 216.437634 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 216.437309 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.437634 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422730 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.422730 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.437309 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422729 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.422729 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id @@ -322,24 +322,24 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22253000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22253000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22253000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22253000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22253000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22253000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22484500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22484500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22484500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22484500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22484500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22484500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48062.634989 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48062.634989 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48062.634989 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 48062.634989 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48062.634989 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 48062.634989 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48562.634989 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48562.634989 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48562.634989 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 48562.634989 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48562.634989 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 48562.634989 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -374,7 +374,7 @@ system.cpu1.itb.data_misses 0 # DT system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.workload.num_syscalls 18 # Number of system calls -system.cpu1.numCycles 1455807 # number of cpu cycles simulated +system.cpu1.numCycles 1455805 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 499997 # Number of instructions committed @@ -393,7 +393,7 @@ system.cpu1.num_mem_refs 180792 # nu system.cpu1.num_load_insts 124443 # Number of load instructions system.cpu1.num_store_insts 56349 # Number of store instructions system.cpu1.num_idle_cycles 0 # Number of idle cycles -system.cpu1.num_busy_cycles 1455807 # Number of busy cycles +system.cpu1.num_busy_cycles 1455805 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles system.cpu1.Branches 59022 # Number of branches fetched @@ -433,14 +433,14 @@ system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 500015 # Class of executed instruction system.cpu1.dcache.tags.replacements 61 # number of replacements -system.cpu1.dcache.tags.tagsinuse 273.595522 # Cycle average of tags in use +system.cpu1.dcache.tags.tagsinuse 273.595136 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.595522 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534366 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.534366 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.595136 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534365 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.534365 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id @@ -464,14 +464,14 @@ system.cpu1.dcache.demand_misses::cpu1.data 463 # system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses system.cpu1.dcache.overall_misses::total 463 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17443000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 17443000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17442000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 17442000 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7645000 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 25088000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 25088000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 25088000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 25088000 # number of overall miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 25087000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 25087000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 25087000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 25087000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses) @@ -488,14 +488,14 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53836.419753 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 53836.419753 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53833.333333 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 53833.333333 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55000 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54185.745140 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 54185.745140 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54185.745140 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 54185.745140 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54183.585313 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 54183.585313 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54183.585313 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 54183.585313 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,14 +514,14 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16957000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16957000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7436500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24393500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 24393500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 17118000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 17118000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24624000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 24624000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses @@ -530,24 +530,24 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 52336.419753 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53500 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52685.745140 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52685.745140 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 52833.333333 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54000 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 53183.585313 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 53183.585313 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 152 # number of replacements -system.cpu1.icache.tags.tagsinuse 216.435498 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 216.435172 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 499553 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 1078.948164 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.435498 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422726 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.422726 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.435172 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422725 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.422725 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id @@ -603,24 +603,24 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22258000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 22258000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22258000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 22258000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22258000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 22258000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22489500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 22489500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22489500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 22489500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22489500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 22489500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 48073.434125 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 48073.434125 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 48073.434125 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 48573.434125 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 48573.434125 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 48573.434125 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 48573.434125 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48573.434125 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 48573.434125 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses @@ -655,7 +655,7 @@ system.cpu2.itb.data_misses 0 # DT system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses system.cpu2.workload.num_syscalls 18 # Number of system calls -system.cpu2.numCycles 1455807 # number of cpu cycles simulated +system.cpu2.numCycles 1455805 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.committedInsts 499992 # Number of instructions committed @@ -674,7 +674,7 @@ system.cpu2.num_mem_refs 180792 # nu system.cpu2.num_load_insts 124443 # Number of load instructions system.cpu2.num_store_insts 56349 # Number of store instructions system.cpu2.num_idle_cycles 0 # Number of idle cycles -system.cpu2.num_busy_cycles 1455807 # Number of busy cycles +system.cpu2.num_busy_cycles 1455805 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles system.cpu2.Branches 59022 # Number of branches fetched @@ -714,14 +714,14 @@ system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 500010 # Class of executed instruction system.cpu2.dcache.tags.replacements 61 # number of replacements -system.cpu2.dcache.tags.tagsinuse 273.592761 # Cycle average of tags in use +system.cpu2.dcache.tags.tagsinuse 273.592374 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.592761 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534361 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.534361 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.592374 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534360 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.534360 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id @@ -745,14 +745,14 @@ system.cpu2.dcache.demand_misses::cpu2.data 463 # system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses system.cpu2.dcache.overall_misses::total 463 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17443000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 17443000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17442000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 17442000 # number of ReadReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7645000 # number of WriteReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 25088000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 25088000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 25088000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 25088000 # number of overall miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 25087000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 25087000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 25087000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 25087000 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses) @@ -769,14 +769,14 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53836.419753 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 53836.419753 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53833.333333 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 53833.333333 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55000 # average WriteReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54185.745140 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 54185.745140 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54185.745140 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 54185.745140 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54183.585313 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 54183.585313 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54183.585313 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 54183.585313 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -795,14 +795,14 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16957000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16957000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7436500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24393500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 24393500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 17118000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 17118000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24624000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 24624000 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses @@ -811,22 +811,22 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 52336.419753 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53500 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52685.745140 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52685.745140 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 52833.333333 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 54000 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 53183.585313 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 53183.585313 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 152 # number of replacements -system.cpu2.icache.tags.tagsinuse 216.433362 # Cycle average of tags in use +system.cpu2.icache.tags.tagsinuse 216.433036 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 499548 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.icache.tags.avg_refs 1078.937365 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.433362 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.433036 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422721 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.422721 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id @@ -884,24 +884,24 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22263000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 22263000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22263000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 22263000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22263000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 22263000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22494500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 22494500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22494500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 22494500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22494500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 22494500 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48084.233261 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 48084.233261 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 48084.233261 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48584.233261 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48584.233261 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48584.233261 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 48584.233261 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48584.233261 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 48584.233261 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dtb.fetch_hits 0 # ITB hits system.cpu3.dtb.fetch_misses 0 # ITB misses @@ -936,7 +936,7 @@ system.cpu3.itb.data_misses 0 # DT system.cpu3.itb.data_acv 0 # DTB access violations system.cpu3.itb.data_accesses 0 # DTB accesses system.cpu3.workload.num_syscalls 18 # Number of system calls -system.cpu3.numCycles 1455807 # number of cpu cycles simulated +system.cpu3.numCycles 1455805 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu3.committedInsts 499988 # Number of instructions committed @@ -955,7 +955,7 @@ system.cpu3.num_mem_refs 180790 # nu system.cpu3.num_load_insts 124441 # Number of load instructions system.cpu3.num_store_insts 56349 # Number of store instructions system.cpu3.num_idle_cycles 0 # Number of idle cycles -system.cpu3.num_busy_cycles 1455807 # Number of busy cycles +system.cpu3.num_busy_cycles 1455805 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles system.cpu3.Branches 59022 # Number of branches fetched @@ -995,12 +995,12 @@ system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 500006 # Class of executed instruction system.cpu3.dcache.tags.replacements 61 # number of replacements -system.cpu3.dcache.tags.tagsinuse 273.589931 # Cycle average of tags in use +system.cpu3.dcache.tags.tagsinuse 273.589530 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.589931 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.589530 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534355 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_percent::total 0.534355 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id @@ -1026,14 +1026,14 @@ system.cpu3.dcache.demand_misses::cpu3.data 463 # system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses system.cpu3.dcache.overall_misses::total 463 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17443500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 17443500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7645500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 7645500 # number of WriteReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 25089000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 25089000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 25089000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 25089000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17442500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 17442500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7645000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 25087500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 25087500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 25087500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 25087500 # number of overall miss cycles system.cpu3.dcache.ReadReq_accesses::cpu3.data 124433 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses) @@ -1050,14 +1050,14 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53837.962963 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 53837.962963 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55003.597122 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 55003.597122 # average WriteReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54187.904968 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 54187.904968 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54187.904968 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 54187.904968 # average overall miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53834.876543 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 53834.876543 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55000 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54184.665227 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 54184.665227 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54184.665227 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 54184.665227 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1076,14 +1076,14 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 463 system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16957500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16957500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7437000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7437000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24394500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 24394500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24394500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 24394500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 17118500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 17118500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24624500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 24624500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24624500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 24624500 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses @@ -1092,24 +1092,24 @@ system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 52337.962963 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 52337.962963 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53503.597122 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53503.597122 # average WriteReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52687.904968 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52687.904968 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52687.904968 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52687.904968 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 52834.876543 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 52834.876543 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 54000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 53184.665227 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 53184.665227 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 53184.665227 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 53184.665227 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 152 # number of replacements -system.cpu3.icache.tags.tagsinuse 216.431169 # Cycle average of tags in use +system.cpu3.icache.tags.tagsinuse 216.430826 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 499544 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.icache.tags.avg_refs 1078.928726 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.431169 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422717 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.422717 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.430826 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422716 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.422716 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id @@ -1127,12 +1127,12 @@ system.cpu3.icache.demand_misses::cpu3.inst 463 # system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses system.cpu3.icache.overall_misses::total 463 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 22962500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 22962500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 22962500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 22962500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 22962500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 22962500 # number of overall miss cycles +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 22963000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 22963000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 22963000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 22963000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 22963000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 22963000 # number of overall miss cycles system.cpu3.icache.ReadReq_accesses::cpu3.inst 500007 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_accesses::total 500007 # number of ReadReq accesses(hits+misses) system.cpu3.icache.demand_accesses::cpu3.inst 500007 # number of demand (read+write) accesses @@ -1145,12 +1145,12 @@ system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49595.032397 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 49595.032397 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49595.032397 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 49595.032397 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49595.032397 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 49595.032397 # average overall miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49596.112311 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 49596.112311 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49596.112311 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 49596.112311 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49596.112311 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 49596.112311 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1165,40 +1165,40 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22268000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 22268000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22268000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 22268000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22268000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 22268000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22500000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 22500000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22500000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 22500000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22500000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 22500000 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48095.032397 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48095.032397 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48095.032397 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 48095.032397 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48095.032397 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 48095.032397 # average overall mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48596.112311 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48596.112311 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48596.112311 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 48596.112311 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48596.112311 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 48596.112311 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 1943.831902 # Cycle average of tags in use -system.l2c.tags.total_refs 332 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 1943.822879 # Cycle average of tags in use +system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17.239792 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 265.090633 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 216.564822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 265.087863 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 216.562658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 265.085095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 216.560494 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 265.082241 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 216.558304 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 17.239740 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 265.089371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 216.563852 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 265.086602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 216.561689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 265.083834 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 216.559525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 265.080948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 216.557319 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.004045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.003305 # Average percentage of cache occupancy @@ -1208,25 +1208,26 @@ system.l2c.tags.occ_percent::cpu2.inst 0.004045 # Av system.l2c.tags.occ_percent::cpu2.data 0.003304 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.004045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.003304 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.029661 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.029660 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2904 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 34048 # Number of tag accesses -system.l2c.tags.data_accesses 34048 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 276 # number of ReadReq hits +system.l2c.tags.tag_accesses 39936 # Number of tag accesses +system.l2c.tags.data_accesses 39936 # Number of data accesses system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits system.l2c.Writeback_hits::total 116 # number of Writeback hits +system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits @@ -1245,20 +1246,21 @@ system.l2c.overall_hits::cpu2.data 9 # nu system.l2c.overall_hits::cpu3.inst 60 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 1612 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 1260 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses @@ -1277,47 +1279,39 @@ system.l2c.overall_misses::cpu2.data 454 # nu system.l2c.overall_misses::cpu3.inst 403 # number of overall misses system.l2c.overall_misses::cpu3.data 454 # number of overall misses system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 21158500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 16537500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 21164500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 16537500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 21169000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 16538500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 21172000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 16539000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 150816500 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 7297500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 7297500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 7297500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 7298000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 29190500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 21158500 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 7297500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 29190000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 21159000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 21164000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 21168500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 21172500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 84664000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 16537500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 16537500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 16537500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 16538000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 66150500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 21159000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 23835000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 21164500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 21164000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 23835000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 21169000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 23836000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 21172000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 23837000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 180007000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 21158500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu2.inst 21168500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 23835000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 21172500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 23835500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 180004500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 21159000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 23835000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 21164500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 21164000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 23835000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 21169000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 23836000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 21172000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 23837000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 180007000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu2.inst 21168500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 23835000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 21172500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 23835500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 180004500 # number of overall miss cycles system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses) @@ -1325,6 +1319,16 @@ system.l2c.ReadExReq_accesses::cpu1.data 139 # nu system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1852 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1296 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses @@ -1343,20 +1347,21 @@ system.l2c.overall_accesses::cpu2.data 463 # nu system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.972222 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses @@ -1375,38 +1380,39 @@ system.l2c.overall_miss_rate::cpu2.data 0.980562 # mi system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52502.481390 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52517.369727 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52528.535980 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52503.174603 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52535.980149 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 52504.761905 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52512.708914 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52503.597122 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52500.899281 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52502.481390 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52503.722084 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 52516.129032 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52527.295285 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 52537.220844 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 52521.091811 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 52500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 52500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 52500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 52501.587302 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 52500.396825 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52503.722084 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52517.369727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52516.129032 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 52528.535980 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 52502.202643 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 52535.980149 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52504.405286 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52510.793466 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52502.481390 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 52527.295285 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 52537.220844 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 52501.101322 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52510.064177 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52503.722084 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52517.369727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52516.129032 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 52528.535980 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 52502.202643 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 52535.980149 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52504.405286 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52510.793466 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 52527.295285 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 52537.220844 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52501.101322 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52510.064177 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1415,20 +1421,21 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_misses::cpu0.inst 403 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 315 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 403 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 315 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 403 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 315 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 403 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 315 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 2872 # number of ReadReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 139 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 139 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 139 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 139 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 556 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 403 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 403 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 403 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 403 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 1612 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 315 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 315 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 315 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 315 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 1260 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 403 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 454 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 403 # number of demand (read+write) MSHR misses @@ -1447,52 +1454,54 @@ system.l2c.overall_mshr_misses::cpu2.data 454 # n system.l2c.overall_mshr_misses::cpu3.inst 403 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 454 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 3428 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 16321500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12757500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 16328500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12757500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 16333000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 12758500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 16335500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 12758500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 116350500 # number of ReadReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5629500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5629500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5629500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5629500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 22518000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 16321500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 18387000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 16328500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 18387000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 16333000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 18388000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 16335500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 18388000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 138868500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 16321500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 18387000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 16328500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 18387000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 16333000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 18388000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 16335500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 18388000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 138868500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.912325 # mshr miss rate for ReadReq accesses +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5907500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5907500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5907500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5907500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 23630000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 17129000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 17134000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 17138500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 17142500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 68544000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 13387500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13387500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 13387500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 13388000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 53550500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 17129000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 19295000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 17134000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 19295000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 17138500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 19295000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 17142500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 19295500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 145724500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 17129000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 19295000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 17134000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 19295000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 17138500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 19295000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 17142500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 19295500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 145724500 # number of overall MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.870410 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.972222 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses @@ -1511,76 +1520,79 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40517.369727 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40528.535980 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40503.174603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40534.739454 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40503.174603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40512.012535 # average ReadReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40500 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40500 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40517.369727 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40528.535980 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40502.202643 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40534.739454 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40502.202643 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40510.064177 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40517.369727 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40528.535980 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40502.202643 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40534.739454 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40502.202643 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40510.064177 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42503.722084 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42516.129032 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42527.295285 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42537.220844 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42521.091811 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42501.587302 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500.396825 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42503.722084 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42516.129032 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42527.295285 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42537.220844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42501.101322 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42510.064177 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42503.722084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42516.129032 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42527.295285 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42537.220844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42501.101322 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42510.064177 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 2872 # Transaction distribution system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3437 # Request fanout histogram +system.membus.snoop_fanout::samples 3433 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3437 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3433 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3437 # Request fanout histogram -system.membus.reqLayer0.occupancy 3440968 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3433 # Request fanout histogram +system.membus.reqLayer0.occupancy 3438468 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) system.membus.respLayer1.occupancy 17142500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.4 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 736 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) @@ -1591,7 +1603,7 @@ system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1602,13 +1614,13 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4556 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2026000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4556 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2394000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 694500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |