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authorAndreas Hansson <andreas.hansson@arm.com>2015-03-23 06:57:31 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-03-23 06:57:31 -0400
commited08dc31babd83c5c4a439b4d189599dfeea33d1 (patch)
treef66ff8891d7ae7caf95c10272606b929c866cda9 /tests/quick/se/30.eon
parent1483496803f8a8618f62adc5439ce435359b36fe (diff)
downloadgem5-ed08dc31babd83c5c4a439b4d189599dfeea33d1.tar.xz
tests: Final reclassification of quick regressions
A few regressions were still considered long, but finished well within the 180 seconds. They are only a handful (mostly mcf in atomic). --HG-- rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/test.py => tests/quick/se/10.mcf/test.py rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/se/30.eon/test.py => tests/quick/se/30.eon/test.py
Diffstat (limited to 'tests/quick/se/30.eon')
-rw-r--r--tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini172
-rwxr-xr-xtests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr51
-rwxr-xr-xtests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout14
-rw-r--r--tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt152
-rw-r--r--tests/quick/se/30.eon/test.py33
5 files changed, 422 insertions, 0 deletions
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..44bc5cf02
--- /dev/null
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,172 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+eventq_index=0
+size=64
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=AlphaISA
+eventq_index=0
+system=system
+
+[system.cpu.itb]
+type=AlphaTLB
+eventq_index=0
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..664365742
--- /dev/null
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,51 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
+warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..e4df23735
--- /dev/null
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,14 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+OO-style eon Time= 0.183333
+Exiting @ tick 199332411500 because target called exit()
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..7803b8dd6
--- /dev/null
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,152 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.199332 # Number of seconds simulated
+sim_ticks 199332411500 # Number of ticks simulated
+final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2820224 # Simulator instruction rate (inst/s)
+host_op_rate 2820224 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1410112599 # Simulator tick rate (ticks/s)
+host_mem_usage 285836 # Number of bytes of host memory used
+host_seconds 141.36 # Real time elapsed on the host
+sim_insts 398664595 # Number of instructions simulated
+sim_ops 398664595 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory
+system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory
+system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 493419140 # Transaction distribution
+system.membus.trans_dist::ReadResp 493419140 # Transaction distribution
+system.membus.trans_dist::WriteReq 73520729 # Transaction distribution
+system.membus.trans_dist::WriteResp 73520729 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 566939869 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram
+system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 566939869 # Request fanout histogram
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 94754489 # DTB read hits
+system.cpu.dtb.read_misses 21 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 94754510 # DTB read accesses
+system.cpu.dtb.write_hits 73520729 # DTB write hits
+system.cpu.dtb.write_misses 35 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 73520764 # DTB write accesses
+system.cpu.dtb.data_hits 168275218 # DTB hits
+system.cpu.dtb.data_misses 56 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 168275274 # DTB accesses
+system.cpu.itb.fetch_hits 398664651 # ITB hits
+system.cpu.itb.fetch_misses 173 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 398664824 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.numCycles 398664824 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 398664595 # Number of instructions committed
+system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
+system.cpu.num_func_calls 16015498 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
+system.cpu.num_int_insts 316365907 # number of integer instructions
+system.cpu.num_fp_insts 155295119 # number of float instructions
+system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
+system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
+system.cpu.num_mem_refs 168275274 # number of memory refs
+system.cpu.num_load_insts 94754510 # Number of load instructions
+system.cpu.num_store_insts 73520764 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 398664824 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.Branches 44587532 # Number of branches fetched
+system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
+system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction
+system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction
+system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
+system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
+system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
+system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction
+system.cpu.op_class::MemRead 94754510 23.77% 81.56% # Class of executed instruction
+system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 398664651 # Class of executed instruction
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/30.eon/test.py b/tests/quick/se/30.eon/test.py
new file mode 100644
index 000000000..2ad1ef429
--- /dev/null
+++ b/tests/quick/se/30.eon/test.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import eon_cook
+
+workload = eon_cook(isa, opsys, 'mdred')
+root.system.cpu[0].workload = workload.makeLiveProcess()