tests: Regression stats updated for recent patches

1 files changed, 249 insertions, 63 deletions

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 5f60d059c..9b40462e7 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
@@ -194,6 +194,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -206,15 +207,16 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu0.dtb]
 type=SparcTLB
@@ -292,10 +294,10 @@ pipelined=true
 
 [system.cpu0.fuPool.FUList3]
 type=FUDesc
-children=opList0 opList1 opList2
+children=opList0 opList1 opList2 opList3 opList4
 count=2
 eventq_index=0
-opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
+opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4
 
 [system.cpu0.fuPool.FUList3.opList0]
 type=OpDesc
@@ -307,11 +309,25 @@ pipelined=true
 [system.cpu0.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu0.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu0.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
 opClass=FloatDiv
 opLat=12
 pipelined=false
 
-[system.cpu0.fuPool.FUList3.opList2]
+[system.cpu0.fuPool.FUList3.opList4]
 type=OpDesc
 eventq_index=0
 opClass=FloatSqrt
@@ -320,18 +336,25 @@ pipelined=false
 
 [system.cpu0.fuPool.FUList4]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu0.fuPool.FUList4.opList
+opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1
 
-[system.cpu0.fuPool.FUList4.opList]
+[system.cpu0.fuPool.FUList4.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemRead
 opLat=1
 pipelined=true
 
+[system.cpu0.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
 [system.cpu0.fuPool.FUList5]
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -481,24 +504,31 @@ pipelined=true
 
 [system.cpu0.fuPool.FUList6]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu0.fuPool.FUList6.opList
+opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
 
-[system.cpu0.fuPool.FUList6.opList]
+[system.cpu0.fuPool.FUList6.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu0.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu0.fuPool.FUList7]
 type=FUDesc
-children=opList0 opList1
+children=opList0 opList1 opList2 opList3
 count=4
 eventq_index=0
-opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
+opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3
 
 [system.cpu0.fuPool.FUList7.opList0]
 type=OpDesc
@@ -514,6 +544,20 @@ opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu0.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu0.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu0.fuPool.FUList8]
 type=FUDesc
 children=opList
@@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
@@ -552,6 +596,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -564,15 +609,16 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu0.interrupts]
 type=SparcInterrupts
@@ -601,7 +647,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 kvmInSE=false
@@ -738,10 +784,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
@@ -755,6 +801,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -767,15 +814,16 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu1.dtb]
 type=SparcTLB
@@ -853,10 +901,10 @@ pipelined=true
 
 [system.cpu1.fuPool.FUList3]
 type=FUDesc
-children=opList0 opList1 opList2
+children=opList0 opList1 opList2 opList3 opList4
 count=2
 eventq_index=0
-opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
+opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4
 
 [system.cpu1.fuPool.FUList3.opList0]
 type=OpDesc
@@ -868,11 +916,25 @@ pipelined=true
 [system.cpu1.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu1.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu1.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
 opClass=FloatDiv
 opLat=12
 pipelined=false
 
-[system.cpu1.fuPool.FUList3.opList2]
+[system.cpu1.fuPool.FUList3.opList4]
 type=OpDesc
 eventq_index=0
 opClass=FloatSqrt
@@ -881,18 +943,25 @@ pipelined=false
 
 [system.cpu1.fuPool.FUList4]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu1.fuPool.FUList4.opList
+opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1
 
-[system.cpu1.fuPool.FUList4.opList]
+[system.cpu1.fuPool.FUList4.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemRead
 opLat=1
 pipelined=true
 
+[system.cpu1.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
 [system.cpu1.fuPool.FUList5]
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -1042,24 +1111,31 @@ pipelined=true
 
 [system.cpu1.fuPool.FUList6]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu1.fuPool.FUList6.opList
+opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1
 
-[system.cpu1.fuPool.FUList6.opList]
+[system.cpu1.fuPool.FUList6.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu1.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu1.fuPool.FUList7]
 type=FUDesc
-children=opList0 opList1
+children=opList0 opList1 opList2 opList3
 count=4
 eventq_index=0
-opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
+opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 system.cpu1.fuPool.FUList7.opList2 system.cpu1.fuPool.FUList7.opList3
 
 [system.cpu1.fuPool.FUList7.opList0]
 type=OpDesc
@@ -1075,6 +1151,20 @@ opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu1.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu1.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu1.fuPool.FUList8]
 type=FUDesc
 children=opList
@@ -1096,10 +1186,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
@@ -1113,6 +1203,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -1125,15 +1216,16 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu1.interrupts]
 type=SparcInterrupts
@@ -1276,10 +1368,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
@@ -1293,6 +1385,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -1305,15 +1398,16 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu2.dtb]
 type=SparcTLB
@@ -1391,10 +1485,10 @@ pipelined=true
 
 [system.cpu2.fuPool.FUList3]
 type=FUDesc
-children=opList0 opList1 opList2
+children=opList0 opList1 opList2 opList3 opList4
 count=2
 eventq_index=0
-opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
+opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4
 
 [system.cpu2.fuPool.FUList3.opList0]
 type=OpDesc
@@ -1406,11 +1500,25 @@ pipelined=true
 [system.cpu2.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu2.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu2.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
 opClass=FloatDiv
 opLat=12
 pipelined=false
 
-[system.cpu2.fuPool.FUList3.opList2]
+[system.cpu2.fuPool.FUList3.opList4]
 type=OpDesc
 eventq_index=0
 opClass=FloatSqrt
@@ -1419,18 +1527,25 @@ pipelined=false
 
 [system.cpu2.fuPool.FUList4]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu2.fuPool.FUList4.opList
+opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1
 
-[system.cpu2.fuPool.FUList4.opList]
+[system.cpu2.fuPool.FUList4.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemRead
 opLat=1
 pipelined=true
 
+[system.cpu2.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
 [system.cpu2.fuPool.FUList5]
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -1580,24 +1695,31 @@ pipelined=true
 
 [system.cpu2.fuPool.FUList6]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu2.fuPool.FUList6.opList
+opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1
 
-[system.cpu2.fuPool.FUList6.opList]
+[system.cpu2.fuPool.FUList6.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu2.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu2.fuPool.FUList7]
 type=FUDesc
-children=opList0 opList1
+children=opList0 opList1 opList2 opList3
 count=4
 eventq_index=0
-opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
+opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3
 
 [system.cpu2.fuPool.FUList7.opList0]
 type=OpDesc
@@ -1613,6 +1735,20 @@ opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu2.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu2.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu2.fuPool.FUList8]
 type=FUDesc
 children=opList
@@ -1634,10 +1770,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
@@ -1651,6 +1787,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu2.icache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -1663,15 +1800,16 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu2.interrupts]
 type=SparcInterrupts
@@ -1814,10 +1952,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
@@ -1831,6 +1969,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -1843,15 +1982,16 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu3.dtb]
 type=SparcTLB
@@ -1929,10 +2069,10 @@ pipelined=true
 
 [system.cpu3.fuPool.FUList3]
 type=FUDesc
-children=opList0 opList1 opList2
+children=opList0 opList1 opList2 opList3 opList4
 count=2
 eventq_index=0
-opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
+opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4
 
 [system.cpu3.fuPool.FUList3.opList0]
 type=OpDesc
@@ -1944,11 +2084,25 @@ pipelined=true
 [system.cpu3.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu3.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu3.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
 opClass=FloatDiv
 opLat=12
 pipelined=false
 
-[system.cpu3.fuPool.FUList3.opList2]
+[system.cpu3.fuPool.FUList3.opList4]
 type=OpDesc
 eventq_index=0
 opClass=FloatSqrt
@@ -1957,18 +2111,25 @@ pipelined=false
 
 [system.cpu3.fuPool.FUList4]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu3.fuPool.FUList4.opList
+opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1
 
-[system.cpu3.fuPool.FUList4.opList]
+[system.cpu3.fuPool.FUList4.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemRead
 opLat=1
 pipelined=true
 
+[system.cpu3.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
 [system.cpu3.fuPool.FUList5]
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -2118,24 +2279,31 @@ pipelined=true
 
 [system.cpu3.fuPool.FUList6]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu3.fuPool.FUList6.opList
+opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1
 
-[system.cpu3.fuPool.FUList6.opList]
+[system.cpu3.fuPool.FUList6.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu3.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu3.fuPool.FUList7]
 type=FUDesc
-children=opList0 opList1
+children=opList0 opList1 opList2 opList3
 count=4
 eventq_index=0
-opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
+opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3
 
 [system.cpu3.fuPool.FUList7.opList0]
 type=OpDesc
@@ -2151,6 +2319,20 @@ opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu3.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu3.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu3.fuPool.FUList8]
 type=FUDesc
 children=opList
@@ -2172,10 +2354,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
@@ -2189,6 +2371,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu3.icache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -2201,15 +2384,16 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu3.interrupts]
 type=SparcInterrupts
@@ -2251,10 +2435,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=20
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
@@ -2268,6 +2452,7 @@ response_latency=20
 sequential_access=false
 size=4194304
 system=system
+tag_latency=20
 tags=system.l2c.tags
 tgts_per_mshr=12
 write_buffers=8
@@ -2280,15 +2465,16 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=20
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=20
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=4194304
+tag_latency=20
 
 [system.membus]
 type=CoherentXBar