diff options
author | Nathan Binkert <nate@binkert.org> | 2012-05-09 11:52:14 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2012-05-09 11:52:14 -0700 |
commit | 4a644767c58754339965cecc5d85853255652a30 (patch) | |
tree | e435caa3b1ba7f5e395c58ca0fdfdfa91804d2dd /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini | |
parent | 55411f7f713a42f67552a9621051fae8f7869648 (diff) | |
download | gem5-4a644767c58754339965cecc5d85853255652a30.tar.xz |
stats: update stats for no_value -> nan
Lots of accumulated older changes too.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini')
-rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini | 53 |
1 files changed, 28 insertions, 25 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index bb8df191a..5684cea4e 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[2] +system_port=system.membus.slave[1] [system.cpu0] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.port[2] +mem_side=system.toL2Bus.slave[1] [system.cpu0.dtb] type=SparcTLB @@ -419,7 +418,7 @@ opLat=3 [system.cpu0.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true @@ -440,7 +439,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.port[1] +mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=SparcInterrupts @@ -570,7 +569,7 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true @@ -591,7 +590,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.port[4] +mem_side=system.toL2Bus.slave[3] [system.cpu1.dtb] type=SparcTLB @@ -862,7 +861,7 @@ opLat=3 [system.cpu1.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true @@ -883,7 +882,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.port[3] +mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=SparcInterrupts @@ -994,7 +993,7 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true @@ -1015,7 +1014,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port -mem_side=system.toL2Bus.port[6] +mem_side=system.toL2Bus.slave[5] [system.cpu2.dtb] type=SparcTLB @@ -1286,7 +1285,7 @@ opLat=3 [system.cpu2.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true @@ -1307,7 +1306,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port -mem_side=system.toL2Bus.port[5] +mem_side=system.toL2Bus.slave[4] [system.cpu2.interrupts] type=SparcInterrupts @@ -1418,7 +1417,7 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true @@ -1439,7 +1438,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port -mem_side=system.toL2Bus.port[8] +mem_side=system.toL2Bus.slave[7] [system.cpu3.dtb] type=SparcTLB @@ -1710,7 +1709,7 @@ opLat=3 [system.cpu3.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true @@ -1731,7 +1730,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port -mem_side=system.toL2Bus.port[7] +mem_side=system.toL2Bus.slave[6] [system.cpu3.interrupts] type=SparcInterrupts @@ -1745,7 +1744,7 @@ type=ExeTracer [system.l2c] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=8 block_size=64 forward_snoops=true @@ -1765,8 +1764,8 @@ tgts_per_mshr=16 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[0] +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] [system.membus] type=Bus @@ -1776,17 +1775,20 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.l2c.mem_side system.physmem.port[0] system.system_port +master=system.physmem.port[0] +slave=system.l2c.mem_side system.system_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] [system.toL2Bus] type=Bus @@ -1796,5 +1798,6 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side |