diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 3830 |
1 files changed, 1914 insertions, 1916 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index e8e12eadf..f14e8cf51 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 110872500 # Number of ticks simulated -final_tick 110872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 110970500 # Number of ticks simulated +final_tick 110970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118027 # Simulator instruction rate (inst/s) -host_op_rate 118027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12557410 # Simulator tick rate (ticks/s) -host_mem_usage 289008 # Number of bytes of host memory used -host_seconds 8.83 # Real time elapsed on the host -sim_insts 1042088 # Number of instructions simulated -sim_ops 1042088 # Number of ops (including micro ops) simulated +host_inst_rate 128659 # Simulator instruction rate (inst/s) +host_op_rate 128659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13699808 # Simulator tick rate (ticks/s) +host_mem_usage 244656 # Number of bytes of host memory used +host_seconds 8.10 # Real time elapsed on the host +sim_insts 1042156 # Number of instructions simulated +sim_ops 1042156 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 4608 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42176 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 4608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 72 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205497305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 96976257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 5772396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7504115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 41561253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11544792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 4040677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7504115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380400911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205497305 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 5772396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 41561253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 4040677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 256871632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205497305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 96976257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5772396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7504115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 41561253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11544792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 4040677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7504115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380400911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 205315827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 96890615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 7497488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7497488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 41524549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11534597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2306919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7497488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380064972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205315827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 7497488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 41524549 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2306919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 256644784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205315827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 96890615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 7497488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7497488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 41524549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11534597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2306919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7497488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380064972 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 660 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 110844500 # Total gap between requests +system.physmem.totGap 110942500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -120,9 +120,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 400 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -217,12 +217,12 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 275.027027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.656156 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 254.302887 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45 30.41% 30.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43 29.05% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 21 14.19% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 274.594595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.768834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.591879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47 31.76% 31.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39 26.35% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 23 15.54% 73.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 12 8.11% 81.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 10 6.76% 88.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 5 3.38% 91.89% # Bytes accessed per row activation @@ -230,127 +230,127 @@ system.physmem.bytesPerActivate::768-895 5 3.38% 95.27% # By system.physmem.bytesPerActivate::896-1023 1 0.68% 95.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 6 4.05% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation -system.physmem.totQLat 5597750 # Total ticks spent queuing -system.physmem.totMemAccLat 17972750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 5904750 # Total ticks spent queuing +system.physmem.totMemAccLat 18279750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8481.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8946.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27231.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27696.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.64 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.98 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.98 # Data bus utilization in percentage -system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.97 # Data bus utilization in percentage +system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 505 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 167946.21 # Average gap between requests +system.physmem.avgGap 168094.70 # Average gap between requests system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 48028250 # Time in different power states +system.physmem.memoryStateTime::IDLE 48408000 # Time in different power states system.physmem.memoryStateTime::REF 3640000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 57613000 # Time in different power states +system.physmem.memoryStateTime::ACT 57233250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 380400911 # Throughput (bytes/s) +system.membus.throughput 380064972 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 529 # Transaction distribution system.membus.trans_dist::ReadResp 528 # Transaction distribution system.membus.trans_dist::UpgradeReq 287 # Transaction distribution system.membus.trans_dist::UpgradeResp 77 # Transaction distribution -system.membus.trans_dist::ReadExReq 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 162 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1715 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1715 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 925500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 921500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6302174 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 6294424 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 417.213115 # Cycle average of tags in use -system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 416.952741 # Cycle average of tags in use +system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.799585 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 285.091922 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.421534 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.040102 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.695019 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 55.399606 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.410902 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 3.621924 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.732522 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.799591 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 285.006820 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.406933 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 8.706163 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.731992 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 54.635838 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.407858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.562888 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.694658 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004349 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000107 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000133 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000845 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000834 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000055 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000039 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006366 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006362 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 179 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18244 # Number of tag accesses -system.l2c.tags.data_accesses 18244 # Number of data accesses +system.l2c.tags.tag_accesses 18236 # Number of tag accesses +system.l2c.tags.data_accesses 18236 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 413 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 409 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 420 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 423 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1442 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 413 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 420 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 423 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1443 # number of demand (read+write) hits +system.l2c.demand_hits::total 1442 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 229 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 413 # number of overall hits +system.l2c.overall_hits::cpu1.inst 409 # number of overall hits system.l2c.overall_hits::cpu1.data 11 # number of overall hits system.l2c.overall_hits::cpu2.inst 349 # number of overall hits system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 420 # number of overall hits +system.l2c.overall_hits::cpu3.inst 423 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1443 # number of overall hits +system.l2c.overall_hits::total 1442 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 19 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 75 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 543 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 64625 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57550.094518 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57191.871456 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10405.714286 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59643.617021 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 66041.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61288.167939 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.376623 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62680.851064 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61916.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 92076.923077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 59416.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65229.007634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61616.071429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61961.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 80287.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 64625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59653.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58787.121212 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61616.071429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61961.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 80287.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59653.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58787.121212 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 1690157613 # Throughput (bytes/s) +system.toL2Bus.throughput 1688665006 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution @@ -696,172 +696,172 @@ system.toL2Bus.trans_dist::UpgradeResp 290 # Tr system.toL2Bus.trans_dist::ReadExReq 392 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 392 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 587 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 356 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 358 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5414 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27136 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 135488 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 51904 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1624477 # Layer occupancy (ticks) +system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 135424 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1625975 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2708498 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2708248 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1467012 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1463019 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1928746 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1929745 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1148249 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1153498 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1927493 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1921995 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1209237 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1183735 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1936745 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 1936494 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1133003 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 1159999 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 82981 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80783 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 83070 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80870 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80310 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78265 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 80399 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78350 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.453617 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.451461 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 221746 # number of cpu cycles simulated +system.cpu0.numCycles 221942 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17234 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 492474 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82981 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78777 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161662 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3811 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13862 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17233 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 493008 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 83070 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78862 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161826 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3812 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13755 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingTrapStallCycles 1482 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 492 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 196720 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503426 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215057 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 491 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 196747 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.505797 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.214858 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35058 17.82% 17.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 80078 40.71% 58.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 578 0.29% 58.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76182 38.73% 98.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34921 17.75% 17.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 80152 40.74% 58.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 578 0.29% 58.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 974 0.50% 59.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 477 0.24% 59.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76267 38.76% 98.28% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::6 570 0.29% 98.57% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2455 1.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2459 1.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 196720 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.374216 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.220892 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17819 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15483 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160693 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 280 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2445 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 489648 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2445 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18474 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 866 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14003 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160341 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 591 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 486805 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 216 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 332880 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 970801 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 733282 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 319911 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12969 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 866 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 886 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3624 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155743 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78707 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75959 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75775 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 407094 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 910 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 404367 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10771 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9755 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 351 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 196720 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055546 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097437 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 196747 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.374287 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.221337 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17711 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15452 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160920 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 218 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2446 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 490118 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2446 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18323 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 441 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14289 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160585 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 663 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 487271 # Number of instructions processed by rename +system.cpu0.rename.SQFullEvents 294 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 333181 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 971741 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 733988 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 320207 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12974 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 868 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 890 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3239 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155891 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78785 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 76033 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75852 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 407472 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 912 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 404753 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 136 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10781 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9726 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 353 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 196747 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.057226 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.098946 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34036 17.30% 17.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4955 2.52% 19.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77877 39.59% 59.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77259 39.27% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1573 0.80% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 652 0.33% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34174 17.37% 17.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4673 2.38% 19.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77781 39.53% 59.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77469 39.37% 98.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1629 0.83% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 654 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 260 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 91 0.05% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 196720 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 196747 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.79% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 52 23.53% 49.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 60 26.43% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 55 24.23% 50.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 49.34% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 170970 42.28% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 171127 42.28% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued @@ -890,96 +890,96 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155279 38.40% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 78118 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155427 38.40% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 78199 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 404367 # Type of FU issued -system.cpu0.iq.rate 1.823559 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000547 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1005807 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 418829 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 402541 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 404753 # Type of FU issued +system.cpu0.iq.rate 1.823688 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 227 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1006616 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 419219 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 402934 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 404588 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 404980 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75486 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75562 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1428 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2445 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 400 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 484514 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155743 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78707 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 397 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 484968 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 314 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 155891 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78785 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 800 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 403298 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 154949 # Number of load instructions executed +system.cpu0.iew.iewExecutedInsts 403684 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 155095 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76510 # number of nop insts executed -system.cpu0.iew.exec_refs 232965 # number of memory reference insts executed -system.cpu0.iew.exec_branches 80120 # Number of branches executed -system.cpu0.iew.exec_stores 78016 # Number of stores executed -system.cpu0.iew.exec_rate 1.818739 # Inst execution rate -system.cpu0.iew.wb_sent 402871 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 402541 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238524 # num instructions producing a value -system.cpu0.iew.wb_consumers 240975 # num instructions consuming a value +system.cpu0.iew.exec_nop 76584 # number of nop insts executed +system.cpu0.iew.exec_refs 233191 # number of memory reference insts executed +system.cpu0.iew.exec_branches 80195 # Number of branches executed +system.cpu0.iew.exec_stores 78096 # Number of stores executed +system.cpu0.iew.exec_rate 1.818872 # Inst execution rate +system.cpu0.iew.wb_sent 403263 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 402934 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238926 # num instructions producing a value +system.cpu0.iew.wb_consumers 241439 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.815325 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989829 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.815492 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989592 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12269 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12279 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 194275 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430668 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136401 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 194301 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.432628 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.139595 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34469 17.74% 17.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79913 41.13% 58.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2377 1.22% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 686 0.35% 60.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75283 38.75% 99.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 305 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34596 17.81% 17.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79813 41.08% 58.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2261 1.16% 60.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 671 0.35% 60.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 526 0.27% 60.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75370 38.79% 99.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 456 0.23% 99.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 240 0.12% 99.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 368 0.19% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 194275 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 472218 # Number of instructions committed -system.cpu0.commit.committedOps 472218 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 194301 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 472662 # Number of instructions committed +system.cpu0.commit.committedOps 472662 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 230824 # Number of memory references committed -system.cpu0.commit.loads 153545 # Number of loads committed +system.cpu0.commit.refs 231046 # Number of memory references committed +system.cpu0.commit.loads 153693 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79166 # Number of branches committed +system.cpu0.commit.branches 79240 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 318242 # Number of committed integer instructions. +system.cpu0.commit.int_insts 318538 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 75898 16.07% 16.07% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 165412 35.03% 51.10% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 75972 16.07% 16.07% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 165560 35.03% 51.10% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.10% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.10% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.10% # Class of committed instruction @@ -1008,37 +1008,37 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.10% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.10% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.10% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 153629 32.53% 83.63% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77279 16.37% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 153777 32.53% 83.63% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77353 16.37% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 472218 # Class of committed instruction -system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 472662 # Class of committed instruction +system.cpu0.commit.bw_lim_events 368 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 677296 # The number of ROB reads -system.cpu0.rob.rob_writes 971436 # The number of ROB writes -system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25026 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 396236 # Number of Instructions Simulated -system.cpu0.committedOps 396236 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.559631 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559631 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.786891 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.786891 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 721496 # number of integer regfile reads -system.cpu0.int_regfile_writes 325166 # number of integer regfile writes +system.cpu0.rob.rob_reads 677713 # The number of ROB reads +system.cpu0.rob.rob_writes 972345 # The number of ROB writes +system.cpu0.timesIdled 334 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25195 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 396606 # Number of Instructions Simulated +system.cpu0.committedOps 396606 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.559603 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559603 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.786980 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.786980 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 722190 # number of integer regfile reads +system.cpu0.int_regfile_writes 325483 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 234788 # number of misc regfile reads +system.cpu0.misc_regfile_reads 235015 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.323737 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 241.252317 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.323737 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471335 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471335 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.252317 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471196 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471196 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id @@ -1058,12 +1058,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 756 # system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses system.cpu0.icache.overall_misses::total 756 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35655495 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 35655495 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 35655495 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 35655495 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 35655495 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 35655495 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35519995 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35519995 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35519995 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35519995 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35519995 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35519995 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses @@ -1076,12 +1076,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47163.353175 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 47163.353175 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 47163.353175 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 47163.353175 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46984.120370 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 46984.120370 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46984.120370 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 46984.120370 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46984.120370 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 46984.120370 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1102,510 +1102,509 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27420002 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27420002 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27420002 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27420002 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27420002 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27420002 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27366252 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27366252 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27366252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27366252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27366252 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27366252 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46632.656463 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46541.244898 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 46541.244898 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 46541.244898 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.026535 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155594 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.985956 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155741 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 915.258824 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 916.123529 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026535 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.985956 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277316 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277316 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 627036 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 627036 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 78986 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78986 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76692 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76692 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 627612 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 627612 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79059 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79059 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76768 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76768 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155678 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155678 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155678 # number of overall hits -system.cpu0.dcache.overall_hits::total 155678 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 416 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 416 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 155827 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155827 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155827 # number of overall hits +system.cpu0.dcache.overall_hits::total 155827 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 413 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 413 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 961 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 961 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 961 # number of overall misses -system.cpu0.dcache.overall_misses::total 961 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13375931 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13375931 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32683256 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32683256 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 956 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 956 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 956 # number of overall misses +system.cpu0.dcache.overall_misses::total 956 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 12955987 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 12955987 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33432506 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 33432506 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 46059187 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 46059187 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 46059187 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 46059187 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79402 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79402 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77237 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77237 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 46388493 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 46388493 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 46388493 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 46388493 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 79472 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 79472 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77311 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77311 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156639 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156639 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156639 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156639 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005239 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005239 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007056 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007056 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 156783 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156783 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156783 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156783 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005197 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005197 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007024 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007024 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006135 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006135 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006135 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006135 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32153.680288 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32153.680288 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59969.277064 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 59969.277064 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006098 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006098 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006098 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006098 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31370.428571 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31370.428571 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 61569.992634 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 61569.992634 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 47928.394381 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 47928.394381 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 512 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48523.528243 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 48523.528243 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48523.528243 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 48523.528243 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.380952 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.833333 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 228 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 598 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 598 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 598 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 226 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 368 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 368 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 594 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 594 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 363 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 363 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 363 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 363 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6192510 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6192510 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7258228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7258228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5995003 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5995003 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7531728 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7531728 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13450738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13450738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13450738 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13450738 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002368 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002368 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002266 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002266 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13526731 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13526731 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13526731 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13526731 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002353 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002353 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002264 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002264 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002317 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002317 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32938.882979 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32938.882979 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41475.588571 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41475.588571 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32058.839572 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32058.839572 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43038.445714 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43038.445714 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37366.660221 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37366.660221 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37366.660221 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37366.660221 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 49222 # Number of BP lookups -system.cpu1.branchPred.condPredicted 46474 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1275 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 43117 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 42310 # Number of BTB hits +system.cpu1.branchPred.lookups 52187 # Number of BP lookups +system.cpu1.branchPred.condPredicted 49510 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1259 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 46153 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 45385 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.128348 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 644 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.335969 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 643 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 177641 # number of cpu cycles simulated +system.cpu1.numCycles 177799 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 30689 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 271480 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 49222 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 42954 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 98036 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3712 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 35816 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 28925 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 291186 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52187 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46028 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 103264 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3653 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 32544 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7751 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 22336 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 175432 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.547494 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.089471 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 7803 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 20583 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 175643 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.657829 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.130344 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 77396 44.12% 44.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 50499 28.79% 72.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7414 4.23% 77.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3189 1.82% 78.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 704 0.40% 79.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 30975 17.66% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1193 0.68% 97.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 759 0.43% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3303 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 72379 41.21% 41.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52711 30.01% 71.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6570 3.74% 74.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3206 1.83% 76.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 681 0.39% 77.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 34861 19.85% 97.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1219 0.69% 97.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 754 0.43% 98.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3262 1.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 175432 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.277087 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.528251 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 37161 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 30981 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 90858 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 6321 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2360 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 267812 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2360 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 37844 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18525 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11702 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 84806 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 12444 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 265497 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 184374 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 502466 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 391647 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 171546 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12828 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 15168 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 73767 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 34233 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 35724 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 29188 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 218285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7630 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 221655 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10737 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10712 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 175432 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.263481 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.299438 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 175643 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.293517 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.637726 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 34549 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 28563 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 96884 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 5527 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2317 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 287488 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2317 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 35238 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 16093 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11725 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 91623 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 10844 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 285400 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RenamedOperands 199084 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 545686 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 424083 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 186368 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12716 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1090 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1211 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13408 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 80706 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38119 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 38742 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 33075 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 236041 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6768 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 238678 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10451 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 175643 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.358881 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.308073 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74808 42.64% 42.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 26276 14.98% 57.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 34476 19.65% 77.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 35104 20.01% 97.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3248 1.85% 99.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1161 0.66% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 252 0.14% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 69713 39.69% 39.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 23816 13.56% 53.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 38346 21.83% 75.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 38982 22.19% 97.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1165 0.66% 99.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 266 0.15% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 175432 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 175643 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 6.42% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 38 14.34% 20.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 79.25% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 108760 49.07% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.07% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 79356 35.80% 84.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 33539 15.13% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 115728 48.49% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.49% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 85517 35.83% 84.32% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37433 15.68% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 221655 # Type of FU issued -system.cpu1.iq.rate 1.247769 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001200 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 619107 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 236695 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 219827 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 238678 # Type of FU issued +system.cpu1.iq.rate 1.342404 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 265 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001110 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 653323 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 253430 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 236861 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 221921 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 238943 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 28930 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 32850 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2336 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1444 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1422 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2360 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 686 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 262565 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 73767 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 34233 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1056 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2317 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 666 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 282498 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 80706 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38119 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1050 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 918 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 220479 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 72759 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 907 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 237512 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 79760 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 36650 # number of nop insts executed -system.cpu1.iew.exec_refs 106217 # number of memory reference insts executed -system.cpu1.iew.exec_branches 45894 # Number of branches executed -system.cpu1.iew.exec_stores 33458 # Number of stores executed -system.cpu1.iew.exec_rate 1.241149 # Inst execution rate -system.cpu1.iew.wb_sent 220112 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 219827 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 122951 # num instructions producing a value -system.cpu1.iew.wb_consumers 127610 # num instructions consuming a value +system.cpu1.iew.exec_nop 39689 # number of nop insts executed +system.cpu1.iew.exec_refs 117113 # number of memory reference insts executed +system.cpu1.iew.exec_branches 48963 # Number of branches executed +system.cpu1.iew.exec_stores 37353 # Number of stores executed +system.cpu1.iew.exec_rate 1.335846 # Inst execution rate +system.cpu1.iew.wb_sent 237151 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 236861 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 133843 # num instructions producing a value +system.cpu1.iew.wb_consumers 138503 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.237479 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.963490 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.332184 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.966355 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12326 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1275 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 165321 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.513546 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.970448 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12124 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 6196 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1259 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 165523 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.633344 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.016153 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 73866 44.68% 44.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 44045 26.64% 71.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7953 4.81% 79.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 29501 17.84% 98.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 477 0.29% 98.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1008 0.61% 99.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 804 0.49% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 67946 41.05% 41.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 47096 28.45% 69.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6082 3.67% 73.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 7142 4.31% 77.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1575 0.95% 78.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 33355 20.15% 98.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1001 0.60% 99.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 165321 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 250221 # Number of instructions committed -system.cpu1.commit.committedOps 250221 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 165523 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 270356 # Number of instructions committed +system.cpu1.commit.committedOps 270356 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 104162 # Number of memory references committed -system.cpu1.commit.loads 71373 # Number of loads committed -system.cpu1.commit.membars 6322 # Number of memory barriers committed -system.cpu1.commit.branches 45072 # Number of branches committed +system.cpu1.commit.refs 115067 # Number of memory references committed +system.cpu1.commit.loads 78370 # Number of loads committed +system.cpu1.commit.membars 5484 # Number of memory barriers committed +system.cpu1.commit.branches 48146 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 171353 # Number of committed integer instructions. +system.cpu1.commit.int_insts 185335 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 35859 14.33% 14.33% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 103878 41.51% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.85% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 77695 31.05% 86.90% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 32789 13.10% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 38938 14.40% 14.40% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 110867 41.01% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 83854 31.02% 86.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 36697 13.57% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 250221 # Class of committed instruction -system.cpu1.commit.bw_lim_events 804 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 270356 # Class of committed instruction +system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 426477 # The number of ROB reads -system.cpu1.rob.rob_writes 527460 # The number of ROB writes -system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2209 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 44103 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 208040 # Number of Instructions Simulated -system.cpu1.committedOps 208040 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.853879 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.853879 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.171126 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.171126 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 377205 # number of integer regfile reads -system.cpu1.int_regfile_writes 176304 # number of integer regfile writes +system.cpu1.rob.rob_reads 446600 # The number of ROB reads +system.cpu1.rob.rob_writes 567283 # The number of ROB writes +system.cpu1.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 44141 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 225934 # Number of Instructions Simulated +system.cpu1.committedOps 225934 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.786951 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.786951 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.270727 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.270727 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 409872 # number of integer regfile reads +system.cpu1.int_regfile_writes 191136 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 107775 # number of misc regfile reads +system.cpu1.misc_regfile_reads 118682 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.769709 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21861 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 79.885573 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20107 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 51.077103 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 46.978972 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.769709 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149941 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149941 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.885573 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156027 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.156027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22764 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22764 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21861 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21861 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21861 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21861 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21861 # number of overall hits -system.cpu1.icache.overall_hits::total 21861 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 475 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 475 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 475 # number of overall misses -system.cpu1.icache.overall_misses::total 475 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7146245 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7146245 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7146245 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7146245 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7146245 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7146245 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 22336 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 22336 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22336 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22336 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22336 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22336 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021266 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.021266 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021266 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.021266 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021266 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.021266 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15044.726316 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15044.726316 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15044.726316 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15044.726316 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21011 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21011 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20107 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20107 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20107 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20107 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20107 # number of overall hits +system.cpu1.icache.overall_hits::total 20107 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses +system.cpu1.icache.overall_misses::total 476 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7353244 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7353244 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7353244 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7353244 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7353244 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7353244 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20583 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20583 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20583 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20583 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20583 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20583 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023126 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023126 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023126 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023126 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023126 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023126 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15447.991597 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15447.991597 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15447.991597 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15447.991597 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15447.991597 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15447.991597 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1614,111 +1613,111 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 47 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 47 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 47 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5694254 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5694254 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5694254 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5694254 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5694254 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5694254 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019162 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019162 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019162 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13304.331776 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5927255 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5927255 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5927255 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5927255 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5927255 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5927255 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020794 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.020794 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.020794 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13848.726636 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13848.726636 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13848.726636 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 23.645460 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 38791 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 24.706566 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 42694 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1385.392857 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1524.785714 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.645460 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046183 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.046183 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.706566 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048255 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 306653 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 306653 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 43477 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 43477 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 32586 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 32586 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 76063 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 76063 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 76063 # number of overall hits -system.cpu1.dcache.overall_hits::total 76063 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 336 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 336 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 57 # 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number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 76531 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007669 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.007669 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004034 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004034 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006115 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006115 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006115 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006115 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12433.437500 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12433.437500 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9149.245614 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9149.245614 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14832.042735 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14832.042735 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 334614 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 334614 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 46543 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 46543 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 36491 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 36491 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 83034 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 83034 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 83034 # number of overall hits +system.cpu1.dcache.overall_hits::total 83034 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 352 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 352 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 492 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 492 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 492 # number of overall misses +system.cpu1.dcache.overall_misses::total 492 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4522597 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4522597 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3033762 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3033762 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 535508 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 535508 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7556359 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7556359 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7556359 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7556359 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 46895 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 46895 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 36631 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 36631 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 83526 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 83526 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 83526 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 83526 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007506 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.007506 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003822 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003822 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.818182 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005890 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005890 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005890 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005890 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12848.286932 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12848.286932 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21669.728571 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21669.728571 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9916.814815 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9916.814815 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15358.453252 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15358.453252 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15358.453252 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15358.453252 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1727,404 +1726,404 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 178 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 30 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 30 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 208 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 208 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 208 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1076519 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1076519 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1313739 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1313739 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 407493 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 407493 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2390258 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2390258 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2390258 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2390258 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003606 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003606 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003118 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003118 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003397 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003397 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6813.411392 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6813.411392 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7149 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7149 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 195 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 227 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 227 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 157 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1099522 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1099522 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1387488 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1387488 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 427492 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 427492 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2487010 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2487010 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2487010 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2487010 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003348 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003348 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002948 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002948 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.818182 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.818182 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003173 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003173 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003173 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003173 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7003.324841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7003.324841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12847.111111 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12847.111111 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7916.518519 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7916.518519 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9384.943396 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9384.943396 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9384.943396 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9384.943396 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 47728 # Number of BP lookups -system.cpu2.branchPred.condPredicted 45021 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1300 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 41568 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 40861 # Number of BTB hits +system.cpu2.branchPred.lookups 51191 # Number of BP lookups +system.cpu2.branchPred.condPredicted 48468 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 44993 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 44297 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.299172 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 682 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.453093 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 177276 # number of cpu cycles simulated +system.cpu2.numCycles 177434 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 30843 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 263204 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 47728 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 41543 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 94904 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3824 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 35041 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 28865 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 285908 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51191 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 44981 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 100768 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3816 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 31184 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 807 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 21784 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 171794 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.532091 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.088011 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 7805 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1366 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 19788 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 172424 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.658168 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.138146 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 76890 44.76% 44.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 48833 28.43% 73.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 7151 4.16% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3183 1.85% 79.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 686 0.40% 79.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 29845 17.37% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1160 0.68% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 777 0.45% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3269 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 71656 41.56% 41.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51257 29.73% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6128 3.55% 74.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3186 1.85% 76.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 695 0.40% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 34284 19.88% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1167 0.68% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 773 0.45% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3278 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 171794 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.269230 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.484713 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 36742 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 30806 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 88081 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5970 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2446 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 259729 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2446 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 37466 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 17718 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12322 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 82351 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 11742 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 257457 # Number of instructions processed by rename -system.cpu2.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 179534 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 487570 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 380512 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 166403 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13131 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1114 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1238 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 14439 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 71183 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 33053 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 34319 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 28008 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 212034 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 7370 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 214866 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11214 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11199 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 171794 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.250719 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.303691 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 172424 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288507 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.611348 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 34386 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 27902 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 94859 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5040 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2432 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 282267 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2432 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 35111 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14773 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12374 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90050 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 9879 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280008 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu2.rename.RenamedOperands 196247 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 536665 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 417354 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 183125 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13122 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1115 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12503 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79020 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37489 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 37725 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 32426 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 232155 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6357 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 234096 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11107 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11056 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 607 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 172424 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.357676 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.313193 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 74486 43.36% 43.36% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 25336 14.75% 58.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 33280 19.37% 77.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 33902 19.73% 97.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3243 1.89% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1160 0.68% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 274 0.16% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 69134 40.10% 40.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22467 13.03% 53.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37714 21.87% 75.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38330 22.23% 97.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3239 1.88% 99.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1151 0.67% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 171794 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172424 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 17 6.18% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 48 17.45% 23.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 76.36% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 12 4.40% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 51 18.68% 23.08% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 76.92% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 106150 49.40% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 76361 35.54% 84.94% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 32355 15.06% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114033 48.71% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83276 35.57% 84.29% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 36787 15.71% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 214866 # Type of FU issued -system.cpu2.iq.rate 1.212042 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 275 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001280 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 601907 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 230666 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 213047 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 234096 # Type of FU issued +system.cpu2.iq.rate 1.319341 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 273 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001166 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 640996 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 249665 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 232273 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 215141 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 234369 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 27720 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 32149 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2543 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2502 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 48 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1485 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 916 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 254607 # Number of instructions dispatched to IQ +system.cpu2.iew.iewSquashCycles 2432 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 787 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277138 # Number of instructions dispatched to IQ system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 71183 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 33053 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1074 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewDispLoadInsts 79020 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37489 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1072 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 48 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 458 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 967 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1425 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 213716 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 70082 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1150 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 971 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1435 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 232944 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 77967 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1152 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 35203 # number of nop insts executed -system.cpu2.iew.exec_refs 102354 # number of memory reference insts executed -system.cpu2.iew.exec_branches 44387 # Number of branches executed -system.cpu2.iew.exec_stores 32272 # Number of stores executed -system.cpu2.iew.exec_rate 1.205555 # Inst execution rate -system.cpu2.iew.wb_sent 213334 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 213047 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 119124 # num instructions producing a value -system.cpu2.iew.wb_consumers 123829 # num instructions consuming a value +system.cpu2.iew.exec_nop 38626 # number of nop insts executed +system.cpu2.iew.exec_refs 114664 # number of memory reference insts executed +system.cpu2.iew.exec_branches 47841 # Number of branches executed +system.cpu2.iew.exec_stores 36697 # Number of stores executed +system.cpu2.iew.exec_rate 1.312849 # Inst execution rate +system.cpu2.iew.wb_sent 232563 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 232273 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131430 # num instructions producing a value +system.cpu2.iew.wb_consumers 136123 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.201781 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.962004 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.309067 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965524 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12897 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 6722 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1300 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 161599 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.495727 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.966465 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12771 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5750 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 162187 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.630001 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.017893 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 73205 45.30% 45.30% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 42525 26.32% 71.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6095 3.77% 75.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1558 0.96% 81.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 28296 17.51% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 469 0.29% 98.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 66847 41.22% 41.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46010 28.37% 69.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6109 3.77% 73.35% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6666 4.11% 77.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1557 0.96% 78.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 32708 20.17% 98.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 471 0.29% 98.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1007 0.62% 99.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 161599 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 241708 # Number of instructions committed -system.cpu2.commit.committedOps 241708 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 162187 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 264365 # Number of instructions committed +system.cpu2.commit.committedOps 264365 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 100224 # Number of memory references committed -system.cpu2.commit.loads 68640 # Number of loads committed -system.cpu2.commit.membars 6003 # Number of memory barriers committed -system.cpu2.commit.branches 43548 # Number of branches committed +system.cpu2.commit.refs 112522 # Number of memory references committed +system.cpu2.commit.loads 76518 # Number of loads committed +system.cpu2.commit.membars 5033 # Number of memory barriers committed +system.cpu2.commit.branches 47000 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 165890 # Number of committed integer instructions. +system.cpu2.commit.int_insts 181641 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 34333 14.20% 14.20% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 101148 41.85% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 74643 30.88% 86.93% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 31584 13.07% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 37787 14.29% 14.29% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 109023 41.24% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 81551 30.85% 86.38% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 36004 13.62% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 241708 # Class of committed instruction -system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 264365 # Class of committed instruction +system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 414795 # The number of ROB reads -system.cpu2.rob.rob_writes 511661 # The number of ROB writes -system.cpu2.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5482 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44468 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 201372 # Number of Instructions Simulated -system.cpu2.committedOps 201372 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.880341 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.880341 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.135924 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.135924 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 365782 # number of integer regfile reads -system.cpu2.int_regfile_writes 171355 # number of integer regfile writes +system.cpu2.rob.rob_reads 437924 # The number of ROB reads +system.cpu2.rob.rob_writes 556709 # The number of ROB writes +system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5010 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44506 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 221545 # Number of Instructions Simulated +system.cpu2.committedOps 221545 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.800894 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.800894 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.248605 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.248605 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 402715 # number of integer regfile reads +system.cpu2.int_regfile_writes 188101 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 103916 # number of misc regfile reads +system.cpu2.misc_regfile_reads 116228 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.236907 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 21297 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 50.110588 # Average number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 81.450670 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19300 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 424 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.518868 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236907 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160619 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.160619 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id +system.cpu2.icache.tags.occ_blocks::cpu2.inst 81.450670 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.159083 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.159083 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 107 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.210938 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 22209 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 22209 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 21297 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 21297 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 21297 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 21297 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 21297 # number of overall hits -system.cpu2.icache.overall_hits::total 21297 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 487 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 487 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 487 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 487 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 487 # number of overall misses -system.cpu2.icache.overall_misses::total 487 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521239 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11521239 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11521239 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11521239 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11521239 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11521239 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 21784 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 21784 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 21784 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 21784 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 21784 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 21784 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.022356 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.022356 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.022356 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.022356 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.022356 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.022356 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23657.574949 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23657.574949 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23657.574949 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23657.574949 # average overall miss latency +system.cpu2.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.208984 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 20212 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 20212 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 19300 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19300 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19300 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19300 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19300 # number of overall hits +system.cpu2.icache.overall_hits::total 19300 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 488 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 488 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 488 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 488 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 488 # number of overall misses +system.cpu2.icache.overall_misses::total 488 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11534741 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11534741 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11534741 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11534741 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11534741 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11534741 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19788 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19788 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19788 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19788 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19788 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19788 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024661 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024661 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024661 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024661 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024661 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024661 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23636.764344 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23636.764344 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23636.764344 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23636.764344 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23636.764344 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23636.764344 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -2133,112 +2132,111 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 62 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 62 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 62 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9226007 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 9226007 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9226007 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 9226007 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9226007 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 9226007 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019510 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.019510 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.019510 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21708.251765 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 64 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 64 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 64 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 64 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 424 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 424 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 424 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 424 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 424 # 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number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1527990 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1527990 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456495 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456495 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3043268 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3043268 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3043268 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3043268 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003897 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003897 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003364 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003364 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.808219 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.808219 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003669 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003669 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9183.503030 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9183.503030 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14415 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14415 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7737.203390 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7737.203390 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1467781 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1467781 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1796490 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1796490 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 444994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 444994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3264271 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3264271 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3264271 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3264271 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003515 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003515 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002950 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002950 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003267 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003267 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003267 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003267 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9116.652174 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9116.652174 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16948.018868 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16948.018868 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7672.310345 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7672.310345 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12225.734082 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12225.734082 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12225.734082 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12225.734082 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 53964 # Number of BP lookups -system.cpu3.branchPred.condPredicted 51232 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1265 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 47874 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 47117 # Number of BTB hits +system.cpu3.branchPred.lookups 47572 # Number of BP lookups +system.cpu3.branchPred.condPredicted 44838 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1269 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 41556 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 40675 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.418766 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.879969 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 650 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 176930 # number of cpu cycles simulated +system.cpu3.numCycles 177088 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 27837 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 302665 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 53964 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 47762 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 106222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3643 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 30631 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 31611 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 260615 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 47572 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 41325 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 95272 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3721 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 37783 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 19577 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 175543 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.724164 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.153360 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 7803 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23344 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 175638 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.483819 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.061741 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 69321 39.49% 39.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 53950 30.73% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6031 3.44% 73.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3206 1.83% 75.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 696 0.40% 75.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 37091 21.13% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1217 0.69% 97.70% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 754 0.43% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3277 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 80366 45.76% 45.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 49379 28.11% 73.87% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7947 4.52% 78.40% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3182 1.81% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 669 0.38% 80.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 28809 16.40% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1228 0.70% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 757 0.43% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3301 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 175543 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.305002 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.710648 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 32973 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 27130 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 100348 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5043 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2300 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 299109 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2300 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 33648 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14616 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11766 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 95589 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 9875 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 296992 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 207702 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 570845 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 442935 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 195079 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12623 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1224 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 12490 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 84722 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 40383 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 40455 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 35338 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 246413 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6255 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 248738 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 58 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10413 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 9948 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 566 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 175543 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.416963 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.309147 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 175638 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.268635 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.471669 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 38601 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 32457 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 87595 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 6808 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2374 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 256826 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2374 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 39299 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 20012 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11695 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 81034 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 13421 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 254587 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu3.rename.RenamedOperands 176229 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 478476 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 373673 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 163264 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12965 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1216 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 16061 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 69948 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 32037 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 34088 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 26994 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 208399 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8161 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 212159 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10835 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11026 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 608 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 175638 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.207933 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.292111 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 66501 37.88% 37.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 22275 12.69% 50.57% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 40683 23.18% 73.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 41300 23.53% 97.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 77942 44.38% 44.38% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 27771 15.81% 60.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 32234 18.35% 78.54% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 32910 18.74% 97.28% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::4 3253 1.85% 99.13% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1166 0.66% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 47 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1156 0.66% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 263 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 175543 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 175638 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 17 6.44% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 37 14.02% 20.45% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 12 4.44% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 48 17.78% 22.22% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 77.78% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 119912 48.21% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.21% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 89101 35.82% 84.03% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 39725 15.97% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 104799 49.40% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 76027 35.83% 85.23% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31333 14.77% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 248738 # Type of FU issued -system.cpu3.iq.rate 1.405855 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 264 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001061 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 673341 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 263119 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 246940 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 212159 # Type of FU issued +system.cpu3.iq.rate 1.198043 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 270 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001273 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 600350 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 227441 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 210302 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 249002 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 212429 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 35155 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26730 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2247 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2459 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2300 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 643 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 294126 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 84722 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 40383 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1060 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2374 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 705 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 251552 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 69948 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 32037 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1046 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1378 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 247584 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 83851 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 910 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1374 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 210966 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 68906 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1193 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 41458 # number of nop insts executed -system.cpu3.iew.exec_refs 123507 # number of memory reference insts executed -system.cpu3.iew.exec_branches 50799 # Number of branches executed -system.cpu3.iew.exec_stores 39656 # Number of stores executed -system.cpu3.iew.exec_rate 1.399333 # Inst execution rate -system.cpu3.iew.wb_sent 247229 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 246940 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 140247 # num instructions producing a value -system.cpu3.iew.wb_consumers 144914 # num instructions consuming a value +system.cpu3.iew.exec_nop 34992 # number of nop insts executed +system.cpu3.iew.exec_refs 100151 # number of memory reference insts executed +system.cpu3.iew.exec_branches 44184 # Number of branches executed +system.cpu3.iew.exec_stores 31245 # Number of stores executed +system.cpu3.iew.exec_rate 1.191306 # Inst execution rate +system.cpu3.iew.wb_sent 210604 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 210302 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 116846 # num instructions producing a value +system.cpu3.iew.wb_consumers 121503 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.395693 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.967795 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.187556 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.961672 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 11951 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5689 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1265 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165494 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.704926 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.039126 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12453 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7553 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1269 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165461 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.444927 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.940782 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 64312 38.86% 38.86% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48901 29.55% 68.41% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.09% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6636 4.01% 76.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 35663 21.55% 98.60% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 504 0.30% 98.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 999 0.60% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 818 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 77418 46.79% 46.79% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 42307 25.57% 72.36% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6087 3.68% 76.04% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8486 5.13% 81.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1577 0.95% 82.12% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 27301 16.50% 98.62% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 474 0.29% 98.91% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1005 0.61% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165494 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 282155 # Number of instructions committed -system.cpu3.commit.committedOps 282155 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165461 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 239079 # Number of instructions committed +system.cpu3.commit.committedOps 239079 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 121473 # Number of memory references committed -system.cpu3.commit.loads 82475 # Number of loads committed -system.cpu3.commit.membars 4979 # Number of memory barriers committed -system.cpu3.commit.branches 49942 # Number of branches committed +system.cpu3.commit.refs 98079 # Number of memory references committed +system.cpu3.commit.loads 67489 # Number of loads committed +system.cpu3.commit.membars 6836 # Number of memory barriers committed +system.cpu3.commit.branches 43385 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 193540 # Number of committed integer instructions. +system.cpu3.commit.int_insts 163585 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 40736 14.44% 14.44% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 114967 40.75% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.18% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 87454 31.00% 86.18% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 38998 13.82% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 34172 14.29% 14.29% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 99992 41.82% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.12% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 74325 31.09% 87.21% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30590 12.79% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 282155 # Class of committed instruction -system.cpu3.commit.bw_lim_events 818 # number cycles where commit BW limit reached +system.cpu3.commit.op_class_0::total 239079 # Class of committed instruction +system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 458195 # The number of ROB reads -system.cpu3.rob.rob_writes 590518 # The number of ROB writes -system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1387 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 236440 # Number of Instructions Simulated -system.cpu3.committedOps 236440 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.748308 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.748308 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.336348 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.336348 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 429141 # number of integer regfile reads -system.cpu3.int_regfile_writes 199912 # number of integer regfile writes +system.cpu3.rob.rob_reads 415600 # The number of ROB reads +system.cpu3.rob.rob_writes 505444 # The number of ROB writes +system.cpu3.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1450 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 198071 # Number of Instructions Simulated +system.cpu3.committedOps 198071 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.894063 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.894063 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.118489 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.118489 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 358875 # number of integer regfile reads +system.cpu3.int_regfile_writes 168004 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 125101 # number of misc regfile reads +system.cpu3.misc_regfile_reads 101700 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 80.524551 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 19102 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 77.082229 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 22869 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 44.423256 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 53.183721 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.524551 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157275 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.157275 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.082229 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.150551 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.150551 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 20007 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 20007 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 19102 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 19102 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 19102 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 19102 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 19102 # number of overall hits -system.cpu3.icache.overall_hits::total 19102 # number of overall hits +system.cpu3.icache.tags.tag_accesses 23774 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 23774 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 22869 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 22869 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 22869 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 22869 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 22869 # number of overall hits +system.cpu3.icache.overall_hits::total 22869 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6525745 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6525745 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6525745 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6525745 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6525745 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6525745 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 19577 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 19577 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 19577 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 19577 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 19577 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 19577 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024263 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.024263 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024263 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.024263 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024263 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.024263 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13738.410526 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13738.410526 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6365994 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6365994 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6365994 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6365994 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6365994 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6365994 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 23344 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 23344 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 23344 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 23344 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 23344 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 23344 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020348 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.020348 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020348 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.020348 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020348 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.020348 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13402.092632 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13402.092632 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13402.092632 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13402.092632 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13402.092632 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13402.092632 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2666,99 +2663,100 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5298255 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5298255 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5298255 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5298255 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5298255 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5298255 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021965 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.021965 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.021965 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5107006 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5107006 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5107006 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5107006 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5107006 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5107006 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018420 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.018420 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018420 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.018420 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018420 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.018420 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11876.758140 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11876.758140 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11876.758140 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11876.758140 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11876.758140 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11876.758140 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.706550 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 44992 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1606.857143 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 23.636588 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 36715 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1266.034483 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.706550 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048255 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.636588 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046165 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.046165 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 350946 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 350946 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 48327 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 48327 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 38795 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 38795 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 87122 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 87122 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 87122 # number of overall hits -system.cpu3.dcache.overall_hits::total 87122 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 351 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 351 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 490 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses -system.cpu3.dcache.overall_misses::total 490 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4621144 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4621144 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3311512 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3311512 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 513008 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 513008 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7932656 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7932656 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7932656 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7932656 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 48678 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 48678 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 38934 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 38934 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 87612 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 87612 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 87612 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 87612 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007211 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.007211 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003570 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003570 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005593 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005593 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005593 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005593 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13165.652422 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 13165.652422 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23823.827338 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 23823.827338 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9865.538462 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 9865.538462 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 16189.093878 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 16189.093878 # average overall miss latency +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 291244 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 291244 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41825 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41825 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 30388 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 30388 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 72213 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 72213 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 72213 # number of overall hits +system.cpu3.dcache.overall_hits::total 72213 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 334 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 334 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 465 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 465 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 465 # number of overall misses +system.cpu3.dcache.overall_misses::total 465 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4213650 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4213650 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2829011 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2829011 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 511006 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 511006 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7042661 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7042661 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7042661 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7042661 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 42159 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 42159 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 30519 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 30519 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 72678 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 72678 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 72678 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 72678 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007922 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.007922 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004292 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004292 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.788732 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006398 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.006398 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006398 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.006398 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12615.718563 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12615.718563 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21595.503817 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 21595.503817 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9125.107143 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9125.107143 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15145.507527 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 15145.507527 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15145.507527 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 15145.507527 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2767,54 +2765,54 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 197 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 230 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 230 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 230 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 230 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 154 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1052517 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1052517 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1403488 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1403488 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 408992 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 408992 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2456005 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2456005 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2456005 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2456005 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003164 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002723 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002723 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.812500 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.812500 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002968 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002968 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6834.525974 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6834.525974 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13240.452830 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13240.452830 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7865.230769 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7865.230769 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 173 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 204 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 204 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 261 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 261 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1077518 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1077518 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1290489 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1290489 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 398994 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 398994 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2368007 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2368007 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2368007 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2368007 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003819 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003819 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003277 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.788732 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003591 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003591 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6692.658385 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6692.658385 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12904.890000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12904.890000 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7124.892857 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7124.892857 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9072.823755 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9072.823755 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9072.823755 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9072.823755 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |