diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 4775 |
1 files changed, 2390 insertions, 2385 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 994a2ff39..ffbae61d5 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105696000 # Number of ticks simulated -final_tick 105696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 105542000 # Number of ticks simulated +final_tick 105542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145069 # Simulator instruction rate (inst/s) -host_op_rate 145069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15443503 # Simulator tick rate (ticks/s) -host_mem_usage 252160 # Number of bytes of host memory used -host_seconds 6.84 # Real time elapsed on the host -sim_insts 992854 # Number of instructions simulated -sim_ops 992854 # Number of ops (including micro ops) simulated +host_inst_rate 163449 # Simulator instruction rate (inst/s) +host_op_rate 163449 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17392605 # Simulator tick rate (ticks/s) +host_mem_usage 309188 # Number of bytes of host memory used +host_seconds 6.07 # Real time elapsed on the host +sim_insts 991839 # Number of instructions simulated +sim_ops 991839 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 22976 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 4800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 4864 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 4800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 4864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 75 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 76 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 668 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 218589161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101725704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8477142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7871632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 45413261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 12110203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2422041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7871632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 404480775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 218589161 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8477142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 45413261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2422041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 274901605 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 218589161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101725704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8477142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7871632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 45413261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 12110203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2422041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7871632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 404480775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 669 # Number of read requests accepted +system.physmem.num_reads::total 664 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 217695325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101874135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 7276724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7883118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 46085918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 12127873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1819181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7883118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 402645392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 217695325 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 7276724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 46085918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1819181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 272877148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 217695325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101874135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 7276724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7883118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 46085918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 12127873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1819181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7883118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 402645392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 665 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 669 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 665 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42816 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 42560 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42816 # Total read bytes from the system interface side +system.physmem.bytesReadSys 42560 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 30 # Per bank write bursts +system.physmem.perBankRdBursts::2 27 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts system.physmem.perBankRdBursts::4 65 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts @@ -81,7 +81,7 @@ system.physmem.perBankRdBursts::6 18 # Pe system.physmem.perBankRdBursts::7 24 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::10 22 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts system.physmem.perBankRdBursts::12 65 # Per bank write bursts system.physmem.perBankRdBursts::13 38 # Per bank write bursts @@ -105,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 105668000 # Total gap between requests +system.physmem.totGap 105514000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 669 # Read request sizes (log2) +system.physmem.readPktSize::6 665 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -120,10 +120,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -216,812 +216,319 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.167832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.166692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.214493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42 29.37% 29.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 27.27% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24 16.78% 73.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 13 9.09% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 4.20% 86.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 4.20% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 4.20% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.40% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 143 # Bytes accessed per row activation -system.physmem.totQLat 6392250 # Total ticks spent queuing -system.physmem.totMemAccLat 18936000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9554.93 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.338028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.767584 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.989000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41 28.87% 28.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38 26.76% 55.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 26 18.31% 73.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 8.45% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 4.23% 86.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 4.23% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 4.23% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.41% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 3.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142 # Bytes accessed per row activation +system.physmem.totQLat 6421750 # Total ticks spent queuing +system.physmem.totMemAccLat 18890500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9656.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28304.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 405.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28406.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 403.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 405.09 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 403.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.15 # Data bus utilization in percentage +system.physmem.busUtilRead 3.15 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 515 # Number of row buffer hits during reads +system.physmem.readRowHits 512 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 157949.18 # Average gap between requests -system.physmem.pageHitRate 76.98 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 46119750 # Time in different power states -system.physmem.memoryStateTime::REF 3380000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 52590250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 695520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 355320 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 379500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 193875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2776800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2051400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 36176760 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 31269060 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29154750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 33459750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 75794610 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 73940685 # Total energy per rank (pJ) -system.physmem.averagePower::0 746.882897 # Core power per rank (mW) -system.physmem.averagePower::1 728.614251 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 538 # Transaction distribution -system.membus.trans_dist::ReadResp 537 # Transaction distribution -system.membus.trans_dist::UpgradeReq 276 # Transaction distribution -system.membus.trans_dist::UpgradeResp 78 # Transaction distribution -system.membus.trans_dist::ReadExReq 177 # Transaction distribution -system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1737 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 244 # Total snoops (count) -system.membus.snoop_fanout::samples 991 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 991 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 991 # Request fanout histogram -system.membus.reqLayer0.occupancy 940500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 6384422 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 424.241443 # Cycle average of tags in use -system.l2c.tags.total_refs 1667 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 535 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.115888 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.793516 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 289.763968 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.233930 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 9.364536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.722908 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 57.054480 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.356180 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.266531 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.685395 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004421 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000871 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006473 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 535 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008163 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 20109 # Number of tag accesses -system.l2c.tags.data_accesses 20109 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 250 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 480 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1667 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 480 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 413 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1667 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 250 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 480 # number of overall hits -system.l2c.overall_hits::cpu1.data 11 # number of overall hits -system.l2c.overall_hits::cpu2.inst 413 # number of overall hits -system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 492 # number of overall hits -system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1667 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 17 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 80 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 550 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 17 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 80 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 681 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 363 # number of overall misses -system.l2c.overall_misses::cpu0.data 168 # number of overall misses -system.l2c.overall_misses::cpu1.inst 17 # number of overall misses -system.l2c.overall_misses::cpu1.data 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 80 # number of overall misses -system.l2c.overall_misses::cpu2.data 20 # number of overall misses -system.l2c.overall_misses::cpu3.inst 7 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 681 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 25064250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5642000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1337250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5652250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 765250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 39069000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6921000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 852750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 837000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9658000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 25064250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12563000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1337250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 927750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5652250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1812500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 458000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 912000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 48727000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 25064250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12563000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1337250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 927750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5652250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1812500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 912000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 48727000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 613 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 493 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 499 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2217 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 613 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 493 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 499 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2348 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 613 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 493 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 499 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2348 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.592170 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.034205 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.162272 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.014028 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.248083 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.962963 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.592170 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.034205 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.162272 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.014028 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.290034 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.592170 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.034205 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.162272 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.014028 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.290034 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69047.520661 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 76243.243243 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78661.764706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70653.125000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 109321.428571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65428.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 71034.545455 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73627.659574 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71062.500000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80557.692308 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 69750 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73725.190840 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 69047.520661 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 74779.761905 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 78661.764706 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71365.384615 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 70653.125000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 90625 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 65428.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 70153.846154 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71552.129222 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 69047.520661 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 74779.761905 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78661.764706 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71365.384615 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 70653.125000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 90625 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 65428.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 70153.846154 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71552.129222 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 362 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 75 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 538 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 17 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 78 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 362 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 75 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 669 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 362 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 75 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 669 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20478250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4729000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 985000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4446750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 678750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 236250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 31679000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 230023 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 170017 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 780078 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5761500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 888250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 687000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8038000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 20478250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 10490500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 985000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 763750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 4446750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1567000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 236250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 749500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 39717000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 20478250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 10490500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 985000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 763750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 4446750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1567000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 236250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 749500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 39717000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.242670 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284923 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284923 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63905.405405 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59290 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 96964.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 58882.899628 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58437.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 57250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61358.778626 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62443.452381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59290 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 78350 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59367.713004 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62443.452381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59290 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 78350 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59367.713004 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.trans_dist::ReadReq 2766 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2765 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 406 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 406 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 353 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 998 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5880 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 150272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1022 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3452 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3452 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3452 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1739480 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2819999 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1460516 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2239746 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1188247 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2234243 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1152996 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2246748 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1204495 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) -system.cpu0.branchPred.lookups 81418 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78534 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1187 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78143 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75395 # Number of BTB hits +system.physmem.avgGap 158667.67 # Average gap between requests +system.physmem.pageHitRate 76.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 687960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 375375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2753400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 29877120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34680750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 74985885 # Total energy per rank (pJ) +system.physmem_0.averagePower 738.913691 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57973250 # Time in different power states +system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40577250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 27463455 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36789750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 73457280 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.948851 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 62480000 # Time in different power states +system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37046000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu0.branchPred.lookups 81296 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78365 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1199 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 77900 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75117 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.483370 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 733 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 96.427471 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 763 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211393 # number of cpu cycles simulated +system.cpu0.numCycles 211085 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20064 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 481063 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81418 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76128 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 164143 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2675 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 20068 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 480268 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81296 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 75880 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 163785 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1880 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 7123 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 658 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 187427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.566669 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.225288 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1916 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 7139 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 648 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 187121 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.566617 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.228608 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30149 16.09% 16.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77654 41.43% 57.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 823 0.44% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1078 0.58% 58.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 624 0.33% 58.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 72980 38.94% 97.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 691 0.37% 98.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 437 0.23% 98.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2991 1.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30271 16.18% 16.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77424 41.38% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 764 0.41% 57.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1076 0.58% 58.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 72740 38.87% 97.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 718 0.38% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 448 0.24% 98.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3056 1.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 187427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.385150 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.275681 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15737 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17837 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 151841 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 675 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1337 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 469212 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1337 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16355 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2021 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14599 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 151852 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1263 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 465757 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 187121 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.385134 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.275235 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 17868 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 151448 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 678 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1349 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 468198 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1349 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16395 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2033 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 151464 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1264 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 464735 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu0.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 319012 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 928821 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 701999 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 305055 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13957 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 896 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 905 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4572 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148578 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75186 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72446 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72197 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 389771 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 964 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 386457 # Number of instructions issued +system.cpu0.rename.RenamedOperands 318331 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 926755 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 700443 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 304259 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14072 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4585 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148203 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75025 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72247 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 71998 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 388891 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 968 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 385538 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12213 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11103 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 405 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 187427 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.061907 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.125198 # Number of insts issued each cycle +system.cpu0.iq.iqSquashedInstsExamined 12303 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11219 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 409 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 187121 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.060367 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.127018 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33106 17.66% 17.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4299 2.29% 19.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73629 39.28% 59.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73187 39.05% 98.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1656 0.88% 99.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 900 0.48% 99.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 407 0.22% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 171 0.09% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 72 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33176 17.73% 17.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4313 2.30% 20.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73426 39.24% 59.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 72986 39.00% 98.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1673 0.89% 99.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 893 0.48% 99.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 397 0.21% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 180 0.10% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 187427 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 187121 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 96 33.92% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 84 29.68% 63.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 36.40% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 102 35.29% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 84 29.07% 64.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 163898 42.41% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 148040 38.31% 80.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74519 19.28% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 163537 42.42% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 147667 38.30% 80.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74334 19.28% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 386457 # Type of FU issued -system.cpu0.iq.rate 1.828145 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 283 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000732 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 960647 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 403001 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 384607 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 385538 # Type of FU issued +system.cpu0.iq.rate 1.826459 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000750 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 958509 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 402215 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 383670 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 386740 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 385827 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71819 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71619 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2461 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1659 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1337 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1980 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 463607 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148578 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75186 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 843 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1995 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 462536 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148203 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75025 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 847 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 323 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1099 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1422 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 385445 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147736 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 324 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 384525 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 147369 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1013 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72872 # number of nop insts executed -system.cpu0.iew.exec_refs 222117 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76458 # Number of branches executed -system.cpu0.iew.exec_stores 74381 # Number of stores executed -system.cpu0.iew.exec_rate 1.823357 # Inst execution rate -system.cpu0.iew.wb_sent 384977 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 384607 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 228096 # num instructions producing a value -system.cpu0.iew.wb_consumers 231328 # num instructions consuming a value +system.cpu0.iew.exec_nop 72677 # number of nop insts executed +system.cpu0.iew.exec_refs 221564 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76264 # Number of branches executed +system.cpu0.iew.exec_stores 74195 # Number of stores executed +system.cpu0.iew.exec_rate 1.821660 # Inst execution rate +system.cpu0.iew.wb_sent 384046 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 383670 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 227520 # num instructions producing a value +system.cpu0.iew.wb_consumers 230755 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.819393 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986028 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.817609 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.985981 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13622 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13745 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1187 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 184803 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.434668 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.147538 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1199 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 184477 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.432498 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.147629 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33298 18.02% 18.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75556 40.88% 58.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2014 1.09% 59.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 640 0.35% 60.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71511 38.70% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33360 18.08% 18.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75359 40.85% 58.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2024 1.10% 60.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 644 0.35% 60.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 522 0.28% 60.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71315 38.66% 99.32% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 246 0.13% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 487 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 184803 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 449934 # Number of instructions committed -system.cpu0.commit.committedOps 449934 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 184477 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 448740 # Number of instructions committed +system.cpu0.commit.committedOps 448740 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219682 # Number of memory references committed -system.cpu0.commit.loads 146117 # Number of loads committed +system.cpu0.commit.refs 219085 # Number of memory references committed +system.cpu0.commit.loads 145719 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75452 # Number of branches committed +system.cpu0.commit.branches 75253 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 303386 # Number of committed integer instructions. +system.cpu0.commit.int_insts 302590 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72184 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 157984 35.11% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 71985 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 157586 35.12% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction @@ -1050,195 +557,104 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 146201 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73565 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 145803 32.49% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73366 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 449934 # Class of committed instruction -system.cpu0.commit.bw_lim_events 488 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 448740 # Class of committed instruction +system.cpu0.commit.bw_lim_events 487 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 646710 # The number of ROB reads -system.cpu0.rob.rob_writes 929757 # The number of ROB writes +system.cpu0.rob.rob_reads 645314 # The number of ROB reads +system.cpu0.rob.rob_writes 927635 # The number of ROB writes system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23966 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 377666 # Number of Instructions Simulated -system.cpu0.committedOps 377666 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.559735 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559735 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.786559 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.786559 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 689346 # number of integer regfile reads -system.cpu0.int_regfile_writes 310987 # number of integer regfile writes +system.cpu0.idleCycles 23964 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 376671 # Number of Instructions Simulated +system.cpu0.committedOps 376671 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.560396 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.560396 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.784452 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.784452 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 687652 # number of integer regfile reads +system.cpu0.int_regfile_writes 310240 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 224004 # number of misc regfile reads +system.cpu0.misc_regfile_reads 223454 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.tags.replacements 322 # number of replacements -system.cpu0.icache.tags.tagsinuse 240.567538 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6326 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 612 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.336601 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.567538 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469858 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.469858 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7735 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7735 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6326 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6326 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6326 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6326 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6326 # number of overall hits -system.cpu0.icache.overall_hits::total 6326 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses -system.cpu0.icache.overall_misses::total 797 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36689746 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 36689746 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 36689746 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 36689746 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 36689746 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 36689746 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7123 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7123 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7123 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7123 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7123 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7123 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111891 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111891 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111891 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111891 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111891 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111891 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46034.813049 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46034.813049 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46034.813049 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46034.813049 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 613 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 613 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 613 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 613 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 613 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 613 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 28185001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 28185001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 28185001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 28185001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 28185001 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 28185001 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45978.794454 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.516453 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148253 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.523626 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 147885 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 872.076471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 869.911765 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.516453 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276399 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.276399 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.523626 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276413 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.276413 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 597940 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 597940 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75362 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75362 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72979 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72979 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 596477 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 596477 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75193 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75193 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72780 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72780 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148341 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148341 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148341 # number of overall hits -system.cpu0.dcache.overall_hits::total 148341 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 480 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 147973 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 147973 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147973 # number of overall hits +system.cpu0.dcache.overall_hits::total 147973 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 482 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 482 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1024 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1024 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1024 # number of overall misses -system.cpu0.dcache.overall_misses::total 1024 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15203420 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15203420 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32866263 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32866263 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 427750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 427750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48069683 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48069683 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48069683 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48069683 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75842 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75842 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73523 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73523 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1026 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1026 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1026 # number of overall misses +system.cpu0.dcache.overall_misses::total 1026 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15529368 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 15529368 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32868763 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32868763 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 428750 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 428750 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 48398131 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 48398131 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 48398131 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 48398131 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75675 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75675 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73324 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73324 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149365 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149365 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 149365 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 149365 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006329 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006329 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007399 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007399 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 148999 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 148999 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 148999 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 148999 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006369 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006369 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007419 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007419 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006856 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006856 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006856 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006856 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31673.791667 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31673.791667 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60415.924632 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 60415.924632 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19443.181818 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19443.181818 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46943.049805 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46943.049805 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006886 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006886 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006886 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006886 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32218.605809 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32218.605809 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60420.520221 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 60420.520221 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19488.636364 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19488.636364 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47171.667641 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47171.667641 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -1249,518 +665,519 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 298 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 299 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 663 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 663 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 664 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 664 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6258507 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6258507 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7387727 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7387727 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 382250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 382250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13646234 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13646234 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13646234 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13646234 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002400 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002435 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002435 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6541511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6541511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7390227 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7390227 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 383250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 383250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13931738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13931738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13931738 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13931738 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002418 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002418 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002441 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002441 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002417 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002417 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34387.401099 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34387.401099 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41272.217877 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41272.217877 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17375 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17375 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002430 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002430 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 35745.961749 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 35745.961749 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41286.184358 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41286.184358 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17420.454545 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17420.454545 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52620 # Number of BP lookups -system.cpu1.branchPred.condPredicted 49209 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1295 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 45306 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 44357 # Number of BTB hits +system.cpu0.icache.tags.replacements 319 # number of replacements +system.cpu0.icache.tags.tagsinuse 239.733862 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6347 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 608 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.439145 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.733862 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.468230 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.468230 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.564453 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7747 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7747 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6347 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6347 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6347 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6347 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6347 # number of overall hits +system.cpu0.icache.overall_hits::total 6347 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 792 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 792 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 792 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 792 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 792 # number of overall misses +system.cpu0.icache.overall_misses::total 792 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36432996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 36432996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 36432996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 36432996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 36432996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 36432996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7139 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7139 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7139 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7139 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7139 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7139 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110940 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110940 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110940 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110940 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110940 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110940 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46001.257576 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 46001.257576 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 46001.257576 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 46001.257576 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 183 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 183 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 183 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 183 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 183 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 609 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 609 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 609 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 609 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 609 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27995751 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27995751 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27995751 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27995751 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27995751 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27995751 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085306 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085306 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085306 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45970.034483 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 48230 # Number of BP lookups +system.cpu1.branchPred.condPredicted 44811 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1266 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 41091 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 39963 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.905355 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 875 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.254873 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 868 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 161023 # number of cpu cycles simulated +system.cpu1.numCycles 160735 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 31247 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 289875 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52620 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 45232 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 125550 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2747 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 33641 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 261327 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 48230 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 40831 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 122936 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2691 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1122 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 22380 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 159305 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.819623 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.179377 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1065 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 24854 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 432 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 159000 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.643566 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.124362 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 56744 35.62% 35.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52063 32.68% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6924 4.35% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3540 2.22% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1103 0.69% 75.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 33079 20.76% 96.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1261 0.79% 97.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 757 0.48% 97.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3834 2.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 63867 40.17% 40.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 48973 30.80% 70.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 8266 5.20% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3472 2.18% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1057 0.66% 79.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 27547 17.33% 96.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1174 0.74% 97.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 753 0.47% 97.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3891 2.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 159305 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.326786 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.800209 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17668 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57241 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 79500 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3513 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1373 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 275603 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1373 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18384 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 26779 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12577 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 80781 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 19401 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 272270 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 17163 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 159000 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.300059 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.625825 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17613 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 67674 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 68228 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4130 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1345 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 247069 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1345 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18292 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33178 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 12317 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 69139 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 24719 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 243777 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 21468 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 22 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 191050 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 520032 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 405162 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 176680 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14370 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1196 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 24088 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 76067 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 35939 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 36374 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 30769 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 225624 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6666 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 227547 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 18 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11238 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 649 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 159305 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.428373 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.374842 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 169834 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 458131 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 358650 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 155489 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14345 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 29340 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 66237 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 30368 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 32190 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 25244 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 200152 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7929 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 203048 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12672 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 159000 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.277031 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.370207 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 60375 37.90% 37.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 22487 14.12% 52.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 35297 22.16% 74.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 34879 21.89% 96.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3406 2.14% 98.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1579 0.99% 99.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 224 0.14% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 67764 42.62% 42.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26124 16.43% 59.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 29595 18.61% 77.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 29204 18.37% 96.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3405 2.14% 98.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1592 1.00% 99.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 226 0.14% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 210 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 159305 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 159000 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 89 26.49% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 38 11.31% 37.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 62.20% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 87 24.30% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 62 17.32% 41.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 58.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 111688 49.08% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 80614 35.43% 84.51% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 35245 15.49% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 101499 49.99% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 71903 35.41% 85.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 29646 14.60% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 227547 # Type of FU issued -system.cpu1.iq.rate 1.413134 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 336 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001477 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 614753 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 244854 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 225845 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 203048 # Type of FU issued +system.cpu1.iq.rate 1.263247 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 358 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001763 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 565493 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 220798 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 201375 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 227883 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 203406 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 30551 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 24951 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2638 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2787 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1613 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1373 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7085 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 269526 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 76067 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 35939 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1117 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1345 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 8539 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 241028 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 239 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 66237 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 30368 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1097 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 476 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1037 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1513 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 226408 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 75003 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1139 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1009 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1474 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 201951 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 65061 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 37236 # number of nop insts executed -system.cpu1.iew.exec_refs 110148 # number of memory reference insts executed -system.cpu1.iew.exec_branches 46633 # Number of branches executed -system.cpu1.iew.exec_stores 35145 # Number of stores executed -system.cpu1.iew.exec_rate 1.406060 # Inst execution rate -system.cpu1.iew.wb_sent 226126 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 225845 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 127804 # num instructions producing a value -system.cpu1.iew.wb_consumers 134338 # num instructions consuming a value +system.cpu1.iew.exec_nop 32947 # number of nop insts executed +system.cpu1.iew.exec_refs 94595 # number of memory reference insts executed +system.cpu1.iew.exec_branches 42219 # Number of branches executed +system.cpu1.iew.exec_stores 29534 # Number of stores executed +system.cpu1.iew.exec_rate 1.256422 # Inst execution rate +system.cpu1.iew.wb_sent 201670 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 201375 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 112178 # num instructions producing a value +system.cpu1.iew.wb_consumers 118722 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.402564 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.951361 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.252839 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.944880 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14108 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6017 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1295 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 156709 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.629549 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.048246 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14315 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1266 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 156398 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.449251 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.979774 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 66028 42.13% 42.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 43411 27.70% 69.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5268 3.36% 73.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6809 4.34% 77.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1543 0.98% 78.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 30606 19.53% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 798 0.51% 98.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 967 0.62% 99.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1279 0.82% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 74586 47.69% 47.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 38945 24.90% 72.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5214 3.33% 75.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8053 5.15% 81.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1537 0.98% 82.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 24957 15.96% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 851 0.54% 98.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 951 0.61% 99.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1304 0.83% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 156709 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 255365 # Number of instructions committed -system.cpu1.commit.committedOps 255365 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 156398 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 226660 # Number of instructions committed +system.cpu1.commit.committedOps 226660 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 107755 # Number of memory references committed -system.cpu1.commit.loads 73429 # Number of loads committed -system.cpu1.commit.membars 5300 # Number of memory barriers committed -system.cpu1.commit.branches 45589 # Number of branches committed +system.cpu1.commit.refs 92171 # Number of memory references committed +system.cpu1.commit.loads 63450 # Number of loads committed +system.cpu1.commit.membars 6533 # Number of memory barriers committed +system.cpu1.commit.branches 41215 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 175463 # Number of committed integer instructions. +system.cpu1.commit.int_insts 155506 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 36376 14.24% 14.24% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 105934 41.48% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 78729 30.83% 86.56% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 34326 13.44% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 32002 14.12% 14.12% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 95954 42.33% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 69983 30.88% 87.33% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 28721 12.67% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 255365 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1279 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 226660 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 424317 # The number of ROB reads -system.cpu1.rob.rob_writes 541540 # The number of ROB writes -system.cpu1.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1718 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43314 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 213689 # Number of Instructions Simulated -system.cpu1.committedOps 213689 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.753539 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.753539 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.327071 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.327071 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 390200 # number of integer regfile reads -system.cpu1.int_regfile_writes 182656 # number of integer regfile writes +system.cpu1.rob.rob_reads 395483 # The number of ROB reads +system.cpu1.rob.rob_writes 484550 # The number of ROB writes +system.cpu1.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1735 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 188125 # Number of Instructions Simulated +system.cpu1.committedOps 188125 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.854405 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.854405 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.170405 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.170405 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 343348 # number of integer regfile reads +system.cpu1.int_regfile_writes 161358 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 111763 # number of misc regfile reads +system.cpu1.misc_regfile_reads 96189 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.tags.replacements 388 # number of replacements -system.cpu1.icache.tags.tagsinuse 78.707719 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21821 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 43.905433 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 78.707719 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.153726 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.153726 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22877 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22877 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21821 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21821 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21821 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21821 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21821 # number of overall hits -system.cpu1.icache.overall_hits::total 21821 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 559 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 559 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 559 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 559 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 559 # number of overall misses -system.cpu1.icache.overall_misses::total 559 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8425746 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8425746 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8425746 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8425746 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8425746 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8425746 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 22380 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 22380 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22380 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22380 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22380 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22380 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024978 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024978 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024978 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024978 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024978 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024978 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15072.890877 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15072.890877 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15072.890877 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15072.890877 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6648254 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6648254 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6648254 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6648254 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6648254 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6648254 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022207 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022207 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022207 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13376.768612 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.402316 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 40362 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 23.332143 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 34754 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1441.500000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1241.214286 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.402316 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.047661 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.047661 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.332143 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.045571 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.045571 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 315306 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 315306 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 43998 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 43998 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 34119 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 34119 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 78117 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 78117 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 78117 # number of overall hits -system.cpu1.dcache.overall_hits::total 78117 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 439 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 439 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 136 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 136 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 575 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 575 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 575 # number of overall misses -system.cpu1.dcache.overall_misses::total 575 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5820038 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5820038 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2819511 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2819511 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 502006 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 502006 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8639549 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8639549 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8639549 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8639549 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 44437 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 44437 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 34255 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 34255 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.tags.tag_accesses 275515 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 275515 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 39673 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39673 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 28513 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 28513 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 68186 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 68186 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 68186 # number of overall hits +system.cpu1.dcache.overall_hits::total 68186 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 422 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 422 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 559 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 559 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 559 # number of overall misses +system.cpu1.dcache.overall_misses::total 559 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5603617 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5603617 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2812761 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2812761 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 492507 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 492507 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8416378 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8416378 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8416378 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8416378 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40095 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40095 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 28650 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 28650 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 78692 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 78692 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 78692 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 78692 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009879 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009879 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003970 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003970 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007307 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007307 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007307 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007307 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13257.489749 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13257.489749 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20731.698529 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20731.698529 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8655.275862 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 8655.275862 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15025.302609 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15025.302609 # average overall miss latency +system.cpu1.dcache.demand_accesses::cpu1.data 68745 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 68745 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 68745 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 68745 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010525 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010525 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004782 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004782 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008132 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.008132 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008132 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.008132 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13278.713270 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13278.713270 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20531.102190 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20531.102190 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8640.473684 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 8640.473684 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15056.132379 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15056.132379 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1769,520 +1186,519 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 276 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 308 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 308 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 308 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 267 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 267 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1085520 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1085520 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1288239 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1288239 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 385994 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 385994 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2373759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2373759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2373759 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2373759 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003668 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003668 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003036 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003036 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003393 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003393 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6659.631902 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6659.631902 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12386.913462 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12386.913462 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6655.068966 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6655.068966 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 262 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 296 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 296 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1125015 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1125015 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1272489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1272489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 378493 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 378493 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2397504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2397504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2397504 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2397504 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003595 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003595 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7031.343750 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7031.343750 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12354.262136 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12354.262136 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6640.228070 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6640.228070 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 52660 # Number of BP lookups -system.cpu2.branchPred.condPredicted 48877 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1286 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 45218 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 43881 # Number of BTB hits +system.cpu1.icache.tags.replacements 388 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.215682 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 24292 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 48.779116 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.215682 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.148859 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.148859 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 25352 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 25352 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 24292 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 24292 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 24292 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 24292 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 24292 # number of overall hits +system.cpu1.icache.overall_hits::total 24292 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 562 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 562 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 562 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 562 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 562 # number of overall misses +system.cpu1.icache.overall_misses::total 562 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7960746 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7960746 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7960746 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7960746 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7960746 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7960746 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 24854 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 24854 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 24854 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 24854 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 24854 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 24854 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022612 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022612 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022612 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022612 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022612 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022612 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.028470 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14165.028470 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14165.028470 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14165.028470 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 64 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 64 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 64 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 64 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 498 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6368004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6368004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6368004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6368004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6368004 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6368004 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020037 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.020037 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.020037 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12787.156627 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.branchPred.lookups 55295 # Number of BP lookups +system.cpu2.branchPred.condPredicted 51520 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1304 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 47890 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 46487 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.043213 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 913 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.070370 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 160663 # number of cpu cycles simulated +system.cpu2.numCycles 160375 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 30584 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 291962 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 52660 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 44794 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 122431 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2729 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 28879 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 309014 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 55295 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 47386 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 123906 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1111 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 21169 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 155507 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.877485 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.219728 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.CacheLines 19451 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 461 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 155294 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.989864 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.243889 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 53998 34.72% 34.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51209 32.93% 67.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6210 3.99% 71.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3413 2.19% 73.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 933 0.60% 74.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 33386 21.47% 95.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1293 0.83% 96.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 846 0.54% 97.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4219 2.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49501 31.88% 31.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 52893 34.06% 65.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5338 3.44% 69.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3457 2.23% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 949 0.61% 72.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 36899 23.76% 95.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1216 0.78% 96.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 841 0.54% 97.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 4200 2.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155507 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.327767 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.817232 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17863 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 52592 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 80411 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3267 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1364 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 276853 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1364 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18564 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 24147 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12636 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 81735 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 17051 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 273529 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 15090 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 155294 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.344786 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.926822 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17746 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 46456 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 86830 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 2870 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1382 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 293603 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1382 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18442 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 20397 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12871 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 87967 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14225 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 290431 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 12472 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 29 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 193256 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 525177 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 409210 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 178291 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 14965 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1175 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 21746 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 76624 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 36478 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 36325 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31287 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 227715 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6015 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 228842 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13120 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11533 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155507 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.471586 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.386146 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 205748 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 562377 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 437048 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 190737 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15011 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1232 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 18731 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 82610 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 39860 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 38981 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34721 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 242796 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 5190 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 242904 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13134 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12157 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155294 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.564156 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.378675 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 57410 36.92% 36.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 20565 13.22% 50.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 35759 23.00% 73.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 35374 22.75% 95.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3397 2.18% 98.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1636 1.05% 99.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 896 0.58% 99.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 267 0.17% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 203 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 52943 34.09% 34.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 18212 11.73% 45.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39071 25.16% 70.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38654 24.89% 95.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3479 2.24% 98.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1594 1.03% 99.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 891 0.57% 99.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 244 0.16% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155507 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155294 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 89 26.57% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 37 11.04% 37.61% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 90 25.64% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 52 14.81% 40.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 59.54% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 112448 49.14% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 80571 35.21% 84.35% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 35823 15.65% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 118122 48.63% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 85639 35.26% 83.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 39143 16.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 228842 # Type of FU issued -system.cpu2.iq.rate 1.424360 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 335 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001464 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 613560 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 246890 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 227101 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 242904 # Type of FU issued +system.cpu2.iq.rate 1.514600 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 351 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001445 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 641482 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 261162 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 241189 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 229177 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 243255 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 31107 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 34438 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2866 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1596 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1666 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6807 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 270837 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 190 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 76624 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 36478 # Number of dispatched store instructions +system.cpu2.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 6074 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 287692 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 82610 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 39860 # Number of dispatched store instructions system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1049 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 227700 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 75599 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedNotTakenIncorrect 1074 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1544 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 241779 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 81452 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1125 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 37107 # number of nop insts executed -system.cpu2.iew.exec_refs 111310 # number of memory reference insts executed -system.cpu2.iew.exec_branches 46563 # Number of branches executed -system.cpu2.iew.exec_stores 35711 # Number of stores executed -system.cpu2.iew.exec_rate 1.417252 # Inst execution rate -system.cpu2.iew.wb_sent 227402 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 227101 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 129036 # num instructions producing a value -system.cpu2.iew.wb_consumers 135804 # num instructions consuming a value +system.cpu2.iew.exec_nop 39706 # number of nop insts executed +system.cpu2.iew.exec_refs 120488 # number of memory reference insts executed +system.cpu2.iew.exec_branches 49059 # Number of branches executed +system.cpu2.iew.exec_stores 39036 # Number of stores executed +system.cpu2.iew.exec_rate 1.507585 # Inst execution rate +system.cpu2.iew.wb_sent 241491 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 241189 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 138145 # num instructions producing a value +system.cpu2.iew.wb_consumers 144798 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.413524 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.950163 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.503906 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.954053 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14614 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5368 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1286 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152859 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.675858 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.068536 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14779 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 4578 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1304 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 152612 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.787933 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.101313 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 62472 40.87% 40.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 43239 28.29% 69.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5166 3.38% 72.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6247 4.09% 76.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1528 1.00% 77.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 31073 20.33% 97.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 875 0.57% 98.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 941 0.62% 99.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1318 0.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 57189 37.47% 37.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 45780 30.00% 67.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5178 3.39% 70.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5403 3.54% 74.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1516 0.99% 75.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34396 22.54% 97.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 886 0.58% 98.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 957 0.63% 99.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1307 0.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152859 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 256170 # Number of instructions committed -system.cpu2.commit.committedOps 256170 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 152612 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 272860 # Number of instructions committed +system.cpu2.commit.committedOps 272860 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 108804 # Number of memory references committed -system.cpu2.commit.loads 73922 # Number of loads committed -system.cpu2.commit.membars 4659 # Number of memory barriers committed -system.cpu2.commit.branches 45502 # Number of branches committed +system.cpu2.commit.refs 117938 # Number of memory references committed +system.cpu2.commit.loads 79744 # Number of loads committed +system.cpu2.commit.membars 3865 # Number of memory barriers committed +system.cpu2.commit.branches 48024 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 176434 # Number of committed integer instructions. +system.cpu2.commit.int_insts 188084 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 36297 14.17% 14.17% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 106410 41.54% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 78581 30.68% 86.38% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 34882 13.62% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 38815 14.23% 14.23% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 112242 41.14% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 83609 30.64% 86.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 38194 14.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 256170 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1318 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 272860 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1307 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 421739 # The number of ROB reads -system.cpu2.rob.rob_writes 544215 # The number of ROB writes +system.cpu2.rob.rob_reads 438358 # The number of ROB reads +system.cpu2.rob.rob_writes 577962 # The number of ROB writes system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5156 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 43676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 215214 # Number of Instructions Simulated -system.cpu2.committedOps 215214 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.746527 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.746527 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.339537 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.339537 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 394013 # number of integer regfile reads -system.cpu2.int_regfile_writes 184721 # number of integer regfile writes +system.cpu2.idleCycles 5081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 43644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 230180 # Number of Instructions Simulated +system.cpu2.committedOps 230180 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.696737 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.696737 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.435261 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.435261 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 421380 # number of integer regfile reads +system.cpu2.int_regfile_writes 197053 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 112958 # number of misc regfile reads +system.cpu2.misc_regfile_reads 122100 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.tags.replacements 380 # number of replacements -system.cpu2.icache.tags.tagsinuse 85.367642 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 20592 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 493 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 41.768763 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 85.367642 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.166734 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.166734 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 21662 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 21662 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 20592 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 20592 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 20592 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 20592 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 20592 # number of overall hits -system.cpu2.icache.overall_hits::total 20592 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 577 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 577 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 577 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 577 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 577 # number of overall misses -system.cpu2.icache.overall_misses::total 577 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13065992 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 13065992 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 13065992 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 13065992 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 13065992 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 13065992 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 21169 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 21169 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 21169 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 21169 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 21169 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 21169 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.027257 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.027257 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.027257 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.027257 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.027257 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.027257 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22644.700173 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22644.700173 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22644.700173 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22644.700173 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 84 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 84 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 84 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 84 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 493 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 493 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 493 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 493 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 493 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 493 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10294257 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10294257 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10294257 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10294257 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10294257 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10294257 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.023289 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.023289 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.023289 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 20880.845842 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 20880.845842 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 20880.845842 # average overall mshr miss latency -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 25.876504 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 41118 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1417.862069 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 25.900864 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 44302 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1582.214286 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.876504 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050540 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.050540 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.900864 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050588 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.050588 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 317671 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 317671 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 44059 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 44059 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 34671 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 34671 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 78730 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 78730 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 78730 # number of overall hits -system.cpu2.dcache.overall_hits::total 78730 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 415 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 415 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 148 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 148 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 563 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 563 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 563 # number of overall misses -system.cpu2.dcache.overall_misses::total 563 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7441548 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7441548 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3663511 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3663511 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 451006 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 451006 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 11105059 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 11105059 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 11105059 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 11105059 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 44474 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 44474 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 34819 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 34819 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 63 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 79293 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 79293 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 79293 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 79293 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009331 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009331 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004251 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004251 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.777778 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.777778 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007100 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007100 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007100 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007100 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17931.440964 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17931.440964 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24753.452703 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 24753.452703 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9204.204082 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9204.204082 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 19724.793961 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 19724.793961 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 341013 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 341013 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 46548 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 46548 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 37978 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 37978 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 84526 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 84526 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 84526 # number of overall hits +system.cpu2.dcache.overall_hits::total 84526 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 448 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 448 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 149 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 149 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 597 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 597 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 597 # number of overall misses +system.cpu2.dcache.overall_misses::total 597 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7705986 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 7705986 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3669012 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3669012 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 505508 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 505508 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 11374998 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 11374998 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 11374998 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 11374998 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 46996 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 46996 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 38127 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 38127 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 85123 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 85123 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 85123 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 85123 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009533 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009533 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003908 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003908 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.820896 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007013 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007013 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007013 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007013 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17200.861607 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17200.861607 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24624.241611 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 24624.241611 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9191.054545 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9191.054545 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 19053.597990 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 19053.597990 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2291,518 +1707,519 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 262 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 40 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 302 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 302 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 153 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 289 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 330 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 330 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1686771 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1686771 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511239 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511239 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 352994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 352994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3198010 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3198010 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3198010 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3198010 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003440 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003440 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003102 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003102 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.777778 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.777778 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003292 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003292 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11024.647059 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11024.647059 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13992.953704 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13992.953704 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7203.959184 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7203.959184 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526276 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526276 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511738 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511738 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 395492 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 395492 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3038014 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3038014 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3038014 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3038014 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003383 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003383 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002833 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002833 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.820896 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003137 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003137 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9599.220126 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9599.220126 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13997.574074 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13997.574074 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7190.763636 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7190.763636 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 48141 # Number of BP lookups -system.cpu3.branchPred.condPredicted 44605 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1305 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 40897 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 39710 # Number of BTB hits +system.cpu2.icache.tags.replacements 378 # number of replacements +system.cpu2.icache.tags.tagsinuse 84.872672 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 18881 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 38.532653 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.872672 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165767 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.165767 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 19941 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 19941 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 18881 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 18881 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 18881 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 18881 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 18881 # number of overall hits +system.cpu2.icache.overall_hits::total 18881 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses +system.cpu2.icache.overall_misses::total 570 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13340243 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 13340243 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 13340243 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 13340243 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 13340243 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 13340243 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19451 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19451 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19451 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19451 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19451 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19451 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029304 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.029304 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029304 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.029304 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029304 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.029304 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23403.935088 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23403.935088 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23403.935088 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23403.935088 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10370006 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10370006 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10370006 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10370006 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10370006 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10370006 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025192 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.025192 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.025192 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21163.277551 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.branchPred.lookups 49708 # Number of BP lookups +system.cpu3.branchPred.condPredicted 46346 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 42456 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 41477 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.097587 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 884 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.694083 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 887 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 160319 # number of cpu cycles simulated +system.cpu3.numCycles 160031 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 33851 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 260297 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 48141 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 40594 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 122891 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 32677 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 271496 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49708 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 42364 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 123781 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2713 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1076 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24972 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 417 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 159213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.634898 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.125574 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1129 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23830 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 414 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 158956 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.707995 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.148637 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 64563 40.55% 40.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 48696 30.59% 71.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8235 5.17% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3504 2.20% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1064 0.67% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 27204 17.09% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1240 0.78% 97.04% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 753 0.47% 97.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3954 2.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 61281 38.55% 38.55% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 50034 31.48% 70.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7755 4.88% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3467 2.18% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1003 0.63% 77.72% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 29472 18.54% 96.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1313 0.83% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 747 0.47% 97.56% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3884 2.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 159213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.300283 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.623619 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17777 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 68157 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 67726 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4161 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1382 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 245360 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1382 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18479 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 33142 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12841 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 69300 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 24059 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 241885 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 21460 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 158956 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.310615 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.696521 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17592 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 63734 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 72321 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3943 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1356 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 257189 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1356 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18288 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 30790 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12415 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 73229 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 22868 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 253914 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 19808 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 26 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 168616 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 454082 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 355646 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 153987 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14629 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1214 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1272 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 28919 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 65522 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 29976 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31799 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24828 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 198526 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7988 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 201423 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12862 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11999 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 692 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 159213 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.265117 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.367863 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 177532 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 480099 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 375267 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 162743 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14789 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1176 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 27539 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 69653 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 32298 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33633 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 27116 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 209239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7471 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 211679 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 13005 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11959 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 663 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 158956 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.331683 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.377458 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 68514 43.03% 43.03% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 26230 16.47% 59.51% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 29303 18.40% 77.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 28880 18.14% 96.05% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3418 2.15% 98.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1568 0.98% 99.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 871 0.55% 99.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 223 0.14% 99.87% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 65156 40.99% 40.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24774 15.59% 56.58% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31508 19.82% 76.40% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 31138 19.59% 95.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3432 2.16% 98.15% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1609 1.01% 99.16% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 879 0.55% 99.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 252 0.16% 99.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 159213 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 158956 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 92 26.36% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 48 13.75% 40.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 59.89% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 91 25.07% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 63 17.36% 42.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 100972 50.13% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 71204 35.35% 85.48% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 29247 14.52% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 105163 49.68% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 74926 35.40% 85.08% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31590 14.92% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 201423 # Type of FU issued -system.cpu3.iq.rate 1.256389 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 349 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001733 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 562441 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 219414 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 199715 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 211679 # Type of FU issued +system.cpu3.iq.rate 1.322737 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 363 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001715 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 582726 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 229757 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 209929 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 201772 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 212042 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 24567 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26876 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2806 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2797 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1637 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1652 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8523 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 239131 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 65522 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 29976 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1120 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1356 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8047 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 251105 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 69653 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 32298 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1093 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1054 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 200291 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 64311 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1132 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 42 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1042 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 210537 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 68521 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 32617 # number of nop insts executed -system.cpu3.iew.exec_refs 93457 # number of memory reference insts executed -system.cpu3.iew.exec_branches 41928 # Number of branches executed -system.cpu3.iew.exec_stores 29146 # Number of stores executed -system.cpu3.iew.exec_rate 1.249328 # Inst execution rate -system.cpu3.iew.wb_sent 200012 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 199715 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 111117 # num instructions producing a value -system.cpu3.iew.wb_consumers 117670 # num instructions consuming a value +system.cpu3.iew.exec_nop 34395 # number of nop insts executed +system.cpu3.iew.exec_refs 99995 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43728 # Number of branches executed +system.cpu3.iew.exec_stores 31474 # Number of stores executed +system.cpu3.iew.exec_rate 1.315601 # Inst execution rate +system.cpu3.iew.wb_sent 210248 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 209929 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 117676 # num instructions producing a value +system.cpu3.iew.wb_consumers 124324 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.245735 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.944310 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.311802 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.946527 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14558 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7296 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1305 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 156559 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.434092 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.973064 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14613 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6808 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 156309 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.007092 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 75373 48.14% 48.14% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 38673 24.70% 72.85% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5214 3.33% 76.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8076 5.16% 81.33% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1539 0.98% 82.32% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24642 15.74% 98.06% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 775 0.50% 98.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1306 0.83% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 71539 45.77% 45.77% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 40455 25.88% 71.65% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5161 3.30% 74.95% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7618 4.87% 79.82% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1540 0.99% 80.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 26903 17.21% 98.02% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 829 0.53% 98.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 953 0.61% 99.16% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1311 0.84% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 156559 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 224520 # Number of instructions committed -system.cpu3.commit.committedOps 224520 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 156309 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 236439 # Number of instructions committed +system.cpu3.commit.committedOps 236439 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 91055 # Number of memory references committed -system.cpu3.commit.loads 62716 # Number of loads committed -system.cpu3.commit.membars 6575 # Number of memory barriers committed -system.cpu3.commit.branches 40877 # Number of branches committed +system.cpu3.commit.refs 97502 # Number of memory references committed +system.cpu3.commit.loads 66856 # Number of loads committed +system.cpu3.commit.membars 6091 # Number of memory barriers committed +system.cpu3.commit.branches 42698 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 154046 # Number of committed integer instructions. +system.cpu3.commit.int_insts 162319 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 31660 14.10% 14.10% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 95230 42.41% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 69291 30.86% 87.38% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 28339 12.62% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33485 14.16% 14.16% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 99361 42.02% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 72947 30.85% 87.04% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30646 12.96% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 224520 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1306 # number cycles where commit BW limit reached +system.cpu3.commit.op_class_0::total 236439 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1311 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 393745 # The number of ROB reads -system.cpu3.rob.rob_writes 480811 # The number of ROB writes -system.cpu3.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1106 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44020 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 186285 # Number of Instructions Simulated -system.cpu3.committedOps 186285 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.860611 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.860611 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.161965 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.161965 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 340113 # number of integer regfile reads -system.cpu3.int_regfile_writes 159981 # number of integer regfile writes +system.cpu3.rob.rob_reads 405464 # The number of ROB reads +system.cpu3.rob.rob_writes 504751 # The number of ROB writes +system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1075 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 43988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 196863 # Number of Instructions Simulated +system.cpu3.committedOps 196863 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.812905 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.812905 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.230155 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.230155 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 359772 # number of integer regfile reads +system.cpu3.int_regfile_writes 168916 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 95078 # number of misc regfile reads +system.cpu3.misc_regfile_reads 101608 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.tags.replacements 386 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.771025 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 24411 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 499 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 48.919840 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.771025 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151897 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151897 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 25471 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 25471 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 24411 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 24411 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 24411 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 24411 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 24411 # number of overall hits -system.cpu3.icache.overall_hits::total 24411 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 561 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 561 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 561 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 561 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 561 # number of overall misses -system.cpu3.icache.overall_misses::total 561 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7400997 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7400997 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7400997 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7400997 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7400997 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7400997 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24972 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24972 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24972 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24972 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24972 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24972 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022465 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.022465 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022465 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.022465 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022465 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.022465 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13192.508021 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13192.508021 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13192.508021 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13192.508021 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 499 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 499 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 499 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 499 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 499 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 499 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5888752 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5888752 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5888752 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5888752 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5888752 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5888752 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.019982 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.019982 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.019982 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11801.106212 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11801.106212 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11801.106212 # average overall mshr miss latency -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.453129 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 34358 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1227.071429 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.432858 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 36837 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1270.241379 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.453129 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045807 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.045807 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.432858 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047720 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047720 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 272485 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 272485 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 39283 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 39283 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 28128 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 28128 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 67411 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 67411 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 67411 # number of overall hits -system.cpu3.dcache.overall_hits::total 67411 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 435 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 435 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 136 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 136 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 62 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 62 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 571 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 571 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 571 # number of overall misses -system.cpu3.dcache.overall_misses::total 571 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5776999 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 5776999 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2748012 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2748012 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 544508 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 544508 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 8525011 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 8525011 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 8525011 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 8525011 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 39718 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 39718 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 28264 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 28264 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 75 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 75 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 67982 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 67982 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 67982 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 67982 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010952 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010952 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004812 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004812 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.826667 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.826667 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008399 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008399 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008399 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008399 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13280.457471 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 13280.457471 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20205.970588 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20205.970588 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8782.387097 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 8782.387097 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14929.966725 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 14929.966725 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14929.966725 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 14929.966725 # average overall miss latency +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 289352 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 289352 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41209 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41209 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 30434 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 30434 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 71643 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 71643 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 71643 # number of overall hits +system.cpu3.dcache.overall_hits::total 71643 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 419 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 419 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 141 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 141 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 560 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 560 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 560 # number of overall misses +system.cpu3.dcache.overall_misses::total 560 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5396537 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 5396537 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2783262 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2783262 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 481005 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 481005 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 8179799 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 8179799 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 8179799 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 8179799 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41628 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41628 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 30575 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 30575 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 72203 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 72203 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 72203 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 72203 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010065 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.010065 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004612 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004612 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007756 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007756 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007756 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007756 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12879.563246 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12879.563246 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19739.446809 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19739.446809 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8438.684211 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 8438.684211 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 14606.783929 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 14606.783929 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2811,54 +2228,642 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 269 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 269 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 166 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 62 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 269 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 269 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1189025 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1189025 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1291488 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1291488 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 420492 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 420492 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2480513 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2480513 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2480513 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2480513 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004179 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004179 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003644 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003644 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.826667 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.826667 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003957 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003957 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003957 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7162.801205 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7162.801205 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12538.718447 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12538.718447 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6782.129032 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6782.129032 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9221.237918 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9221.237918 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9221.237918 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9221.237918 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 259 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 259 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 293 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 293 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 293 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 293 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1078521 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1078521 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1312238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1312238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 366995 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 366995 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2390759 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2390759 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2390759 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2390759 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003844 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003844 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003500 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003500 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003698 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003698 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.756250 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.756250 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12263.906542 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12263.906542 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6438.508772 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6438.508772 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.tags.replacements 386 # number of replacements +system.cpu3.icache.tags.tagsinuse 78.630086 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 23274 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 495 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 47.018182 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 78.630086 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.153574 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.153574 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 24325 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 24325 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 23274 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23274 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23274 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23274 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 23274 # number of overall hits +system.cpu3.icache.overall_hits::total 23274 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 556 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 556 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 556 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 556 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 556 # number of overall misses +system.cpu3.icache.overall_misses::total 556 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7666496 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7666496 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7666496 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7666496 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7666496 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7666496 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 23830 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 23830 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 23830 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 23830 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 23830 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 23830 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023332 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023332 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023332 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023332 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023332 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023332 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13788.661871 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13788.661871 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13788.661871 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13788.661871 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 61 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 61 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 61 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 495 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 495 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 495 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 495 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 495 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 495 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5988753 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5988753 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5988753 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5988753 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5988753 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5988753 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020772 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020772 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.020772 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12098.490909 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 421.782597 # Cycle average of tags in use +system.l2c.tags.total_refs 1661 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 531 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.128060 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.793367 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 288.136506 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.239710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 7.908939 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.685353 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 57.810668 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.358893 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.126194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.722968 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004397 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000010 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000882 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000032 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006436 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 531 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008102 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 20025 # Number of tag accesses +system.l2c.tags.data_accesses 20025 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 248 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 483 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 489 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1661 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.l2c.demand_hits::cpu0.inst 248 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 483 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 409 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::total 1661 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 248 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 483 # number of overall hits +system.l2c.overall_hits::cpu1.data 11 # number of overall hits +system.l2c.overall_hits::cpu2.inst 409 # number of overall hits +system.l2c.overall_hits::cpu2.data 5 # number of overall hits +system.l2c.overall_hits::cpu3.inst 489 # number of overall hits +system.l2c.overall_hits::cpu3.data 11 # number of overall hits +system.l2c.overall_hits::total 1661 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 81 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::total 546 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 81 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::total 677 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 361 # number of overall misses +system.l2c.overall_misses::cpu0.data 168 # number of overall misses +system.l2c.overall_misses::cpu1.inst 15 # number of overall misses +system.l2c.overall_misses::cpu1.data 13 # number of overall misses +system.l2c.overall_misses::cpu2.inst 81 # number of overall misses +system.l2c.overall_misses::cpu2.data 20 # number of overall misses +system.l2c.overall_misses::cpu3.inst 6 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses +system.l2c.overall_misses::total 677 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 24898500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 5922000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 1027000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 5770000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 523250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 593000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 38883750 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6920500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 837000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 851750 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9656500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 24898500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 12842500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 1027000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 912000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 5770000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1570500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 593000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 926750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 48540250 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 24898500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 12842500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 1027000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 912000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 5770000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1570500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 593000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 926750 # number of overall miss cycles +system.l2c.overall_miss_latency::total 48540250 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 609 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 498 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 490 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 495 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2207 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 609 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 498 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 490 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 495 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2338 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 609 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 498 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 490 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 495 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2338 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.592775 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.030120 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.165306 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.012121 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.247395 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.962963 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.592775 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.030120 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.165306 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.012121 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.289564 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.592775 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.030120 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.165306 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.012121 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.289564 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68970.914127 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 80027.027027 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 68466.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 71234.567901 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 74750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 98833.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 71215.659341 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73622.340426 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69750 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80557.692308 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 70979.166667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73713.740458 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 68970.914127 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 68466.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 70153.846154 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 71234.567901 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 78525 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 98833.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 71288.461538 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71699.039882 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 68970.914127 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 68466.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 70153.846154 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 71234.567901 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 78525 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 98833.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 71288.461538 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71699.039882 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 360 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 12 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 76 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 534 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 78 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 360 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 12 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 76 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 665 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 360 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 12 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 76 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 665 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20340000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5009000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 701250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4539000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 390250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 31540750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 230023 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 180018 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 200020 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 170017 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 780078 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5761500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 687000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 888250 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 700750 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8037500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 20340000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 10770500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 701250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 749500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 4539000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1324500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 390250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 763250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 39578250 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 20340000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 10770500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 701250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 749500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 4539000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1324500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 390250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 763250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 39578250 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.241957 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.284431 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.284431 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67689.189189 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59065.074906 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58395.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61354.961832 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 534 # Transaction distribution +system.membus.trans_dist::ReadResp 533 # Transaction distribution +system.membus.trans_dist::UpgradeReq 274 # Transaction distribution +system.membus.trans_dist::UpgradeResp 78 # Transaction distribution +system.membus.trans_dist::ReadExReq 179 # Transaction distribution +system.membus.trans_dist::ReadExResp 131 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1729 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42496 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 244 # Total snoops (count) +system.membus.snoop_fanout::samples 987 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 987 # Request fanout histogram +system.membus.reqLayer0.occupancy 933500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 6348672 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.0 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2754 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2753 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 411 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 411 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1217 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5861 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 149632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1023 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3443 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1734981 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2800749 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1466512 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 2243496 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1172003 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 2220994 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 1183494 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 2229247 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1196246 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |