diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 1589 |
1 files changed, 988 insertions, 601 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 191a42060..befe09ef8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000104 # Nu sim_ticks 104317500 # Number of ticks simulated final_tick 104317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132902 # Simulator instruction rate (inst/s) -host_tick_rate 13605540 # Simulator tick rate (ticks/s) -host_mem_usage 226920 # Number of bytes of host memory used -host_seconds 7.67 # Real time elapsed on the host +host_inst_rate 190796 # Simulator instruction rate (inst/s) +host_op_rate 190795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19532213 # Simulator tick rate (ticks/s) +host_mem_usage 225896 # Number of bytes of host memory used +host_seconds 5.34 # Real time elapsed on the host sim_insts 1018993 # Number of instructions simulated +sim_ops 1018993 # Number of ops (including micro ops) simulated system.physmem.bytes_read 41984 # Number of bytes read from this memory system.physmem.bytes_inst_read 28224 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -234,6 +236,7 @@ system.cpu0.iew.wb_rate 1.886424 # in system.cpu0.iew.wb_fanout 0.991039 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitCommittedInsts 462799 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 462799 # The number of committed instructions system.cpu0.commit.commitSquashedInsts 9535 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1043 # The number of times a branch was mispredicted @@ -254,7 +257,8 @@ system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::total 188840 # Number of insts commited each cycle -system.cpu0.commit.count 462799 # Number of instructions committed +system.cpu0.commit.committedInsts 462799 # Number of instructions committed +system.cpu0.commit.committedOps 462799 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 226109 # Number of memory references committed system.cpu0.commit.loads 150402 # Number of loads committed @@ -270,6 +274,7 @@ system.cpu0.rob.rob_writes 946703 # Th system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 17790 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.committedInsts 388389 # Number of Instructions Simulated +system.cpu0.committedOps 388389 # Number of Ops (including micro ops) Simulated system.cpu0.committedInsts_total 388389 # Number of Instructions Simulated system.cpu0.cpi 0.537183 # CPI: Cycles Per Instruction system.cpu0.cpi_total 0.537183 # CPI: Total CPI of All Threads @@ -286,26 +291,39 @@ system.cpu0.icache.total_refs 4810 # To system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 8.278830 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 244.353680 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.477253 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 4810 # number of ReadReq hits -system.cpu0.icache.demand_hits 4810 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 4810 # number of overall hits -system.cpu0.icache.ReadReq_misses 705 # number of ReadReq misses -system.cpu0.icache.demand_misses 705 # number of demand (read+write) misses -system.cpu0.icache.overall_misses 705 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 27622000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 27622000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 27622000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses 5515 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses 5515 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses 5515 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.127833 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.127833 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.127833 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency 39180.141844 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency 39180.141844 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 39180.141844 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 244.353680 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.477253 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.477253 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 4810 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 4810 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 4810 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 4810 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 4810 # number of overall hits +system.cpu0.icache.overall_hits::total 4810 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 705 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 705 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 705 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 705 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 705 # number of overall misses +system.cpu0.icache.overall_misses::total 705 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 27622000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 27622000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 27622000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 27622000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 27622000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 27622000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5515 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5515 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5515 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5515 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5515 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5515 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.127833 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.127833 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.127833 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39180.141844 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -314,68 +332,90 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 123 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 582 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 582 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 582 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 21369000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 21369000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 21369000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.105530 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate 0.105530 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate 0.105530 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36716.494845 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 123 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 123 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 123 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 123 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 123 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 582 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 582 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 582 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 582 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 582 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 582 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21369000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21369000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21369000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21369000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21369000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21369000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 138.901719 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 140.432794 # Cycle average of tags in use system.cpu0.dcache.total_refs 97328 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 559.356322 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 140.432794 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.531076 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.274283 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.002990 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 77005 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits 75125 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits 23 # number of SwapReq hits -system.cpu0.dcache.demand_hits 152130 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 152130 # number of overall hits -system.cpu0.dcache.ReadReq_misses 517 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses 19 # number of SwapReq misses -system.cpu0.dcache.demand_misses 1057 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses 1057 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 14734500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 24692984 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency 371000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency 39427484 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 39427484 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 77522 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses 75665 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 153187 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 153187 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate 0.006669 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate 0.007137 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate 0.452381 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate 0.006900 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate 0.006900 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency 28500 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency 45727.748148 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency 19526.315789 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency 37301.309366 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 37301.309366 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 140.432794 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.274283 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.274283 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 77005 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77005 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75125 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75125 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 152130 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 152130 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 152130 # number of overall hits +system.cpu0.dcache.overall_hits::total 152130 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 517 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 517 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 540 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 540 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1057 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1057 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1057 # number of overall misses +system.cpu0.dcache.overall_misses::total 1057 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 14734500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14734500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24692984 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24692984 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 371000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 371000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 39427484 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 39427484 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 39427484 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 39427484 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 77522 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 77522 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 75665 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 75665 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 153187 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 153187 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 153187 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 153187 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006669 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007137 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006900 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006900 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28500 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45727.748148 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19526.315789 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -384,36 +424,46 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 327 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 368 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 695 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 695 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 190 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 172 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses 19 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 5255000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6251500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency 314000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 11506500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 11506500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002273 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.452381 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate 0.002363 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate 0.002363 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27657.894737 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36345.930233 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16526.315789 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 31785.911602 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 31785.911602 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks +system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 327 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 327 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 368 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 368 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 695 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 695 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 695 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 695 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 190 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 190 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6251500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6251500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 314000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 314000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11506500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11506500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11506500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11506500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002273 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27657.894737 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36345.930233 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16526.315789 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 174305 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -631,6 +681,7 @@ system.cpu1.iew.wb_rate 1.379140 # in system.cpu1.iew.wb_fanout 0.968192 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitCommittedInsts 275667 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 275667 # The number of committed instructions system.cpu1.commit.commitSquashedInsts 9533 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 5427 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 1085 # The number of times a branch was mispredicted @@ -651,7 +702,8 @@ system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::total 163203 # Number of insts commited each cycle -system.cpu1.commit.count 275667 # Number of instructions committed +system.cpu1.commit.committedInsts 275667 # Number of instructions committed +system.cpu1.commit.committedOps 275667 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.refs 118493 # Number of memory references committed system.cpu1.commit.loads 80399 # Number of loads committed @@ -668,6 +720,7 @@ system.cpu1.timesIdled 225 # Nu system.cpu1.idleCycles 2707 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 34329 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 231385 # Number of Instructions Simulated +system.cpu1.committedOps 231385 # Number of Ops (including micro ops) Simulated system.cpu1.committedInsts_total 231385 # Number of Instructions Simulated system.cpu1.cpi 0.753312 # CPI: Cycles Per Instruction system.cpu1.cpi_total 0.753312 # CPI: Total CPI of All Threads @@ -684,26 +737,39 @@ system.cpu1.icache.total_refs 17870 # To system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 41.850117 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 84.541118 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.165119 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits 17870 # number of ReadReq hits -system.cpu1.icache.demand_hits 17870 # number of demand (read+write) hits -system.cpu1.icache.overall_hits 17870 # number of overall hits -system.cpu1.icache.ReadReq_misses 471 # number of ReadReq misses -system.cpu1.icache.demand_misses 471 # number of demand (read+write) misses -system.cpu1.icache.overall_misses 471 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7203000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7203000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7203000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses 18341 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses 18341 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses 18341 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate 0.025680 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate 0.025680 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate 0.025680 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency 15292.993631 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency 15292.993631 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency 15292.993631 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 84.541118 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.165119 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.165119 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 17870 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 17870 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 17870 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 17870 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 17870 # number of overall hits +system.cpu1.icache.overall_hits::total 17870 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 471 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 471 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 471 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 471 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 471 # number of overall misses +system.cpu1.icache.overall_misses::total 471 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7203000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7203000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7203000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7203000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7203000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7203000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 18341 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 18341 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 18341 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 18341 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 18341 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 18341 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025680 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025680 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025680 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15292.993631 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15292.993631 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15292.993631 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -712,68 +778,90 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 44 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 44 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 427 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 427 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5374000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5374000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5374000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.023281 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate 0.023281 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate 0.023281 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12585.480094 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12585.480094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12585.480094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 427 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 427 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 427 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 427 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 427 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5374000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5374000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5374000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5374000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5374000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5374000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 18.588243 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 24.401572 # Cycle average of tags in use system.cpu1.dcache.total_refs 44082 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 1469.400000 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 24.401572 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -5.813330 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.047659 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::1 -0.011354 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 46660 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 37905 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits 84565 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 84565 # number of overall hits -system.cpu1.dcache.ReadReq_misses 478 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses 124 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses 52 # number of SwapReq misses -system.cpu1.dcache.demand_misses 602 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses 602 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 10261500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 2943000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency 1149500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency 13204500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 13204500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 47138 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 38029 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 85167 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 85167 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.010140 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate 0.003261 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.007068 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.007068 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency 21467.573222 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency 23733.870968 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency 22105.769231 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency 21934.385382 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 21934.385382 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 24.401572 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.047659 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.047659 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 46660 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 46660 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 37905 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 37905 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 84565 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 84565 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 84565 # number of overall hits +system.cpu1.dcache.overall_hits::total 84565 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 478 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 478 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 124 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 124 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 602 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 602 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 602 # number of overall misses +system.cpu1.dcache.overall_misses::total 602 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10261500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 10261500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2943000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2943000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1149500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 1149500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13204500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13204500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13204500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13204500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 47138 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 47138 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 38029 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 38029 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 85167 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 85167 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 85167 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 85167 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010140 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003261 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007068 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007068 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21467.573222 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23733.870968 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 22105.769231 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21934.385382 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21934.385382 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -782,36 +870,46 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 323 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 341 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 341 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 261 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 261 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2079000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1617000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency 993500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 3696000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 3696000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003288 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002787 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate 0.003065 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate 0.003065 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13412.903226 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15254.716981 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19105.769231 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14160.919540 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14160.919540 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu1.dcache.writebacks::total 1 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 18 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 18 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 341 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 341 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 261 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 261 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2079000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2079000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1617000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1617000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 993500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 993500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3696000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3696000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3696000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3696000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003288 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002787 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13412.903226 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15254.716981 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 19105.769231 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 174018 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -1029,6 +1127,7 @@ system.cpu2.iew.wb_rate 1.290855 # in system.cpu2.iew.wb_fanout 0.966435 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitCommittedInsts 256708 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 256708 # The number of committed instructions system.cpu2.commit.commitSquashedInsts 10074 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 5686 # The number of times commit has been forced to stall to communicate backwards system.cpu2.commit.branchMispredicts 1149 # The number of times a branch was mispredicted @@ -1049,7 +1148,8 @@ system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::total 160519 # Number of insts commited each cycle -system.cpu2.commit.count 256708 # Number of instructions committed +system.cpu2.commit.committedInsts 256708 # Number of instructions committed +system.cpu2.commit.committedOps 256708 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed system.cpu2.commit.refs 108759 # Number of memory references committed system.cpu2.commit.loads 73984 # Number of loads committed @@ -1066,6 +1166,7 @@ system.cpu2.timesIdled 232 # Nu system.cpu2.idleCycles 5048 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 34616 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu2.committedInsts 215254 # Number of Instructions Simulated +system.cpu2.committedOps 215254 # Number of Ops (including micro ops) Simulated system.cpu2.committedInsts_total 215254 # Number of Instructions Simulated system.cpu2.cpi 0.808431 # CPI: Cycles Per Instruction system.cpu2.cpi_total 0.808431 # CPI: Total CPI of All Threads @@ -1082,26 +1183,39 @@ system.cpu2.icache.total_refs 18578 # To system.cpu2.icache.sampled_refs 427 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 43.508197 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 85.227474 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.166460 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits 18578 # number of ReadReq hits -system.cpu2.icache.demand_hits 18578 # number of demand (read+write) hits -system.cpu2.icache.overall_hits 18578 # number of overall hits -system.cpu2.icache.ReadReq_misses 481 # number of ReadReq misses -system.cpu2.icache.demand_misses 481 # number of demand (read+write) misses -system.cpu2.icache.overall_misses 481 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency 10446500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency 10446500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency 10446500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses 19059 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses 19059 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses 19059 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate 0.025237 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate 0.025237 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate 0.025237 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency 21718.295218 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency 21718.295218 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency 21718.295218 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 85.227474 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.166460 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.166460 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 18578 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 18578 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 18578 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 18578 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 18578 # number of overall hits +system.cpu2.icache.overall_hits::total 18578 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 481 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 481 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 481 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 481 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 481 # number of overall misses +system.cpu2.icache.overall_misses::total 481 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 10446500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 10446500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 10446500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 10446500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 10446500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 10446500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19059 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19059 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19059 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19059 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19059 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19059 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.025237 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.025237 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.025237 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21718.295218 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1110,68 +1224,90 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses 427 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses 427 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.ReadReq_mshr_miss_latency 8026500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency 8026500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency 8026500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.022404 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate 0.022404 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate 0.022404 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18797.423888 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 18797.423888 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 18797.423888 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 54 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 54 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 54 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 54 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 54 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 427 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 427 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 427 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 427 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 427 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8026500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 8026500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8026500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 8026500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8026500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 8026500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 19.370911 # Cycle average of tags in use +system.cpu2.dcache.tagsinuse 26.582846 # Cycle average of tags in use system.cpu2.dcache.total_refs 40686 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 1356.200000 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 26.582846 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -7.211935 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.051920 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::1 -0.014086 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 43569 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 34581 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits 78150 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 78150 # number of overall hits -system.cpu2.dcache.ReadReq_misses 459 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses 120 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses 61 # number of SwapReq misses -system.cpu2.dcache.demand_misses 579 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses 579 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency 10999500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency 2980500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency 1343500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency 13980000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 13980000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 44028 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 34701 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 78729 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 78729 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate 0.010425 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate 0.003458 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate 0.824324 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.007354 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.007354 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency 23964.052288 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency 24837.500000 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency 22024.590164 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency 24145.077720 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 24145.077720 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 26.582846 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.051920 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.051920 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 43569 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 43569 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 34581 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 34581 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 78150 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 78150 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 78150 # number of overall hits +system.cpu2.dcache.overall_hits::total 78150 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 459 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 459 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 120 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 120 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 61 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 61 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 579 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 579 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 579 # number of overall misses +system.cpu2.dcache.overall_misses::total 579 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10999500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 10999500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2980500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2980500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1343500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 1343500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 13980000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 13980000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 13980000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 13980000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 44028 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 44028 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 34701 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 34701 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 74 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 78729 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 78729 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 78729 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 78729 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010425 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003458 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.824324 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007354 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007354 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23964.052288 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24837.500000 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 22024.590164 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1180,36 +1316,46 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits 315 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits 315 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses 61 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 2380000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency 1660000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency 1160500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency 4040000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 4040000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003679 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002939 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.824324 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate 0.003353 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate 0.003353 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14691.358025 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16274.509804 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19024.590164 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu2.dcache.writebacks::total 1 # number of writebacks +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 297 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 297 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 18 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 18 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 315 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 315 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 61 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 61 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 264 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 264 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2380000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2380000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1660000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1660000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1160500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1160500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4040000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4040000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4040000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4040000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002939 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.824324 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14691.358025 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16274.509804 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 19024.590164 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173752 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -1427,6 +1573,7 @@ system.cpu3.iew.wb_rate 1.121909 # in system.cpu3.iew.wb_fanout 0.961453 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu3.commit.commitCommittedInsts 222296 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 222296 # The number of committed instructions system.cpu3.commit.commitSquashedInsts 9409 # The number of squashed insts skipped by commit system.cpu3.commit.commitNonSpecStalls 7641 # The number of times commit has been forced to stall to communicate backwards system.cpu3.commit.branchMispredicts 1065 # The number of times a branch was mispredicted @@ -1447,7 +1594,8 @@ system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::total 162652 # Number of insts commited each cycle -system.cpu3.commit.count 222296 # Number of instructions committed +system.cpu3.commit.committedInsts 222296 # Number of instructions committed +system.cpu3.commit.committedOps 222296 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed system.cpu3.commit.refs 89597 # Number of memory references committed system.cpu3.commit.loads 61865 # Number of loads committed @@ -1464,6 +1612,7 @@ system.cpu3.timesIdled 234 # Nu system.cpu3.idleCycles 2770 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 34882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu3.committedInsts 183965 # Number of Instructions Simulated +system.cpu3.committedOps 183965 # Number of Ops (including micro ops) Simulated system.cpu3.committedInsts_total 183965 # Number of Instructions Simulated system.cpu3.cpi 0.944484 # CPI: Cycles Per Instruction system.cpu3.cpi_total 0.944484 # CPI: Total CPI of All Threads @@ -1480,26 +1629,39 @@ system.cpu3.icache.total_refs 22493 # To system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 52.800469 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 80.006059 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.156262 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits 22493 # number of ReadReq hits -system.cpu3.icache.demand_hits 22493 # number of demand (read+write) hits -system.cpu3.icache.overall_hits 22493 # number of overall hits -system.cpu3.icache.ReadReq_misses 466 # number of ReadReq misses -system.cpu3.icache.demand_misses 466 # number of demand (read+write) misses -system.cpu3.icache.overall_misses 466 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency 6527000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency 6527000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency 6527000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses 22959 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses 22959 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses 22959 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate 0.020297 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate 0.020297 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate 0.020297 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency 14006.437768 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency 14006.437768 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency 14006.437768 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 80.006059 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.156262 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.156262 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 22493 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 22493 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 22493 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 22493 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 22493 # number of overall hits +system.cpu3.icache.overall_hits::total 22493 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 466 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 466 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 466 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 466 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 466 # number of overall misses +system.cpu3.icache.overall_misses::total 466 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6527000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6527000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6527000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6527000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6527000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6527000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 22959 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 22959 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 22959 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 22959 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 22959 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 22959 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020297 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020297 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020297 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14006.437768 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1508,68 +1670,90 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits 40 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses 426 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.ReadReq_mshr_miss_latency 4833500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency 4833500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency 4833500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.018555 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate 0.018555 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate 0.018555 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11346.244131 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11346.244131 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11346.244131 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 40 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 40 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 40 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 40 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 40 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 426 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 426 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 426 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 426 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 426 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4833500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4833500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4833500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4833500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4833500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4833500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 13.455705 # Cycle average of tags in use +system.cpu3.dcache.tagsinuse 23.407477 # Cycle average of tags in use system.cpu3.dcache.total_refs 33584 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.avg_refs 1158.068966 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::0 23.407477 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -9.951772 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.045718 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::1 -0.019437 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 38412 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 27537 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits 65949 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 65949 # number of overall hits -system.cpu3.dcache.ReadReq_misses 448 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses 125 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses 56 # number of SwapReq misses -system.cpu3.dcache.demand_misses 573 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses 573 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency 9358000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency 2911000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency 1350500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency 12269000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency 12269000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 38860 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 27662 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 66522 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 66522 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate 0.011529 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate 0.004519 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate 0.800000 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate 0.008614 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate 0.008614 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency 20888.392857 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency 23288 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency 24116.071429 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency 21411.867365 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency 21411.867365 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 23.407477 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.045718 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.045718 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 38412 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 38412 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 27537 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 27537 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 65949 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 65949 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 65949 # number of overall hits +system.cpu3.dcache.overall_hits::total 65949 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 448 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 448 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 125 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 125 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 573 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 573 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 573 # number of overall misses +system.cpu3.dcache.overall_misses::total 573 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9358000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 9358000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2911000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2911000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1350500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 1350500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 12269000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 12269000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 12269000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 12269000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 38860 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 38860 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 27662 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 27662 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 66522 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 66522 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 66522 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 66522 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011529 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004519 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.800000 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008614 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008614 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20888.392857 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23288 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 24116.071429 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 21411.867365 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 21411.867365 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1578,36 +1762,46 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_hits 279 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits 296 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses 169 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses 56 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses 277 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 2218000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency 1624500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency 1182500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency 3842500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency 3842500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004349 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003904 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.800000 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate 0.004164 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate 0.004164 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13124.260355 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15041.666667 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 21116.071429 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 13871.841155 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 13871.841155 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu3.dcache.writebacks::total 1 # number of writebacks +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 279 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 17 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 17 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 296 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 296 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 169 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 277 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 277 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2218000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2218000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1624500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1624500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1182500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1182500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3842500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3842500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3842500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3842500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004349 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003904 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004164 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004164 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13124.260355 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15041.666667 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 21116.071429 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13871.841155 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13871.841155 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 428.231635 # Cycle average of tags in use @@ -1615,142 +1809,231 @@ system.l2c.total_refs 1446 # To system.l2c.sampled_refs 527 # Sample count of references to valid blocks. system.l2c.avg_refs 2.743833 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 347.174574 # Average occupied blocks per context -system.l2c.occ_blocks::1 11.269547 # Average occupied blocks per context -system.l2c.occ_blocks::2 63.254631 # Average occupied blocks per context -system.l2c.occ_blocks::3 1.567259 # Average occupied blocks per context -system.l2c.occ_blocks::4 4.965624 # Average occupied blocks per context -system.l2c.occ_percent::0 0.005297 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.000172 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000965 # Average percentage of cache occupancy -system.l2c.occ_percent::3 0.000024 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.000076 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 233 # number of ReadReq hits -system.l2c.ReadReq_hits::1 424 # number of ReadReq hits -system.l2c.ReadReq_hits::2 356 # number of ReadReq hits -system.l2c.ReadReq_hits::3 436 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 4.965624 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 287.776309 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.398265 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 10.494682 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 0.774865 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 57.571117 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 5.683514 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 0.828706 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.738553 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000076 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004391 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000906 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000160 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000878 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000087 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006534 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 228 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 12 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 7 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 424 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 12 # number of ReadReq hits system.l2c.ReadReq_hits::total 1449 # number of ReadReq hits -system.l2c.Writeback_hits::0 9 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::0 233 # number of demand (read+write) hits -system.l2c.demand_hits::1 424 # number of demand (read+write) hits -system.l2c.demand_hits::2 356 # number of demand (read+write) hits -system.l2c.demand_hits::3 436 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 228 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 7 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 12 # number of demand (read+write) hits system.l2c.demand_hits::total 1449 # number of demand (read+write) hits -system.l2c.overall_hits::0 233 # number of overall hits -system.l2c.overall_hits::1 424 # number of overall hits -system.l2c.overall_hits::2 356 # number of overall hits -system.l2c.overall_hits::3 436 # number of overall hits +system.l2c.overall_hits::cpu0.inst 228 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 412 # number of overall hits +system.l2c.overall_hits::cpu1.data 12 # number of overall hits +system.l2c.overall_hits::cpu2.inst 349 # number of overall hits +system.l2c.overall_hits::cpu2.data 7 # number of overall hits +system.l2c.overall_hits::cpu3.inst 424 # number of overall hits +system.l2c.overall_hits::cpu3.data 12 # number of overall hits system.l2c.overall_hits::total 1449 # number of overall hits -system.l2c.ReadReq_misses::0 429 # number of ReadReq misses -system.l2c.ReadReq_misses::1 16 # number of ReadReq misses -system.l2c.ReadReq_misses::2 85 # number of ReadReq misses -system.l2c.ReadReq_misses::3 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 354 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 78 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 533 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::0 523 # number of demand (read+write) misses -system.l2c.demand_misses::1 28 # number of demand (read+write) misses -system.l2c.demand_misses::2 98 # number of demand (read+write) misses -system.l2c.demand_misses::3 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 354 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 78 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses system.l2c.demand_misses::total 664 # number of demand (read+write) misses -system.l2c.overall_misses::0 523 # number of overall misses -system.l2c.overall_misses::1 28 # number of overall misses -system.l2c.overall_misses::2 98 # number of overall misses -system.l2c.overall_misses::3 15 # number of overall misses +system.l2c.overall_misses::cpu0.inst 354 # number of overall misses +system.l2c.overall_misses::cpu0.data 169 # number of overall misses +system.l2c.overall_misses::cpu1.inst 15 # number of overall misses +system.l2c.overall_misses::cpu1.data 13 # number of overall misses +system.l2c.overall_misses::cpu2.inst 78 # number of overall misses +system.l2c.overall_misses::cpu2.data 20 # number of overall misses +system.l2c.overall_misses::cpu3.inst 2 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 664 # number of overall misses -system.l2c.ReadReq_miss_latency 27701000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 157500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6878000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 34579000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 34579000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 662 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 440 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 441 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 439 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu0.inst 18441500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 3931500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 745000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 52500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 4016500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 365500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 96000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 27701000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 52500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 52500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3.data 52500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 157500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4940000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 627500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 683000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 627500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6878000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 18441500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8871500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 745000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 680000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 4016500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1048500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 96000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 680000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 34579000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 18441500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8871500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 745000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 680000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 4016500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1048500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 96000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 680000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 34579000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 582 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 14 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 426 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 24 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 22 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 22 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 22 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 756 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 452 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 454 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 451 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 582 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 426 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2113 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 756 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 452 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 454 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 451 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 582 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 426 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2113 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.648036 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.036364 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.192744 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.006834 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.883977 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.875000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 3.875000 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.691799 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.061947 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.215859 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.033259 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 1.002864 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.691799 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.061947 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.215859 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.033259 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 1.002864 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 64571.095571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 1731312.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 325894.117647 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 9233666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 11355444.379885 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 7500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 7159.090909 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 7159.090909 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 7159.090909 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28977.272727 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 73170.212766 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 573166.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 529076.923077 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 573166.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1748580.469176 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 66116.634799 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1234964.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 352846.938776 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 2305266.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3959194.525956 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 66116.634799 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1234964.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 352846.938776 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 2305266.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3959194.525956 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.inst 0.608247 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.035129 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.076923 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.182670 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.004695 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.076923 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.608247 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.035129 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.520000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.182670 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.004695 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.520000 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.608247 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.035129 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.520000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.182670 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.004695 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.520000 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52094.632768 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52420 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49666.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51493.589744 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 52214.285714 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 48000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2386.363636 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 2386.363636 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2386.363636 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52553.191489 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52538.461538 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52094.632768 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52494.082840 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 49666.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 51493.589744 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52425 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 48000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52094.632768 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52494.082840 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 49666.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 51493.589744 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52425 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 48000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1759,55 +2042,159 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 0 # number of writebacks -system.l2c.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 8 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 8 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 525 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 87 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 656 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 656 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 20993500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 3480000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5279000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 26272500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 26272500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.793051 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 1.193182 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 1.190476 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 1.195900 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 4.372609 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 3.625000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 3.954545 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 3.954545 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 3.954545 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 15.488636 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.867725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.451327 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.444934 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.454545 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 5.218532 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.867725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.451327 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.444934 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.454545 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 5.218532 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 39987.619048 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40049.542683 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40049.542683 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 353 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 14 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 73 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 525 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 22 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 22 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 22 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 87 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 353 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 656 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 353 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 73 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 656 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14091500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3019000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 561000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2922000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 20993500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 840000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3480000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3792000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 524500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5279000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 14091500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6811000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 561000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 521000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 2922000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 804500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 26272500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 14091500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6811000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 561000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 521000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 2922000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 804500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 26272500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40253.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40340.425532 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40083.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40346.153846 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |