diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
| commit | 9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch) | |
| tree | fab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | |
| parent | 009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff) | |
| download | gem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz | |
stats: update stats for previous changes.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 1544 |
1 files changed, 772 insertions, 772 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index bb0098d76..a08676b4f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 104830500 # Number of ticks simulated -final_tick 104830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 104832500 # Number of ticks simulated +final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112424 # Simulator instruction rate (inst/s) -host_op_rate 112424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11388036 # Simulator tick rate (ticks/s) -host_mem_usage 275264 # Number of bytes of host memory used -host_seconds 9.21 # Real time elapsed on the host -sim_insts 1034897 # Number of instructions simulated -sim_ops 1034897 # Number of ops (including micro ops) simulated +host_inst_rate 49068 # Simulator instruction rate (inst/s) +host_op_rate 49068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4970400 # Simulator tick rate (ticks/s) +host_mem_usage 237836 # Number of bytes of host memory used +host_seconds 21.09 # Real time elapsed on the host +sim_insts 1034907 # Number of instructions simulated +sim_ops 1034907 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory @@ -34,29 +34,29 @@ system.physmem.num_reads::cpu2.data 13 # Nu system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 658 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 217341327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 102565570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49451257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 12210187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1831528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7936621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2442037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7936621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 401715150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 217341327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49451257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1831528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2442037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271066150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 217341327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 102565570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49451257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 12210187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1831528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7936621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2442037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7936621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401715150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 217337181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 102563613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49450314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 12209954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1831493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7936470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2441991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7936470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 401707486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 217337181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49450314 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1831493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2441991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 271060978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 217337181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 102563613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49450314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 12209954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1831493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7936470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2441991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7936470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401707486 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 659 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady @@ -100,7 +100,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 104802500 # Total gap between requests +system.physmem.totGap 104804500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -194,17 +194,17 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2987155 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17761155 # Sum of mem lat for all requests +system.physmem.totQLat 2976655 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 17750655 # Sum of mem lat for all requests system.physmem.totBusLat 2636000 # Total cycles spent in databus access system.physmem.totBankLat 12138000 # Total cycles spent in bank access -system.physmem.avgQLat 4532.86 # Average queueing delay per request +system.physmem.avgQLat 4516.93 # Average queueing delay per request system.physmem.avgBankLat 18418.82 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26951.68 # Average memory access latency -system.physmem.avgRdBW 401.72 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26935.74 # Average memory access latency +system.physmem.avgRdBW 401.71 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 401.72 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 401.71 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.51 # Data bus utilization in percentage @@ -214,9 +214,9 @@ system.physmem.readRowHits 506 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 159032.63 # Average gap between requests +system.physmem.avgGap 159035.66 # Average gap between requests system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 209662 # number of cpu cycles simulated +system.cpu0.numCycles 209666 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.BPredUnit.lookups 82004 # Number of BP lookups @@ -227,38 +227,38 @@ system.cpu0.BPredUnit.BTBHits 77227 # Nu system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.BPredUnit.usedRAS 516 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16907 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12545 # Number of cycles fetch has spent blocked +system.cpu0.fetch.BlockedCycles 12561 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 192893 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.523176 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215866 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 483 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 192912 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.522928 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215898 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33256 17.24% 17.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79042 40.98% 58.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33275 17.25% 17.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79042 40.97% 58.22% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 987 0.51% 59.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 987 0.51% 59.04% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 75108 38.94% 98.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 578 0.30% 98.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 75108 38.93% 98.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 578 0.30% 98.51% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 192893 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391125 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.321370 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::total 192912 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391117 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.321325 # Number of inst fetches per cycle system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14000 # Number of cycles decode is blocked +system.cpu0.decode.BlockedCycles 14019 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing @@ -266,7 +266,7 @@ system.cpu0.decode.DecodedInsts 483730 # Nu system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12765 # count of cycles rename stalled for serializing inst +system.cpu0.rename.serializeStallCycles 12784 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename @@ -279,35 +279,35 @@ system.cpu0.rename.CommittedMaps 315995 # Nu system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3587 # count of insts added to the skid buffer +system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores. system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 399521 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10786 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9496 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqInstsIssued 399553 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10756 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9264 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 192893 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.071205 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.088777 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 192912 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.071167 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.088883 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 32269 16.73% 16.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4844 2.51% 19.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 76822 39.83% 59.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76327 39.57% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1582 0.82% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 687 0.36% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 32280 16.73% 16.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4842 2.51% 19.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 76824 39.82% 59.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76328 39.57% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1590 0.82% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 686 0.36% 99.81% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 192893 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 192912 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available @@ -343,50 +343,50 @@ system.cpu0.iq.fu_full::MemWrite 114 50.89% 100.00% # at system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 169105 42.33% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 153283 38.37% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77133 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 169105 42.32% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 153315 38.37% 80.70% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77133 19.30% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 399521 # Type of FU issued -system.cpu0.iq.rate 1.905548 # Inst issue rate +system.cpu0.iq.FU_type_0::total 399553 # Type of FU issued +system.cpu0.iq.rate 1.905664 # Inst issue rate system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 992323 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 413903 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 397700 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_reads 992374 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 413873 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 397773 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 399745 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 399777 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -413,43 +413,43 @@ system.cpu0.iew.memOrderViolationEvents 44 # Nu system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 398429 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 152970 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1092 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 398478 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 152978 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1075 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 75469 # number of nop insts executed -system.cpu0.iew.exec_refs 229968 # number of memory reference insts executed +system.cpu0.iew.exec_refs 230010 # number of memory reference insts executed system.cpu0.iew.exec_branches 79152 # Number of branches executed -system.cpu0.iew.exec_stores 76998 # Number of stores executed -system.cpu0.iew.exec_rate 1.900340 # Inst execution rate -system.cpu0.iew.wb_sent 398024 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 397700 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 235727 # num instructions producing a value -system.cpu0.iew.wb_consumers 238246 # num instructions consuming a value +system.cpu0.iew.exec_stores 77032 # Number of stores executed +system.cpu0.iew.exec_rate 1.900537 # Inst execution rate +system.cpu0.iew.wb_sent 398087 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 397773 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 235728 # num instructions producing a value +system.cpu0.iew.wb_consumers 238247 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.896863 # insts written-back per cycle +system.cpu0.iew.wb_rate 1.897175 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 190472 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.448360 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.135276 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 190474 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.448334 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.135304 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32802 17.22% 17.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32805 17.22% 17.22% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2340 1.23% 59.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2339 1.23% 59.79% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 74330 39.02% 99.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 74329 39.02% 99.46% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.83% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 190472 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 190474 # Number of insts commited each cycle system.cpu0.commit.committedInsts 466344 # Number of instructions committed system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed @@ -462,31 +462,31 @@ system.cpu0.commit.int_insts 314326 # Nu system.cpu0.commit.function_calls 223 # Number of function calls committed. system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 667502 # The number of ROB reads +system.cpu0.rob.rob_reads 667504 # The number of ROB reads system.cpu0.rob.rob_writes 959472 # The number of ROB writes system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 16769 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.idleCycles 16754 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.committedInsts 391341 # Number of Instructions Simulated system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated -system.cpu0.cpi 0.535753 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535753 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.866533 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.866533 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 712669 # number of integer regfile reads -system.cpu0.int_regfile_writes 321346 # number of integer regfile writes +system.cpu0.cpi 0.535763 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.535763 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.866497 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.866497 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 712766 # number of integer regfile reads +system.cpu0.int_regfile_writes 321389 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 231752 # number of misc regfile reads +system.cpu0.misc_regfile_reads 231850 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.replacements 297 # number of replacements -system.cpu0.icache.tagsinuse 245.466325 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 245.463196 # Cycle average of tags in use system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 245.466325 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.479426 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.479426 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 245.463196 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.479420 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.479420 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits @@ -499,12 +499,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 742 # system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses system.cpu0.icache.overall_misses::total 742 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25612000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 25612000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 25612000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 25612000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 25612000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 25612000 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25596000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 25596000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 25596000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 25596000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 25596000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 25596000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses @@ -517,12 +517,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126384 system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34517.520216 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 34517.520216 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 34517.520216 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 34517.520216 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34495.956873 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 34495.956873 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 34495.956873 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 34495.956873 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,44 +543,44 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20478500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20478500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20478500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20478500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20478500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20478500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20466000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 20466000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20466000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 20466000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20466000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 20466000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34827.380952 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34806.122449 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 143.868426 # Cycle average of tags in use -system.cpu0.dcache.total_refs 153554 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 143.865824 # Cycle average of tags in use +system.cpu0.dcache.total_refs 153562 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 903.258824 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 903.305882 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 143.868426 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.280993 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.280993 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 77923 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77923 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 143.865824 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.280988 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.280988 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 77931 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77931 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 75708 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 75708 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153631 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153631 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153631 # number of overall hits -system.cpu0.dcache.overall_hits::total 153631 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 153639 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153639 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153639 # number of overall hits +system.cpu0.dcache.overall_hits::total 153639 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses @@ -593,26 +593,26 @@ system.cpu0.dcache.overall_misses::cpu0.data 1021 system.cpu0.dcache.overall_misses::total 1021 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22991498 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 22991498 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23032998 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 23032998 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34076998 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34076998 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34076998 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34076998 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78394 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78394 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 34118498 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34118498 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34118498 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34118498 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78402 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78402 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154652 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154652 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154652 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154652 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006008 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006008 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 154660 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 154660 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154660 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154660 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006007 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006007 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses @@ -623,14 +623,14 @@ system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006602 system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41802.723636 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41802.723636 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41878.178182 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41878.178182 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33376.099902 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33376.099902 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33416.746327 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33416.746327 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -661,16 +661,16 @@ system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5605500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5605500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5613000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5613000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10499500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10499500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002475 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002475 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10507000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10507000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10507000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10507000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002474 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002474 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses @@ -681,98 +681,98 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002328 system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33768.072289 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33768.072289 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33813.253012 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33813.253012 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 174084 # number of cpu cycles simulated +system.cpu1.numCycles 174086 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 52904 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 50238 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 52905 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 50239 # Number of conditional branches predicted system.cpu1.BPredUnit.condIncorrect 1268 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 46828 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 46138 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 46829 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 46139 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.BPredUnit.usedRAS 659 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 297398 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52904 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46797 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 103835 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46798 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 103837 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 29305 # Number of cycles fetch has spent blocked +system.cpu1.fetch.BlockedCycles 29303 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6116 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.NoActiveThreadStallCycles 6120 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 169680 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.752699 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.165176 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::samples 169684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.752693 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.165174 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65845 38.81% 38.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52566 30.98% 69.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 65847 38.81% 38.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52567 30.98% 69.79% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 36566 21.55% 96.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 36567 21.55% 96.93% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 169680 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.303899 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.708359 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::total 169684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.303902 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.708374 # Number of inst fetches per cycle system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 26240 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 98388 # Number of cycles decode is running +system.cpu1.decode.BlockedCycles 26238 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 98390 # Number of cycles decode is running system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 293925 # Number of instructions handled by decode +system.cpu1.decode.DecodedInsts 293931 # Number of instructions handled by decode system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11858 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 94082 # Number of cycles rename is running +system.cpu1.rename.serializeStallCycles 11856 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 94084 # Number of cycles rename is running system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 291891 # Number of instructions processed by rename +system.cpu1.rename.RenamedInsts 291897 # Number of instructions processed by rename system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 205019 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 562522 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 562522 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 192184 # Number of HB maps that are committed +system.cpu1.rename.RenamedOperands 205023 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 562534 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 562534 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 192188 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 83196 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 39822 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 39557 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 34785 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 242788 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.memDep0.insertedLoads 83198 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 39823 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 39558 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 34786 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 242793 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 244431 # Number of instructions issued +system.cpu1.iq.iqInstsIssued 244436 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10770 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedInstsExamined 10755 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10381 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 169680 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.440541 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::samples 169684 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.440537 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 63213 37.25% 37.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 63215 37.25% 37.25% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 39930 23.53% 73.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 40650 23.96% 97.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 39931 23.53% 73.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 40651 23.96% 97.13% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle @@ -781,7 +781,7 @@ system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 169680 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 169684 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available @@ -817,7 +817,7 @@ system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # at system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 118248 48.38% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 118250 48.38% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued @@ -846,23 +846,23 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.38% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 87044 35.61% 83.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 39139 16.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 87046 35.61% 83.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 39140 16.01% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 244431 # Type of FU issued -system.cpu1.iq.rate 1.404098 # Inst issue rate +system.cpu1.iq.FU_type_0::total 244436 # Type of FU issued +system.cpu1.iq.rate 1.404111 # Inst issue rate system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 658925 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 259421 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 242675 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_reads 658939 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 259411 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 242683 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 244726 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 244731 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 34549 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 34550 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed @@ -876,10 +876,10 @@ system.cpu1.iew.iewIdleCycles 0 # Nu system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 289058 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispatchedInsts 289064 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 83196 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 39822 # Number of dispatched store instructions +system.cpu1.iew.iewDispLoadInsts 83198 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 39823 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -887,81 +887,81 @@ system.cpu1.iew.memOrderViolationEvents 45 # Nu system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 243269 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 82226 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1162 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 243277 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 82228 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1159 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 40452 # number of nop insts executed -system.cpu1.iew.exec_refs 121286 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49717 # Number of branches executed -system.cpu1.iew.exec_stores 39060 # Number of stores executed -system.cpu1.iew.exec_rate 1.397423 # Inst execution rate -system.cpu1.iew.wb_sent 242942 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 242675 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 138073 # num instructions producing a value -system.cpu1.iew.wb_consumers 142763 # num instructions consuming a value +system.cpu1.iew.exec_nop 40453 # number of nop insts executed +system.cpu1.iew.exec_refs 121292 # number of memory reference insts executed +system.cpu1.iew.exec_branches 49718 # Number of branches executed +system.cpu1.iew.exec_stores 39064 # Number of stores executed +system.cpu1.iew.exec_rate 1.397453 # Inst execution rate +system.cpu1.iew.wb_sent 242950 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 242683 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 138076 # num instructions producing a value +system.cpu1.iew.wb_consumers 142766 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.394011 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.967148 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.394041 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.967149 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161217 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.716302 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.045846 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::samples 161216 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.716349 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.045856 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 62248 38.61% 38.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47764 29.63% 68.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 62245 38.61% 38.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 47765 29.63% 68.24% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.82% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 35062 21.75% 98.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 35063 21.75% 98.55% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161217 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 276697 # Number of instructions committed -system.cpu1.commit.committedOps 276697 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161216 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 276703 # Number of instructions committed +system.cpu1.commit.committedOps 276703 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 119191 # Number of memory references committed -system.cpu1.commit.loads 80801 # Number of loads committed +system.cpu1.commit.refs 119194 # Number of memory references committed +system.cpu1.commit.loads 80803 # Number of loads committed system.cpu1.commit.membars 4532 # Number of memory barriers committed -system.cpu1.commit.branches 48885 # Number of branches committed +system.cpu1.commit.branches 48886 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 190199 # Number of committed integer instructions. +system.cpu1.commit.int_insts 190203 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 448868 # The number of ROB reads -system.cpu1.rob.rob_writes 580470 # The number of ROB writes +system.cpu1.rob.rob_reads 448873 # The number of ROB reads +system.cpu1.rob.rob_writes 580482 # The number of ROB writes system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4404 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 232489 # Number of Instructions Simulated -system.cpu1.committedOps 232489 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 232489 # Number of Instructions Simulated -system.cpu1.cpi 0.748784 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.748784 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.335499 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.335499 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 422509 # number of integer regfile reads -system.cpu1.int_regfile_writes 197149 # number of integer regfile writes +system.cpu1.idleCycles 4402 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 232494 # Number of Instructions Simulated +system.cpu1.committedOps 232494 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 232494 # Number of Instructions Simulated +system.cpu1.cpi 0.748776 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.748776 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.335512 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.335512 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 422524 # number of integer regfile reads +system.cpu1.int_regfile_writes 197153 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 122869 # number of misc regfile reads +system.cpu1.misc_regfile_reads 122878 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 85.783317 # Cycle average of tags in use +system.cpu1.icache.tagsinuse 85.782711 # Cycle average of tags in use system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 85.783317 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.167546 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.167546 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::cpu1.inst 85.782711 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.167544 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.167544 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits @@ -974,12 +974,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 482 # system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses system.cpu1.icache.overall_misses::total 482 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9898500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9898500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9898500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9898500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9898500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9898500 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9897000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9897000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9897000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9897000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9897000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9897000 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses @@ -992,12 +992,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025831 system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20536.307054 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20536.307054 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20536.307054 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20536.307054 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20533.195021 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20533.195021 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20533.195021 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20533.195021 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1018,44 +1018,44 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8055000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8055000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8055000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8055000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8055000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8055000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8054000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8054000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8054000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8054000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8054000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8054000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022776 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.022776 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.022776 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18952.941176 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18950.588235 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.224773 # Cycle average of tags in use -system.cpu1.dcache.total_refs 44406 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.224520 # Cycle average of tags in use +system.cpu1.dcache.total_refs 44407 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1585.928571 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1585.964286 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.224773 # Average occupied blocks per requestor +system.cpu1.dcache.occ_blocks::cpu1.data 27.224520 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 47254 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 47254 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 38186 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 38186 # number of WriteReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 47255 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 47255 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 38187 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 38187 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 85440 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 85440 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 85440 # number of overall hits -system.cpu1.dcache.overall_hits::total 85440 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 85442 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 85442 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 85442 # number of overall hits +system.cpu1.dcache.overall_hits::total 85442 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 407 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 407 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses @@ -1068,24 +1068,24 @@ system.cpu1.dcache.overall_misses::cpu1.data 544 system.cpu1.dcache.overall_misses::total 544 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6159500 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 6159500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2649500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2649500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2641000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2641000 # number of WriteReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 528500 # number of SwapReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::total 528500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8809000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8809000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8809000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8809000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 47661 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 47661 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 38323 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 38323 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.demand_miss_latency::cpu1.data 8800500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8800500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8800500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8800500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 47662 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 47662 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 38324 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 38324 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 85984 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 85984 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 85984 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 85984 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 85986 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 85986 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 85986 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 85986 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008539 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.008539 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003575 # miss rate for WriteReq accesses @@ -1098,14 +1098,14 @@ system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006327 system.cpu1.dcache.overall_miss_rate::total 0.006327 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19339.416058 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19339.416058 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19277.372263 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19277.372263 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9971.698113 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::total 9971.698113 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16193.014706 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16193.014706 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16177.389706 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16177.389706 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1134,14 +1134,14 @@ system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1383500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1383500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1381000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1381000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2913500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2913500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2913500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2913500 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2911000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2911000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2911000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2911000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses @@ -1154,16 +1154,16 @@ system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003024 system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13176.190476 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13176.190476 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13152.380952 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13152.380952 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 173759 # number of cpu cycles simulated +system.cpu2.numCycles 173761 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.BPredUnit.lookups 43658 # Number of BP lookups @@ -1180,17 +1180,17 @@ system.cpu2.fetch.Branches 43658 # Nu system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 41179 # Number of cycles fetch has spent blocked +system.cpu2.fetch.BlockedCycles 41181 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6107 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.NoActiveThreadStallCycles 6111 # Number of stall cycles due to no active thread to fetch from system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 172022 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.367924 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.005612 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 172028 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.367876 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.005593 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 83795 48.71% 48.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 83801 48.71% 48.71% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total) @@ -1202,11 +1202,11 @@ system.cpu2.fetch.rateDist::8 3307 1.92% 100.00% # Nu system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 172022 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.251256 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.354249 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::total 172028 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.251253 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.354234 # Number of inst fetches per cycle system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 35177 # Number of cycles decode is blocked +system.cpu2.decode.BlockedCycles 35179 # Number of cycles decode is blocked system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing @@ -1214,7 +1214,7 @@ system.cpu2.decode.DecodedInsts 231751 # Nu system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11999 # count of cycles rename stalled for serializing inst +system.cpu2.rename.serializeStallCycles 12001 # count of cycles rename stalled for serializing inst system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename @@ -1236,14 +1236,14 @@ system.cpu2.iq.iqInstsAdded 186544 # Nu system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10969 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedInstsExamined 11059 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10957 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 172022 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.110277 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.273783 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::samples 172028 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.110238 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.273778 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 81441 47.34% 47.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 81447 47.35% 47.35% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle @@ -1255,7 +1255,7 @@ system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Nu system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 172022 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172028 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available @@ -1325,12 +1325,12 @@ system.cpu2.iq.FU_type_0::MemWrite 26665 13.96% 100.00% # Ty system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued -system.cpu2.iq.rate 1.099178 # Inst issue rate +system.cpu2.iq.rate 1.099165 # Inst issue rate system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 554402 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 206628 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 189208 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.int_inst_queue_reads 554408 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 206613 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 189211 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses @@ -1361,31 +1361,31 @@ system.cpu2.iew.memOrderViolationEvents 47 # Nu system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 189816 # Number of executed instructions +system.cpu2.iew.iewExecutedInsts 189819 # Number of executed instructions system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecSquashedInsts 1173 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 31084 # number of nop insts executed -system.cpu2.iew.exec_refs 86812 # number of memory reference insts executed +system.cpu2.iew.exec_refs 86815 # number of memory reference insts executed system.cpu2.iew.exec_branches 40244 # Number of branches executed -system.cpu2.iew.exec_stores 26581 # Number of stores executed -system.cpu2.iew.exec_rate 1.092410 # Inst execution rate -system.cpu2.iew.wb_sent 189478 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 189208 # cumulative count of insts written-back +system.cpu2.iew.exec_stores 26584 # Number of stores executed +system.cpu2.iew.exec_rate 1.092414 # Inst execution rate +system.cpu2.iew.wb_sent 189481 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 189211 # cumulative count of insts written-back system.cpu2.iew.wb_producers 103581 # num instructions producing a value system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.088911 # insts written-back per cycle +system.cpu2.iew.wb_rate 1.088915 # insts written-back per cycle system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 163490 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.308153 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.875243 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::samples 163491 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.308145 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.875240 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 83402 51.01% 51.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 83403 51.01% 51.01% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle @@ -1397,7 +1397,7 @@ system.cpu2.commit.committed_per_cycle::8 815 0.50% 100.00% # N system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 163490 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 163491 # Number of insts commited each cycle system.cpu2.commit.committedInsts 213870 # Number of instructions committed system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed @@ -1410,30 +1410,30 @@ system.cpu2.commit.int_insts 146274 # Nu system.cpu2.commit.function_calls 322 # Number of function calls committed. system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 388659 # The number of ROB reads +system.cpu2.rob.rob_reads 388660 # The number of ROB reads system.cpu2.rob.rob_writes 455572 # The number of ROB writes system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1737 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35901 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.idleCycles 1733 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu2.committedInsts 176057 # Number of Instructions Simulated system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated -system.cpu2.cpi 0.986947 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.986947 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.013225 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.013225 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 319017 # number of integer regfile reads +system.cpu2.cpi 0.986959 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.986959 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.013214 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.013214 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 319023 # number of integer regfile reads system.cpu2.int_regfile_writes 150022 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88362 # number of misc regfile reads +system.cpu2.misc_regfile_reads 88368 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.replacements 319 # number of replacements -system.cpu2.icache.tagsinuse 80.119670 # Cycle average of tags in use +system.cpu2.icache.tagsinuse 80.119801 # Cycle average of tags in use system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 80.119670 # Average occupied blocks per requestor +system.cpu2.icache.occ_blocks::cpu2.inst 80.119801 # Average occupied blocks per requestor system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits @@ -1448,12 +1448,12 @@ system.cpu2.icache.demand_misses::cpu2.inst 475 # system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses system.cpu2.icache.overall_misses::total 475 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6356500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6356500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6356500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6356500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6356500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6356500 # number of overall miss cycles +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6355000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6355000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6355000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6355000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6355000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6355000 # number of overall miss cycles system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses) system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses @@ -1466,12 +1466,12 @@ system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018969 system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13382.105263 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13382.105263 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13382.105263 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13382.105263 # average overall miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13378.947368 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13378.947368 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13378.947368 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13378.947368 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1492,32 +1492,32 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 429 system.cpu2.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 429 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5130000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5130000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5130000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5130000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5130000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5129000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5129000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5129000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5129000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5129000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5129000 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017132 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.017132 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.017132 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11958.041958 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11955.710956 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 24.750979 # Cycle average of tags in use +system.cpu2.dcache.tagsinuse 24.751060 # Cycle average of tags in use system.cpu2.dcache.total_refs 32016 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 1104 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.750979 # Average occupied blocks per requestor +system.cpu2.dcache.occ_blocks::cpu2.data 24.751060 # Average occupied blocks per requestor system.cpu2.dcache.occ_percent::cpu2.data 0.048342 # Average percentage of cache occupancy system.cpu2.dcache.occ_percent::total 0.048342 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 37788 # number of ReadReq hits @@ -1540,16 +1540,16 @@ system.cpu2.dcache.demand_misses::cpu2.data 530 # system.cpu2.dcache.demand_misses::total 530 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 530 # number of overall misses system.cpu2.dcache.overall_misses::total 530 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5135500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5135500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2343500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2343500 # number of WriteReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5134500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5134500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2352000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2352000 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 565000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 565000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 7479000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 7479000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 7479000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 7479000 # number of overall miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 7486500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 7486500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 7486500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 7486500 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 38185 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 38185 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 25814 # number of WriteReq accesses(hits+misses) @@ -1570,16 +1570,16 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008281 system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12935.768262 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 12935.768262 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17620.300752 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17620.300752 # average WriteReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12933.249370 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 12933.249370 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17684.210526 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 17684.210526 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14111.320755 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14111.320755 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14125.471698 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14125.471698 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1606,16 +1606,16 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1409000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1409000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1142500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1142500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1408000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1408000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1144000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1144000 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2551500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2551500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2551500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2551500 # number of overall MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2552000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2552000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2552000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2552000 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses @@ -1626,101 +1626,101 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004234 system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8288.235294 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8288.235294 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11311.881188 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11311.881188 # average WriteReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8282.352941 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8282.352941 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11326.732673 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11326.732673 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 173449 # number of cpu cycles simulated +system.cpu3.numCycles 173451 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 53688 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 50962 # Number of conditional branches predicted +system.cpu3.BPredUnit.lookups 53689 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 50963 # Number of conditional branches predicted system.cpu3.BPredUnit.condIncorrect 1276 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 47521 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 46771 # Number of BTB hits +system.cpu3.BPredUnit.BTBLookups 47522 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 46772 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.BPredUnit.usedRAS 661 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 301358 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 53688 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 47432 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 105431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 47433 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 105433 # Number of cycles fetch has run and was not squashing or blocked system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6125 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.NoActiveThreadStallCycles 6129 # Number of stall cycles due to no active thread to fetch from system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 172027 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.751806 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.162661 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::samples 172033 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.751780 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.162655 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 66596 38.71% 38.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 53420 31.05% 69.77% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 66600 38.71% 38.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 53421 31.05% 69.77% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 37059 21.54% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 37060 21.54% 96.99% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 172027 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.309532 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.737444 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::total 172033 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.309534 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.737459 # Number of inst fetches per cycle system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 99738 # Number of cycles decode is running +system.cpu3.decode.RunCycles 99740 # Number of cycles decode is running system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 297869 # Number of instructions handled by decode +system.cpu3.decode.DecodedInsts 297875 # Number of instructions handled by decode system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 95158 # Number of cycles rename is running +system.cpu3.rename.RunCycles 95160 # Number of cycles rename is running system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 295495 # Number of instructions processed by rename +system.cpu3.rename.RenamedInsts 295501 # Number of instructions processed by rename system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 206972 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 568769 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 568769 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 194051 # Number of HB maps that are committed +system.cpu3.rename.RenamedOperands 206976 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 568781 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 568781 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 194055 # Number of HB maps that are committed system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 84321 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 40263 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 40233 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 35230 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 245462 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.memDep0.insertedLoads 84323 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 40264 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 40234 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 35231 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 245467 # Number of instructions added to the IQ (excludes non-spec) system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 247263 # Number of instructions issued +system.cpu3.iq.iqInstsIssued 247268 # Number of instructions issued system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10948 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10583 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedInstsExamined 10933 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10571 # Number of squashed operands that are examined and possibly removed from graph system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 172027 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.437350 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.311410 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::samples 172033 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.437329 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.311411 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 63993 37.20% 37.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 63997 37.20% 37.20% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 40281 23.42% 73.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 41063 23.87% 97.14% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 40282 23.42% 73.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 41064 23.87% 97.14% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle @@ -1729,7 +1729,7 @@ system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Nu system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 172027 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 172033 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available @@ -1765,7 +1765,7 @@ system.cpu3.iq.fu_full::MemWrite 210 73.17% 100.00% # at system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 119304 48.25% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 119306 48.25% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued @@ -1794,23 +1794,23 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.25% # Ty system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 88373 35.74% 83.99% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 39586 16.01% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 88375 35.74% 83.99% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 39587 16.01% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 247263 # Type of FU issued -system.cpu3.iq.rate 1.425566 # Inst issue rate +system.cpu3.iq.FU_type_0::total 247268 # Type of FU issued +system.cpu3.iq.rate 1.425578 # Inst issue rate system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 666924 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 262516 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 245480 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.int_inst_queue_reads 666940 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 262506 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 245488 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 247550 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 247555 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 34961 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 34962 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed @@ -1824,10 +1824,10 @@ system.cpu3.iew.iewIdleCycles 0 # Nu system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 292666 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispatchedInsts 292672 # Number of instructions dispatched to IQ system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 84321 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 40263 # Number of dispatched store instructions +system.cpu3.iew.iewDispLoadInsts 84323 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 40264 # Number of dispatched store instructions system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -1835,79 +1835,79 @@ system.cpu3.iew.memOrderViolationEvents 45 # Nu system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 246084 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 83306 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecutedInsts 246092 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 83308 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 41143 # number of nop insts executed -system.cpu3.iew.exec_refs 122808 # number of memory reference insts executed -system.cpu3.iew.exec_branches 50377 # Number of branches executed -system.cpu3.iew.exec_stores 39502 # Number of stores executed -system.cpu3.iew.exec_rate 1.418769 # Inst execution rate -system.cpu3.iew.wb_sent 245746 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 245480 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 139608 # num instructions producing a value -system.cpu3.iew.wb_consumers 144273 # num instructions consuming a value +system.cpu3.iew.exec_nop 41144 # number of nop insts executed +system.cpu3.iew.exec_refs 122814 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50378 # Number of branches executed +system.cpu3.iew.exec_stores 39506 # Number of stores executed +system.cpu3.iew.exec_rate 1.418798 # Inst execution rate +system.cpu3.iew.wb_sent 245754 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 245488 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 139611 # num instructions producing a value +system.cpu3.iew.wb_consumers 144276 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.415286 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.967665 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.415316 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.967666 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 163516 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.713105 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.043722 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::samples 163517 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.713131 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.043728 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 63247 38.68% 38.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48404 29.60% 68.28% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 63246 38.68% 38.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48405 29.60% 68.28% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 35437 21.67% 98.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 35438 21.67% 98.54% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 163516 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 280120 # Number of instructions committed -system.cpu3.commit.committedOps 280120 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 163517 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 280126 # Number of instructions committed +system.cpu3.commit.committedOps 280126 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 120652 # Number of memory references committed -system.cpu3.commit.loads 81858 # Number of loads committed +system.cpu3.commit.refs 120655 # Number of memory references committed +system.cpu3.commit.loads 81860 # Number of loads committed system.cpu3.commit.membars 4779 # Number of memory barriers committed -system.cpu3.commit.branches 49540 # Number of branches committed +system.cpu3.commit.branches 49541 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 192312 # Number of committed integer instructions. +system.cpu3.commit.int_insts 192316 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 454763 # The number of ROB reads -system.cpu3.rob.rob_writes 587684 # The number of ROB writes +system.cpu3.rob.rob_reads 454770 # The number of ROB reads +system.cpu3.rob.rob_writes 587696 # The number of ROB writes system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1422 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 36211 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 235010 # Number of Instructions Simulated -system.cpu3.committedOps 235010 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 235010 # Number of Instructions Simulated -system.cpu3.cpi 0.738049 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.738049 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.354923 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.354923 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 427031 # number of integer regfile reads -system.cpu3.int_regfile_writes 198982 # number of integer regfile writes +system.cpu3.idleCycles 1418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 36213 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 235015 # Number of Instructions Simulated +system.cpu3.committedOps 235015 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 235015 # Number of Instructions Simulated +system.cpu3.cpi 0.738042 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.738042 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.354936 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.354936 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 427046 # number of integer regfile reads +system.cpu3.int_regfile_writes 198986 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 124365 # number of misc regfile reads +system.cpu3.misc_regfile_reads 124374 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 83.493816 # Cycle average of tags in use +system.cpu3.icache.tagsinuse 83.494084 # Cycle average of tags in use system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 83.493816 # Average occupied blocks per requestor +system.cpu3.icache.occ_blocks::cpu3.inst 83.494084 # Average occupied blocks per requestor system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits @@ -1922,12 +1922,12 @@ system.cpu3.icache.demand_misses::cpu3.inst 474 # system.cpu3.icache.demand_misses::total 474 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 474 # number of overall misses system.cpu3.icache.overall_misses::total 474 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6191000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6191000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6191000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6191000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6191000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6191000 # number of overall miss cycles +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6189500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6189500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6189500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6189500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6189500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6189500 # number of overall miss cycles system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses) system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses @@ -1940,12 +1940,12 @@ system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024681 system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13061.181435 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13061.181435 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13061.181435 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13061.181435 # average overall miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13058.016878 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13058.016878 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13058.016878 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13058.016878 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1966,44 +1966,44 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 428 system.cpu3.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 428 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4970500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4970500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4970500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4970500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4970500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4970500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4969500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4969500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4969500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4969500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4969500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4969500 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022286 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_miss_rate::total 0.022286 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_miss_rate::total 0.022286 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11613.317757 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11610.981308 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 25.854093 # Cycle average of tags in use -system.cpu3.dcache.total_refs 44811 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 25.854191 # Cycle average of tags in use +system.cpu3.dcache.total_refs 44812 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1600.392857 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1600.428571 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.854093 # Average occupied blocks per requestor +system.cpu3.dcache.occ_blocks::cpu3.data 25.854191 # Average occupied blocks per requestor system.cpu3.dcache.occ_percent::cpu3.data 0.050496 # Average percentage of cache occupancy system.cpu3.dcache.occ_percent::total 0.050496 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 47901 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 47901 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 38585 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 38585 # number of WriteReq hits +system.cpu3.dcache.ReadReq_hits::cpu3.data 47902 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 47902 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 38586 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 38586 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 86486 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 86486 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 86486 # number of overall hits -system.cpu3.dcache.overall_hits::total 86486 # number of overall hits +system.cpu3.dcache.demand_hits::cpu3.data 86488 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 86488 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 86488 # number of overall hits +system.cpu3.dcache.overall_hits::total 86488 # number of overall hits system.cpu3.dcache.ReadReq_misses::cpu3.data 426 # number of ReadReq misses system.cpu3.dcache.ReadReq_misses::total 426 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 142 # number of WriteReq misses @@ -2014,26 +2014,26 @@ system.cpu3.dcache.demand_misses::cpu3.data 568 # system.cpu3.dcache.demand_misses::total 568 # number of demand (read+write) misses system.cpu3.dcache.overall_misses::cpu3.data 568 # number of overall misses system.cpu3.dcache.overall_misses::total 568 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5342000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 5342000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2332500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2332500 # number of WriteReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5341000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 5341000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2325000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2325000 # number of WriteReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 555000 # number of SwapReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::total 555000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7674500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7674500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7674500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7674500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 48327 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 48327 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 38727 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 38727 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.demand_miss_latency::cpu3.data 7666000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7666000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7666000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7666000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 48328 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 48328 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 38728 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 38728 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 87054 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 87054 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 87054 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 87054 # number of overall (read+write) accesses +system.cpu3.dcache.demand_accesses::cpu3.data 87056 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 87056 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 87056 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 87056 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008815 # miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_miss_rate::total 0.008815 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003667 # miss rate for WriteReq accesses @@ -2044,16 +2044,16 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006525 system.cpu3.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006525 # miss rate for overall accesses system.cpu3.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12539.906103 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12539.906103 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16426.056338 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 16426.056338 # average WriteReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12537.558685 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12537.558685 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16373.239437 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16373.239437 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9910.714286 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 9910.714286 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 13511.443662 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 13511.443662 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 13496.478873 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 13496.478873 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2080,16 +2080,16 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1265000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1265000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1159500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1159500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1264000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1264000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1158000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1158000 # number of WriteReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 443000 # number of SwapReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::total 443000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2424500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2424500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2424500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2424500 # number of overall MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2422000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2422000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2422000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2422000 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003166 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002815 # mshr miss rate for WriteReq accesses @@ -2100,32 +2100,32 @@ system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003010 system.cpu3.dcache.demand_mshr_miss_rate::total 0.003010 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for overall accesses system.cpu3.dcache.overall_mshr_miss_rate::total 0.003010 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8267.973856 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8267.973856 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10637.614679 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10637.614679 # average WriteReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8261.437908 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8261.437908 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10623.853211 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10623.853211 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7910.714286 # average SwapReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7910.714286 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9253.816794 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9253.816794 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9253.816794 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9253.816794 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 425.296596 # Cycle average of tags in use +system.l2c.tagsinuse 425.291959 # Cycle average of tags in use system.l2c.total_refs 1448 # Total number of references to valid blocks. system.l2c.sampled_refs 525 # Sample count of references to valid blocks. system.l2c.avg_refs 2.758095 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.828895 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 289.891501 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.268437 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 63.508816 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.639642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2.310248 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.728233 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 2.354110 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.766714 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.828889 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.887816 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.267955 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 63.508377 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.639601 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2.310233 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.728238 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.354132 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.766718 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000904 # Average percentage of cache occupancy @@ -2135,7 +2135,7 @@ system.l2c.occ_percent::cpu2.inst 0.000035 # Av system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000036 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006490 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits @@ -2204,38 +2204,38 @@ system.l2c.overall_misses::cpu2.data 13 # nu system.l2c.overall_misses::cpu3.inst 4 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 668 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 17565000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 17552500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 4069000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4146500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4145500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 381000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 396000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 395000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 233000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 232000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 26927500 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5000500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 881000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 699500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 661500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7242500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 17565000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 9069500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4146500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1262000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 396000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 768000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 233000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 730000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 34170000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 17565000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 9069500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4146500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1262000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 396000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 768000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 233000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 730000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 34170000 # number of overall miss cycles +system.l2c.ReadReq_miss_latency::total 26912000 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5008000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 878500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 701000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 660000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7247500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 17552500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 9077000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4145500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1259500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 395000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 769500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 232000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 728500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 34159500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 17552500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 9077000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4145500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1259500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 395000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 769500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 232000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 728500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 34159500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) @@ -2312,38 +2312,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.541667 # mi system.l2c.overall_miss_rate::cpu3.inst 0.009346 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.315690 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48927.576602 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48892.757660 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 54986.486486 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49957.831325 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49945.783133 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 54428.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49375 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 58250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 58000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 50144.320298 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53196.808511 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67769.230769 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58291.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55125 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 55286.259542 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 48927.576602 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 53985.119048 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 49957.831325 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 63100 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 49500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 59076.923077 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 58250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 56153.846154 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51152.694611 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 48927.576602 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 53985.119048 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 49957.831325 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 63100 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 49500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 59076.923077 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 58250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 56153.846154 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51152.694611 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::total 50115.456238 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53276.595745 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67576.923077 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58416.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55324.427481 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 48892.757660 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 54029.761905 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 49945.783133 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 62975 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 49375 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 59192.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 58000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 56038.461538 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51136.976048 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 48892.757660 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 54029.761905 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 49945.783133 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 62975 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 49375 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 59192.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 58000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 56038.461538 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51136.976048 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2401,43 +2401,43 @@ system.l2c.overall_mshr_misses::cpu2.data 13 # n system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 659 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13017059 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13005059 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3150576 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3026126 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 293010 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 103002 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 181507 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 180507 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 19883284 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 19870284 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 193013 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 181515 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 153009 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200519 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 728056 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3829610 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 719513 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 549018 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511018 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5609159 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 13017059 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6980186 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3834610 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 717513 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 550018 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 510018 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5612159 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 13005059 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6985186 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 3026126 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1012523 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1010523 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 103002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 605020 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 181507 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 567020 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 25492443 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 13017059 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6980186 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 606020 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 180507 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 566020 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 25482443 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 13005059 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6985186 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 3026126 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1012523 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1010523 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 103002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 605020 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 181507 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 567020 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 25492443 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 606020 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 180507 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 566020 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 25482443 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for ReadReq accesses @@ -2475,43 +2475,43 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.311437 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42575.351351 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 34334 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 37657.734848 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 37633.113636 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.578947 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10084.166667 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10200.600000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10025.950000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.888889 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40740.531915 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55347.153846 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45751.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42584.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 42818.007634 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40793.723404 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55193.307692 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45834.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42501.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42840.908397 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41578.488095 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50526.150000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46616.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43540 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 38668.350531 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41578.488095 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50526.150000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46616.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 38668.350531 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |