stats: changes to due to recent set of patches

2 files changed, 12 insertions, 9 deletions

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 8f525a009..4a4cc509f 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -2150,11 +2151,14 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.l2c.mem_side
 
@@ -2185,7 +2189,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -2239,11 +2243,14 @@ port=system.membus.master[0]
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 948908ba0..97adbdaa9 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -563,7 +563,6 @@ system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::total           450384                       # Class of committed instruction
 system.cpu0.commit.bw_lim_events                  494                       # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.rob.rob_reads                      649458                       # The number of ROB reads
 system.cpu0.rob.rob_writes                     931043                       # The number of ROB writes
 system.cpu0.timesIdled                            314                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1087,7 +1086,6 @@ system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::total           251602                       # Class of committed instruction
 system.cpu1.commit.bw_lim_events                 1312                       # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu1.rob.rob_reads                      417798                       # The number of ROB reads
 system.cpu1.rob.rob_writes                     534614                       # The number of ROB writes
 system.cpu1.timesIdled                            216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1607,7 +1605,6 @@ system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::total           246921                       # Class of committed instruction
 system.cpu2.commit.bw_lim_events                 1310                       # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu2.rob.rob_reads                      416888                       # The number of ROB reads
 system.cpu2.rob.rob_writes                     525783                       # The number of ROB writes
 system.cpu2.timesIdled                            205                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -2128,7 +2125,6 @@ system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::total           238347                       # Class of committed instruction
 system.cpu3.commit.bw_lim_events                 1300                       # number cycles where commit BW limit reached
-system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu3.rob.rob_reads                      408052                       # The number of ROB reads
 system.cpu3.rob.rob_writes                     507784                       # The number of ROB writes
 system.cpu3.timesIdled                            206                       # Number of times that the entire CPU went into an idle state and unscheduled itself