diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
| commit | d52adc4eb68c2733f9af4ac68834583c0a555f9d (patch) | |
| tree | 2ee5c3d271af63a3ef527c54950f57f406a05d90 /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt | |
| parent | 88554790c34f6fef4ba6285927fb9742b90ab258 (diff) | |
| download | gem5-d52adc4eb68c2733f9af4ac68834583c0a555f9d.tar.xz | |
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt | 1925 |
1 files changed, 964 insertions, 961 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 1523ab302..df50fe29d 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000269 # Number of seconds simulated -sim_ticks 268898000 # Number of ticks simulated -final_tick 268898000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000262 # Number of seconds simulated +sim_ticks 261623500 # Number of ticks simulated +final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1131883 # Simulator instruction rate (inst/s) -host_op_rate 1131850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 454173870 # Simulator tick rate (ticks/s) -host_mem_usage 240368 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -sim_insts 670104 # Number of instructions simulated -sim_ops 670104 # Number of ops (including micro ops) simulated +host_inst_rate 776063 # Simulator instruction rate (inst/s) +host_op_rate 776047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 307506962 # Simulator tick rate (ticks/s) +host_mem_usage 231300 # Number of bytes of host memory used +host_seconds 0.85 # Real time elapsed on the host +sim_insts 660239 # Number of instructions simulated +sim_ops 660239 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 67832412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39271397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14042499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5236186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 476017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3570127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1904068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3808135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136140842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 67832412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14042499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 476017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1904068 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84254996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 67832412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39271397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14042499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5236186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 476017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3570127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1904068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3808135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 136140842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 537796 # number of cpu cycles simulated +system.cpu0.numCycles 523247 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 160914 # Number of instructions committed -system.cpu0.committedOps 160914 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 110768 # Number of integer alu accesses +system.cpu0.committedInsts 158010 # Number of instructions committed +system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 26422 # number of instructions that are conditional controls -system.cpu0.num_int_insts 110768 # number of integer instructions +system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108832 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 320462 # number of times the integer registers were read -system.cpu0.num_int_register_writes 112374 # number of times the integer registers were written +system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 75191 # number of memory refs -system.cpu0.num_load_insts 49787 # Number of load instructions -system.cpu0.num_store_insts 25404 # Number of store instructions +system.cpu0.num_mem_refs 73739 # number of memory refs +system.cpu0.num_load_insts 48819 # Number of load instructions +system.cpu0.num_store_insts 24920 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 537796 # Number of busy cycles +system.cpu0.num_busy_cycles 523247 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.263647 # Cycle average of tags in use -system.cpu0.icache.total_refs 160510 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use +system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 343.704497 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.263647 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414577 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414577 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 160510 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 160510 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 160510 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 160510 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 160510 # number of overall hits -system.cpu0.icache.overall_hits::total 160510 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits +system.cpu0.icache.overall_hits::total 157606 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18554000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18554000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18554000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18554000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18554000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18554000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 160977 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 160977 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 160977 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 160977 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 160977 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 160977 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002901 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002901 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002901 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002901 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002901 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002901 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 39730.192719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 39730.192719 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,44 +139,44 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17153000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17153000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17153000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17153000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17153000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17153000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002901 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002901 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36730.192719 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.520681 # Cycle average of tags in use -system.cpu0.dcache.total_refs 74667 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.601248 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73215 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 447.107784 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 438.413174 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.520681 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284220 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284220 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 49615 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 49615 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 25170 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 25170 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.601248 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284377 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284377 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48647 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48647 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24686 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24686 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 74785 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 74785 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 74785 # number of overall hits -system.cpu0.dcache.overall_hits::total 74785 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73333 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73333 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73333 # number of overall hits +system.cpu0.dcache.overall_hits::total 73333 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -187,46 +187,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5171000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5171000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7310000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7310000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 522000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 522000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12481000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12481000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12481000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12481000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 49777 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 49777 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 25353 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 25353 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4649500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7005000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7005000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 363500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 363500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11654500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11654500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11654500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11654500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48809 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48809 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24869 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24869 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 75130 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 75130 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 75130 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 75130 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003255 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003255 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007218 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007218 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73678 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73678 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73678 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73678 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003319 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003319 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007359 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007359 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004592 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004592 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004592 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004592 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31919.753086 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31919.753086 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39945.355191 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39945.355191 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20076.923077 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 20076.923077 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36176.811594 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004683 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004683 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004683 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -247,104 +247,104 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4684001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4684001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6761000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6761000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 444000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 444000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11445001 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11445001 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11445001 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11445001 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003255 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003255 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007218 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007218 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4325500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6639000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6639000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10964500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007359 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004592 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004592 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28913.586420 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28913.586420 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36945.355191 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36945.355191 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17076.923077 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17076.923077 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004683 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004683 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26700.617284 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26700.617284 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36278.688525 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36278.688525 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11980.769231 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 537796 # number of cpu cycles simulated +system.cpu1.numCycles 523247 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 159902 # Number of instructions committed -system.cpu1.committedOps 159902 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 114536 # Number of integer alu accesses +system.cpu1.committedInsts 173283 # Number of instructions committed +system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 26689 # number of instructions that are conditional controls -system.cpu1.num_int_insts 114536 # number of integer instructions +system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls +system.cpu1.num_int_insts 108736 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 313629 # number of times the integer registers were read -system.cpu1.num_int_register_writes 121810 # number of times the integer registers were written +system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read +system.cpu1.num_int_register_writes 93825 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 64016 # number of memory refs -system.cpu1.num_load_insts 42937 # Number of load instructions -system.cpu1.num_store_insts 21079 # Number of store instructions -system.cpu1.num_idle_cycles 71578.001734 # Number of idle cycles -system.cpu1.num_busy_cycles 466217.998266 # Number of busy cycles -system.cpu1.not_idle_fraction 0.866905 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.133095 # Percentage of idle cycles +system.cpu1.num_mem_refs 48621 # number of memory refs +system.cpu1.num_load_insts 40031 # Number of load instructions +system.cpu1.num_store_insts 8590 # Number of store instructions +system.cpu1.num_idle_cycles 68750.001737 # Number of idle cycles +system.cpu1.num_busy_cycles 454496.998263 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868609 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131391 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 69.905818 # Cycle average of tags in use -system.cpu1.icache.total_refs 159569 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 65.593035 # Cycle average of tags in use +system.cpu1.icache.total_refs 172950 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 435.980874 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 472.540984 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 69.905818 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136535 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136535 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 159569 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 159569 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 159569 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 159569 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 159569 # number of overall hits -system.cpu1.icache.overall_hits::total 159569 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 65.593035 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.128111 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.128111 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 172950 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 172950 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 172950 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 172950 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 172950 # number of overall hits +system.cpu1.icache.overall_hits::total 172950 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7984500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7984500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7984500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7984500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7984500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7984500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 159935 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 159935 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 159935 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 159935 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 159935 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 159935 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002288 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002288 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002288 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002288 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002288 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002288 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21815.573770 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21815.573770 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21815.573770 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21815.573770 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5373500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5373500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5373500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5373500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5373500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5373500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 173316 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 173316 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 173316 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 173316 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 173316 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 173316 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002112 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002112 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002112 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002112 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002112 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002112 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14681.693989 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14681.693989 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14681.693989 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14681.693989 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +359,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6886000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6886000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6886000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6886000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6886000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6886000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002288 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18814.207650 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4641500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4641500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4641500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4641500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4641500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4641500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002112 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002112 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.693989 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.731515 # Cycle average of tags in use -system.cpu1.dcache.total_refs 44449 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1532.724138 # Average number of references to valid blocks. +system.cpu1.dcache.tagsinuse 25.918058 # Cycle average of tags in use +system.cpu1.dcache.total_refs 19532 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 651.066667 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.731515 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054163 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054163 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 42776 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 42776 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 20903 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 20903 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 10 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 63679 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 63679 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 63679 # number of overall hits -system.cpu1.dcache.overall_hits::total 63679 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 153 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 153 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 259 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 259 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259 # number of overall misses -system.cpu1.dcache.overall_misses::total 259 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3030000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3030000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2410000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2410000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 772000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 772000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5440000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5440000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5440000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5440000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 42929 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 42929 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 21009 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 21009 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 63938 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 63938 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 63938 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 63938 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003564 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003564 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005045 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.005045 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.852941 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004051 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004051 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004051 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004051 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19803.921569 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19803.921569 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22735.849057 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22735.849057 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13310.344828 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 13310.344828 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21003.861004 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21003.861004 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 25.918058 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.050621 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.050621 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 39847 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39847 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 8412 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 8412 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 48259 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 48259 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 48259 # number of overall hits +system.cpu1.dcache.overall_hits::total 48259 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 177 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 177 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses +system.cpu1.dcache.overall_misses::total 282 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3316000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3316000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1875500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1875500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 659500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 659500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5191500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5191500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5191500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5191500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40024 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40024 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 8517 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 8517 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 48541 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 48541 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 48541 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 48541 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004422 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004422 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012328 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012328 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.774648 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.774648 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005810 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005810 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005810 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005810 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18734.463277 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18734.463277 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17861.904762 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17861.904762 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11990.909091 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 11990.909091 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18409.574468 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18409.574468 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,114 +455,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2570001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2570001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2092000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 598000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 598000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4662001 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4662001 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4662001 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4662001 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003564 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003564 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.005045 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.005045 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.852941 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004051 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004051 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16797.392157 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16797.392157 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19735.849057 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19735.849057 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10310.344828 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10310.344828 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 177 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 282 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 282 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 282 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 282 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2962000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2962000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1665500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 549500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4627500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4627500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4627500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004422 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012328 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012328 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005810 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005810 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 9990.909091 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 537796 # number of cpu cycles simulated +system.cpu2.numCycles 523246 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 177221 # Number of instructions committed -system.cpu2.committedOps 177221 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 109567 # Number of integer alu accesses +system.cpu2.committedInsts 160665 # Number of instructions committed +system.cpu2.committedOps 160665 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 113639 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 37840 # number of instructions that are conditional controls -system.cpu2.num_int_insts 109567 # number of integer instructions +system.cpu2.num_conditional_control_insts 27518 # number of instructions that are conditional controls +system.cpu2.num_int_insts 113639 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 249142 # number of times the integer registers were read -system.cpu2.num_int_register_writes 92045 # number of times the integer registers were written +system.cpu2.num_int_register_reads 306682 # number of times the integer registers were read +system.cpu2.num_int_register_writes 118721 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 47896 # number of memory refs -system.cpu2.num_load_insts 40447 # Number of load instructions -system.cpu2.num_store_insts 7449 # Number of store instructions -system.cpu2.num_idle_cycles 71854.001733 # Number of idle cycles -system.cpu2.num_busy_cycles 465941.998267 # Number of busy cycles -system.cpu2.not_idle_fraction 0.866392 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.133608 # Percentage of idle cycles +system.cpu2.num_mem_refs 62290 # number of memory refs +system.cpu2.num_load_insts 42488 # Number of load instructions +system.cpu2.num_store_insts 19802 # Number of store instructions +system.cpu2.num_idle_cycles 69015.869837 # Number of idle cycles +system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles +system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles system.cpu2.icache.replacements 281 # number of replacements -system.cpu2.icache.tagsinuse 67.534984 # Cycle average of tags in use -system.cpu2.icache.total_refs 176887 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use +system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 481.980926 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 67.534984 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.131904 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.131904 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 176887 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 176887 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 176887 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 176887 # 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number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 177254 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 177254 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 177254 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 177254 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002070 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002070 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002070 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002070 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002070 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002070 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15557.220708 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15557.220708 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15557.220708 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15557.220708 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5321500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5321500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5321500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5321500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5321500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5321500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 160698 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 160698 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 160698 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 160698 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 160698 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 160698 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002284 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002284 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002284 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002284 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002284 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002284 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14500 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14500 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14500 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,94 +577,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4608500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4608500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4608500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4608500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4608500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4608500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002070 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002070 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002070 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12557.220708 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4587500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4587500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4587500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4587500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4587500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4587500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002284 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12500 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12500 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 26.638398 # Cycle average of tags in use -system.cpu2.dcache.total_refs 17171 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.833050 # Cycle average of tags in use +system.cpu2.dcache.total_refs 41851 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 592.103448 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1443.137931 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.638398 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.052028 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.052028 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 40266 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40266 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 7273 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 7273 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 18 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 18 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 47539 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 47539 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 47539 # number of overall hits -system.cpu2.dcache.overall_hits::total 47539 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 173 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 173 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 278 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 278 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 278 # number of overall misses -system.cpu2.dcache.overall_misses::total 278 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3995000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3995000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2318000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2318000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 814000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 814000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 6313000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 6313000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 6313000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 6313000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40439 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40439 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 7378 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 7378 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 47817 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 47817 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 47817 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 47817 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004278 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.004278 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.014231 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.014231 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.739130 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.739130 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005814 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005814 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005814 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005814 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23092.485549 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 23092.485549 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22076.190476 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 22076.190476 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15960.784314 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 15960.784314 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 22708.633094 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 22708.633094 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 26.833050 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.052408 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.052408 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42328 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42328 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 19626 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 19626 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 61954 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 61954 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 61954 # number of overall hits +system.cpu2.dcache.overall_hits::total 61954 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 106 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 106 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 258 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 258 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 258 # number of overall misses +system.cpu2.dcache.overall_misses::total 258 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1938000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 1938000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2155000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2155000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 612500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 612500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4093000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4093000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4093000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4093000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42480 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42480 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 19732 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 19732 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 62212 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 62212 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 62212 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 62212 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003578 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003578 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005372 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.005372 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.852941 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004147 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004147 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004147 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004147 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12750 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 12750 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20330.188679 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20330.188679 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10560.344828 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10560.344828 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15864.341085 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15864.341085 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,114 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 173 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 278 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 278 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 3476000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 3476000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2003000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2003000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 661000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 661000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5479000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 5479000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5479000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 5479000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004278 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004278 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014231 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.014231 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.739130 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.739130 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.005814 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.005814 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20092.485549 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 20092.485549 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19076.190476 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19076.190476 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 12960.784314 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 12960.784314 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 258 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 258 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1634000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1634000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1943000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1943000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 496500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 496500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3577000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3577000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3577000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3577000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003578 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003578 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005372 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005372 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.852941 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004147 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004147 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10750 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10750 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18330.188679 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18330.188679 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8560.344828 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8560.344828 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 537796 # number of cpu cycles simulated +system.cpu3.numCycles 523246 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 172067 # Number of instructions committed -system.cpu3.committedOps 172067 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111206 # Number of integer alu accesses +system.cpu3.committedInsts 168281 # Number of instructions committed +system.cpu3.committedOps 168281 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 108796 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 34437 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111206 # number of integer instructions +system.cpu3.num_conditional_control_insts 33752 # number of instructions that are conditional controls +system.cpu3.num_int_insts 108796 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 269314 # number of times the integer registers were read -system.cpu3.num_int_register_writes 101322 # number of times the integer registers were written +system.cpu3.num_int_register_reads 262371 # number of times the integer registers were read +system.cpu3.num_int_register_writes 98980 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 52937 # number of memory refs -system.cpu3.num_load_insts 41268 # Number of load instructions -system.cpu3.num_store_insts 11669 # Number of store instructions -system.cpu3.num_idle_cycles 72130.001732 # Number of idle cycles -system.cpu3.num_busy_cycles 465665.998268 # Number of busy cycles -system.cpu3.not_idle_fraction 0.865879 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.134121 # Percentage of idle cycles +system.cpu3.num_mem_refs 51213 # number of memory refs +system.cpu3.num_load_insts 40064 # Number of load instructions +system.cpu3.num_store_insts 11149 # Number of store instructions +system.cpu3.num_idle_cycles 69253.869381 # Number of idle cycles +system.cpu3.num_busy_cycles 453992.130619 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867646 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132354 # Percentage of idle cycles system.cpu3.icache.replacements 280 # number of replacements -system.cpu3.icache.tagsinuse 65.345482 # Cycle average of tags in use -system.cpu3.icache.total_refs 171734 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 70.063196 # Cycle average of tags in use +system.cpu3.icache.total_refs 167948 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 469.218579 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 458.874317 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 65.345482 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.127628 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.127628 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 171734 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 171734 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 171734 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 171734 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 171734 # number of overall hits -system.cpu3.icache.overall_hits::total 171734 # number of overall hits +system.cpu3.icache.occ_blocks::cpu3.inst 70.063196 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.136842 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.136842 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 167948 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 167948 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 167948 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 167948 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 167948 # number of overall hits +system.cpu3.icache.overall_hits::total 167948 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 366 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 366 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 366 # number of overall misses system.cpu3.icache.overall_misses::total 366 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5645500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5645500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5645500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5645500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5645500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5645500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 172100 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 172100 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 172100 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 172100 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 172100 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 172100 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002127 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002127 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002127 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002127 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002127 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002127 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15424.863388 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15424.863388 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15424.863388 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15424.863388 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15424.863388 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15424.863388 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7343000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7343000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7343000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7343000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7343000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7343000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 168314 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 168314 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 168314 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 168314 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 168314 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 168314 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002175 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002175 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002175 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 20062.841530 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 20062.841530 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 20062.841530 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 20062.841530 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -795,94 +795,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 366 system.cpu3.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 366 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4547000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4547000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4547000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4547000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4547000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4547000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002127 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002127 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002127 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12423.497268 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6611000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6611000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6611000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6611000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6611000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6611000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 18062.841530 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 25.850163 # Cycle average of tags in use -system.cpu3.dcache.total_refs 25744 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 858.133333 # Average number of references to valid blocks. +system.cpu3.dcache.tagsinuse 27.713697 # Cycle average of tags in use +system.cpu3.dcache.total_refs 24536 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 846.068966 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.850163 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050489 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050489 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41084 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41084 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 11491 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 11491 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 52575 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 52575 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 52575 # number of overall hits -system.cpu3.dcache.overall_hits::total 52575 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 176 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 176 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 59 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 59 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 281 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 281 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 281 # number of overall misses -system.cpu3.dcache.overall_misses::total 281 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4401000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4401000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1861000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1861000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 928000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 928000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 6262000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 6262000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 6262000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 6262000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41260 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41260 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 11596 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 11596 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 52856 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 52856 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 52856 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 52856 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004266 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.004266 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009055 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.009055 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830986 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.830986 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005316 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005316 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005316 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005316 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 25005.681818 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 25005.681818 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17723.809524 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 17723.809524 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15728.813559 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 15728.813559 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 22284.697509 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 22284.697509 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 22284.697509 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 22284.697509 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 27.713697 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.054128 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.054128 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 39885 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 39885 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 10974 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 10974 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 50859 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 50859 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 50859 # number of overall hits +system.cpu3.dcache.overall_hits::total 50859 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 172 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 172 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 104 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 104 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 276 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 276 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 276 # number of overall misses +system.cpu3.dcache.overall_misses::total 276 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3405000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 3405000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1971500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1971500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 653500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 653500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 5376500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 5376500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 5376500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 5376500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 40057 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 40057 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 11078 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 11078 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 69 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 51135 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 51135 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 51135 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 51135 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004294 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.004294 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009388 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.009388 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797101 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005397 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005397 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005397 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005397 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 19796.511628 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 19796.511628 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18956.730769 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18956.730769 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11881.818182 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 11881.818182 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 19480.072464 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 19480.072464 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -891,80 +891,80 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 176 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 281 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 281 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3873000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3873000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1546000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1546000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 751000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 751000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 5419000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 5419000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 5419000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 5419000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004266 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004266 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830986 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005316 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005316 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 22005.681818 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 22005.681818 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14723.809524 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14723.809524 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 12728.813559 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 12728.813559 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 19284.697509 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 19284.697509 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 19284.697509 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 19284.697509 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # 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number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4824500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4824500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4824500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4824500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004294 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004294 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009388 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009388 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797101 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005397 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005397 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17796.511628 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17796.511628 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16956.730769 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16956.730769 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9881.818182 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9881.818182 # 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Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 231.689332 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 54.189752 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 51.472071 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.113701 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.771073 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.842159 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 1.030424 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.829169 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.889459 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 231.842883 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 54.217473 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 6.219466 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 0.812784 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.917796 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.863537 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 46.262373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 6.128563 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.003535 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000785 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005323 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000706 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000094 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005328 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 300 # 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number of ReadReq accesses(hits+misses) @@ -1069,47 +1069,47 @@ system.l2c.ReadReq_accesses::total 1670 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 27 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 87 # 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average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40147.887324 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |