diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp')
3 files changed, 982 insertions, 674 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index ae7e021b5..c00589f53 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[1] [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache itb tracer workload +children=dcache dtb icache interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu0.interrupts itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu0.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu0.interrupts] +type=SparcInterrupts + [system.cpu0.itb] type=SparcTLB size=64 @@ -143,16 +142,18 @@ uid=100 [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer checker=Null clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu1.interrupts itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -160,6 +161,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu1.tracer @@ -178,20 +180,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -214,20 +209,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -235,6 +223,9 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] +[system.cpu1.interrupts] +type=SparcInterrupts + [system.cpu1.itb] type=SparcTLB size=64 @@ -244,16 +235,18 @@ type=ExeTracer [system.cpu2] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer checker=Null clock=500 cpu_id=2 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu2.interrupts itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -261,6 +254,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu2.tracer @@ -279,20 +273,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -315,20 +302,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -336,6 +316,9 @@ write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.port[5] +[system.cpu2.interrupts] +type=SparcInterrupts + [system.cpu2.itb] type=SparcTLB size=64 @@ -345,16 +328,18 @@ type=ExeTracer [system.cpu3] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer checker=Null clock=500 cpu_id=3 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu3.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu3.interrupts itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -362,6 +347,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu3.tracer @@ -380,20 +366,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -416,20 +395,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -437,6 +409,9 @@ write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.port[7] +[system.cpu3.interrupts] +type=SparcInterrupts + [system.cpu3.itb] type=SparcTLB size=64 @@ -455,20 +430,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=4 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 6f90c0dd1..bd048d482 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:33 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:56:07 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 0ce3fe3af..fcff65a90 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000262 # Nu sim_ticks 262298000 # Number of ticks simulated final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1158712 # Simulator instruction rate (inst/s) -host_tick_rate 458877844 # Simulator tick rate (ticks/s) -host_mem_usage 222944 # Number of bytes of host memory used -host_seconds 0.57 # Real time elapsed on the host +host_inst_rate 1330969 # Simulator instruction rate (inst/s) +host_op_rate 1330920 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 527074583 # Simulator tick rate (ticks/s) +host_mem_usage 221728 # Number of bytes of host memory used +host_seconds 0.50 # Real time elapsed on the host sim_insts 662307 # Number of instructions simulated +sim_ops 662307 # Number of ops (including micro ops) simulated system.physmem.bytes_read 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu0.workload.num_syscalls 89 # Nu system.cpu0.numCycles 524596 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 158353 # Number of instructions executed +system.cpu0.committedInsts 158353 # Number of instructions committed +system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu0.icache.total_refs 157949 # To system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 212.479188 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.414998 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 157949 # number of ReadReq hits -system.cpu0.icache.demand_hits 157949 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 157949 # number of overall hits -system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses -system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 18524000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 18524000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 18524000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses 158416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses 158416 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses 158416 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.002948 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.002948 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.002948 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency 39665.952891 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency 39665.952891 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits +system.cpu0.icache.overall_hits::total 157949 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 17123000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 17123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 17123000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.002948 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate 0.002948 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate 0.002948 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36665.952891 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use @@ -101,38 +115,59 @@ system.cpu0.dcache.total_refs 56009 # To system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 141.233342 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.275846 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 48758 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits 24741 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits 73499 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 73499 # number of overall hits -system.cpu0.dcache.ReadReq_misses 162 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses 183 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency 387000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 11924000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 48920 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses 24924 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 73844 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 73844 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate 0.003312 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate 0.007342 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate 0.004672 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate 0.004672 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 34562.318841 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits +system.cpu0.dcache.overall_hits::total 73499 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses +system.cpu0.dcache.overall_misses::total 345 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,39 +176,44 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 183 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 345 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.003312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.007342 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate 0.004672 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks +system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 524596 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 172325 # Number of instructions executed +system.cpu1.committedInsts 172325 # Number of instructions committed +system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured @@ -197,26 +237,39 @@ system.cpu1.icache.total_refs 171992 # To system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 70.076133 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits 171992 # number of ReadReq hits -system.cpu1.icache.demand_hits 171992 # number of demand (read+write) hits -system.cpu1.icache.overall_hits 171992 # number of overall hits -system.cpu1.icache.ReadReq_misses 366 # number of ReadReq misses -system.cpu1.icache.demand_misses 366 # number of demand (read+write) misses -system.cpu1.icache.overall_misses 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7920500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7920500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7920500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses 172358 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses 172358 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses 172358 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate 0.002123 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate 0.002123 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate 0.002123 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency 21640.710383 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency 21640.710383 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency 21640.710383 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 70.076133 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136867 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136867 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 171992 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 171992 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 171992 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 171992 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 171992 # number of overall hits +system.cpu1.icache.overall_hits::total 171992 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses +system.cpu1.icache.overall_misses::total 366 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7920500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7920500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7920500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7920500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7920500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -225,67 +278,84 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 366 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 6822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 6822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 6822000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.002123 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate 0.002123 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate 0.002123 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 18639.344262 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 22.703917 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 26.693562 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -3.989645 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.052136 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::1 -0.007792 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 39428 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 8099 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits 18 # number of SwapReq hits -system.cpu1.dcache.demand_hits 47527 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 47527 # number of overall hits -system.cpu1.dcache.ReadReq_misses 181 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses 98 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses 65 # number of SwapReq misses -system.cpu1.dcache.demand_misses 279 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses 279 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 3713000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 1889000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency 415000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency 5602000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 5602000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 39609 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 8197 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses 83 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 47806 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 47806 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.004570 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate 0.011956 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate 0.783133 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.005836 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.005836 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency 20513.812155 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency 19275.510204 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency 6384.615385 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency 20078.853047 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 20078.853047 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.052136 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.052136 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 39428 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39428 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 47527 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 47527 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 47527 # number of overall hits +system.cpu1.dcache.overall_hits::total 47527 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 181 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 181 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 279 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 279 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 279 # number of overall misses +system.cpu1.dcache.overall_misses::total 279 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3713000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3713000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1889000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1889000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5602000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5602000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5602000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5602000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 39609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 39609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -294,39 +364,44 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 279 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 3170000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1595000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.004570 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.011956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16275.510204 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu1.dcache.writebacks::total 1 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3170000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3170000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1595000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 524596 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.num_insts 165499 # Number of instructions executed +system.cpu2.committedInsts 165499 # Number of instructions committed +system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured @@ -350,26 +425,39 @@ system.cpu2.icache.total_refs 165166 # To system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 65.601019 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits 165166 # number of ReadReq hits -system.cpu2.icache.demand_hits 165166 # number of demand (read+write) hits -system.cpu2.icache.overall_hits 165166 # number of overall hits -system.cpu2.icache.ReadReq_misses 366 # number of ReadReq misses -system.cpu2.icache.demand_misses 366 # number of demand (read+write) misses -system.cpu2.icache.overall_misses 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency 5648500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency 5648500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency 5648500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses 165532 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses 165532 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate 0.002211 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate 0.002211 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency 15433.060109 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency 15433.060109 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency 15433.060109 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 65.601019 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.128127 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.128127 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 165166 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165166 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165166 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165166 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165166 # number of overall hits +system.cpu2.icache.overall_hits::total 165166 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses +system.cpu2.icache.overall_misses::total 366 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5648500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5648500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,67 +466,84 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses 366 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.ReadReq_mshr_miss_latency 4550500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency 4550500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency 4550500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate 0.002211 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 12433.060109 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 12433.060109 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 12433.060109 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 23.305393 # Cycle average of tags in use +system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 24.943438 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -1.638045 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::1 -0.003199 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 41688 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 15916 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits 57604 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 57604 # number of overall hits -system.cpu2.dcache.ReadReq_misses 156 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses 109 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses 265 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses 265 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency 2084000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency 305000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 4611000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 41844 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 16025 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses 62 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 57869 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 57869 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate 0.003728 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate 0.006802 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.004579 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.004579 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency 19119.266055 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency 5980.392157 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 17400 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.048718 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.048718 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 41688 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 41688 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 57604 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 57604 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 57604 # number of overall hits +system.cpu2.dcache.overall_hits::total 57604 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 156 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 156 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 265 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 265 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 265 # number of overall misses +system.cpu2.dcache.overall_misses::total 265 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2527000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2527000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2084000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,39 +552,44 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses 109 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses 265 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency 1757000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003728 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.006802 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16119.266055 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu2.dcache.writebacks::total 1 # number of writebacks +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 524596 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.num_insts 166130 # Number of instructions executed +system.cpu3.committedInsts 166130 # Number of instructions committed +system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured @@ -503,26 +613,39 @@ system.cpu3.icache.total_refs 165796 # To system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 67.737646 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits 165796 # number of ReadReq hits -system.cpu3.icache.demand_hits 165796 # number of demand (read+write) hits -system.cpu3.icache.overall_hits 165796 # number of overall hits -system.cpu3.icache.ReadReq_misses 367 # number of ReadReq misses -system.cpu3.icache.demand_misses 367 # number of demand (read+write) misses -system.cpu3.icache.overall_misses 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency 5531500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency 5531500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses 166163 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses 166163 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate 0.002209 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate 0.002209 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency 15072.207084 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency 15072.207084 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 67.737646 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.132300 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 165796 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 165796 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 165796 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 165796 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 165796 # number of overall hits +system.cpu3.icache.overall_hits::total 165796 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses +system.cpu3.icache.overall_misses::total 367 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5531500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5531500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5531500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5531500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,67 +654,84 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses 367 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses 367 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.ReadReq_mshr_miss_latency 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency 4430500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.002209 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate 0.002209 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate 0.002209 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 12072.207084 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 22.083417 # Cycle average of tags in use +system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::0 25.684916 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -3.601499 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.050166 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::1 -0.007034 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 41555 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 15348 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits 56903 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 56903 # number of overall hits -system.cpu3.dcache.ReadReq_misses 157 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses 108 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses 265 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses 265 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency 2569000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency 2080000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency 326000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency 4649000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency 4649000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 41712 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 15456 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 57168 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 57168 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate 0.003764 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate 0.006988 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate 0.830769 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate 0.004635 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate 0.004635 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency 16363.057325 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency 19259.259259 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency 17543.396226 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.050166 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.050166 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41555 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41555 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # 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number of overall misses +system.cpu3.dcache.overall_misses::total 265 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2569000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2569000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2080000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2080000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4649000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4649000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4649000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4649000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41712 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41712 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -600,34 +740,38 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses 157 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses 265 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 2098000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency 1756000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency 164000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency 3854000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003764 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.006988 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.830769 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate 0.004635 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate 0.004635 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13363.057325 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16259.259259 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 3037.037037 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu3.dcache.writebacks::total 1 # number of writebacks +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # 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number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1756000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3854000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 353.886259 # Cycle average of tags in use @@ -635,142 +779,231 @@ system.l2c.total_refs 1223 # To system.l2c.sampled_refs 434 # Sample count of references to valid blocks. system.l2c.avg_refs 2.817972 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 286.079543 # Average occupied blocks per context -system.l2c.occ_blocks::1 57.730360 # Average occupied blocks per context -system.l2c.occ_blocks::2 2.746586 # Average occupied blocks per context -system.l2c.occ_blocks::3 1.731874 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.597896 # Average occupied blocks per context -system.l2c.occ_percent::0 0.004365 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.000881 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::3 0.000026 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.000085 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 187 # 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Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005400 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 354 # 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number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits system.l2c.demand_hits::total 1226 # number of demand (read+write) hits -system.l2c.overall_hits::0 187 # number of overall hits -system.l2c.overall_hits::1 305 # number of overall hits -system.l2c.overall_hits::2 365 # number of overall hits -system.l2c.overall_hits::3 369 # number of overall hits +system.l2c.overall_hits::cpu0.inst 182 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 300 # number of overall hits +system.l2c.overall_hits::cpu1.data 5 # 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number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 450 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 12 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 12 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 15 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses -system.l2c.demand_misses::0 450 # number of demand (read+write) misses -system.l2c.demand_misses::1 89 # number of demand (read+write) misses -system.l2c.demand_misses::2 28 # number of demand (read+write) misses -system.l2c.demand_misses::3 25 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses system.l2c.demand_misses::total 592 # number of demand (read+write) misses -system.l2c.overall_misses::0 450 # number of overall misses -system.l2c.overall_misses::1 89 # number of overall misses -system.l2c.overall_misses::2 28 # number of overall misses -system.l2c.overall_misses::3 25 # number of overall misses +system.l2c.overall_misses::cpu0.inst 285 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 66 # number of overall misses +system.l2c.overall_misses::cpu1.data 23 # number of overall misses +system.l2c.overall_misses::cpu2.inst 12 # number of overall misses +system.l2c.overall_misses::cpu2.data 16 # number of overall misses +system.l2c.overall_misses::cpu3.inst 9 # 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number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 413000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 615000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 104000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 429000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 99000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 23330000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 52000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 52000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3.data 52000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 156000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5148000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 781000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 728000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 728000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7385000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 14822000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8580000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3416000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1194000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 615000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 832000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 429000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 827000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30715000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 14822000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3416000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1194000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 615000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 832000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 429000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 827000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30715000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 13 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1676 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 12 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 12 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 15 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 14 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 394 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 393 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 394 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 28 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 27 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 394 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 393 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 394 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 28 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 27 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1818 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.652416 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.195251 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.036939 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.028947 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.913554 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 3.933333 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.706436 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.225888 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.071247 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.063452 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 1.067023 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.706436 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.225888 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.071247 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.063452 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 1.067023 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 66467.236467 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 315270.270270 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 1666428.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 2120909.090909 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 4169075.169075 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 5571.428571 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 13000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 9750 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 9750 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 38071.428571 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 74595.959596 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 492333.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 527500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 527500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1621929.292929 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 68255.555556 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 345112.359551 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 1096964.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 1228600 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 2738932.200820 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 68255.555556 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 345112.359551 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 1096964.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 1228600 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 2738932.200820 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.615385 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.821429 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.592593 # 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mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |