diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux')
3 files changed, 3713 insertions, 3705 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index ebb41442e..37bdd5ca5 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,79 +1,73 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 107944000 # Number of ticks simulated -final_tick 107944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107900000 # Number of ticks simulated +final_tick 107900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128828 # Simulator instruction rate (inst/s) -host_op_rate 128828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13989470 # Simulator tick rate (ticks/s) -host_mem_usage 239356 # Number of bytes of host memory used -host_seconds 7.72 # Real time elapsed on the host -sim_insts 994048 # Number of instructions simulated -sim_ops 994048 # Number of ops (including micro ops) simulated +host_inst_rate 161691 # Simulator instruction rate (inst/s) +host_op_rate 161690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17527940 # Simulator tick rate (ticks/s) +host_mem_usage 308804 # Number of bytes of host memory used +host_seconds 6.16 # Real time elapsed on the host +sim_insts 995346 # Number of instructions simulated +sim_ops 995346 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5440 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 576 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42816 # Number of bytes read from this memory +system.physmem.bytes_read::total 42944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 85 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 9 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 669 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 214629808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 100200104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47432002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11858000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 4150300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7707700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2964500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7707700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 396650115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 214629808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47432002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 4150300 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2964500 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269176610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 214629808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 100200104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47432002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11858000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 4150300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7707700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2964500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7707700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 396650115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 670 # Number of read requests accepted +system.physmem.num_reads::total 671 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 214717331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100240964 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50417053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11862836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7710843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 5338276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7710843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 397998146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 214717331 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50417053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 5338276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270472660 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 214717331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100240964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50417053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11862836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7710843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 5338276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7710843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 397998146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 672 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 670 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 672 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42880 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 43008 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42880 # Total read bytes from the system interface side +system.physmem.bytesReadSys 43008 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 115 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 75 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 27 # Per bank write bursts +system.physmem.perBankRdBursts::2 30 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts system.physmem.perBankRdBursts::4 66 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts @@ -105,14 +99,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107916000 # Total gap between requests +system.physmem.totGap 107872000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 670 # Read request sizes (log2) +system.physmem.readPktSize::6 672 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -120,11 +114,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -216,319 +210,319 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 270.702703 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.430987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 234.776821 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 43 29.05% 29.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 26.35% 55.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25 16.89% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19 12.84% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 4.05% 89.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 4.05% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 3.38% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.35% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 2.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation -system.physmem.totQLat 6539750 # Total ticks spent queuing -system.physmem.totMemAccLat 19102250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9760.82 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.744966 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.953250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 233.682770 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 43 28.86% 28.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40 26.85% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25 16.78% 72.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17 11.41% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 5.37% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 4.70% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 2.68% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.34% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 2.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 149 # Bytes accessed per row activation +system.physmem.totQLat 7242000 # Total ticks spent queuing +system.physmem.totMemAccLat 19842000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3360000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10776.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28510.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 397.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29526.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 398.59 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 397.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 398.59 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.10 # Data bus utilization in percentage -system.physmem.busUtilRead 3.10 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.11 # Data bus utilization in percentage +system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 511 # Number of row buffer hits during reads +system.physmem.readRowHits 512 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.19 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 161068.66 # Average gap between requests -system.physmem.pageHitRate 76.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2761200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 160523.81 # Average gap between requests +system.physmem.pageHitRate 76.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2776800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 39247065 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 26461500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 76167750 # Total energy per rank (pJ) -system.physmem_0.averagePower 750.559832 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 46478250 # Time in different power states +system.physmem_0.actBackEnergy 34825860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30339750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75652080 # Total energy per rank (pJ) +system.physmem_0.averagePower 745.478401 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 52910500 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 54316750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 47852500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 30855240 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 33814500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 73943955 # Total energy per rank (pJ) -system.physmem_1.averagePower 728.745214 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 59727000 # Time in different power states +system.physmem_1.actBackEnergy 31297275 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 33426750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 73998240 # Total energy per rank (pJ) +system.physmem_1.averagePower 729.280213 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 59054500 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 42022000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 42666000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81450 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78581 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1205 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78182 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75500 # Number of BTB hits +system.cpu0.branchPred.lookups 81516 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78639 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1206 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 78220 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75547 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.569543 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 747 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 96.582715 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 751 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 215889 # number of cpu cycles simulated +system.cpu0.numCycles 215801 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20419 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 481443 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81450 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76247 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 165590 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2709 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 19984 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 481810 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81516 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76298 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165347 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2214 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 7225 # Number of cache lines fetched +system.cpu0.fetch.PendingTrapStallCycles 2206 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 7238 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 189580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.539524 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.227640 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 188895 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.550676 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.226315 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 32064 16.91% 16.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77818 41.05% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 818 0.43% 58.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1146 0.60% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 623 0.33% 59.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 72992 38.50% 97.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 703 0.37% 98.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 447 0.24% 98.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2969 1.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 31263 16.55% 16.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77878 41.23% 57.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 817 0.43% 58.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1146 0.61% 58.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 622 0.33% 59.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73043 38.67% 97.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 702 0.37% 98.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 447 0.24% 98.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2977 1.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 189580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.377277 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.230049 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 19697 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 152079 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 672 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1354 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 469796 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1354 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16409 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2266 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15970 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 152076 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1505 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 466337 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1001 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 319451 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 929999 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 702902 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 305355 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14096 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed +system.cpu0.fetch.rateDist::total 188895 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.377737 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.232659 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15795 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18848 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152228 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 669 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1355 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 470263 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1355 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16424 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2157 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15249 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152226 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1484 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 466822 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 991 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 319803 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 930944 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 703631 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 305659 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14144 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 901 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4587 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148758 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75265 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72519 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72258 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 390345 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.skidInsts 4515 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148895 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75333 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72583 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72320 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 390748 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 386997 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 13187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11208 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqInstsIssued 387435 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 13210 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11146 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 189580 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.041339 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.140292 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 188895 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.051060 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.134423 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 35140 18.54% 18.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4258 2.25% 20.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73622 38.83% 59.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73334 38.68% 98.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1646 0.87% 99.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 901 0.48% 99.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 423 0.22% 99.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 182 0.10% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 74 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34285 18.15% 18.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4265 2.26% 20.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73704 39.02% 59.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73391 38.85% 98.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1671 0.88% 99.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 904 0.48% 99.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 416 0.22% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 183 0.10% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 189580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 188895 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 91 32.73% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 84 30.22% 62.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 37.05% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 90 32.14% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 85 30.36% 62.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 105 37.50% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 164205 42.43% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 148197 38.29% 80.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74595 19.28% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164414 42.44% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 148348 38.29% 80.73% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74673 19.27% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 386997 # Type of FU issued -system.cpu0.iq.rate 1.792574 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 278 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000718 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 963876 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 404550 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 385100 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 387435 # Type of FU issued +system.cpu0.iq.rate 1.795335 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 280 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000723 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 964068 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 404976 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 385522 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 387275 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 387715 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71895 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71972 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2491 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2476 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1617 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1354 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2232 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 464248 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148758 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75265 # Number of dispatched store instructions +system.cpu0.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2123 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 464714 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148895 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75333 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 333 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1104 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 385946 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147890 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1051 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 331 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1444 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 386358 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 148024 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1077 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72936 # number of nop insts executed -system.cpu0.iew.exec_refs 222349 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76534 # Number of branches executed -system.cpu0.iew.exec_stores 74459 # Number of stores executed -system.cpu0.iew.exec_rate 1.787706 # Inst execution rate -system.cpu0.iew.wb_sent 385475 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 385100 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 228400 # num instructions producing a value -system.cpu0.iew.wb_consumers 231722 # num instructions consuming a value +system.cpu0.iew.exec_nop 72999 # number of nop insts executed +system.cpu0.iew.exec_refs 222560 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76623 # Number of branches executed +system.cpu0.iew.exec_stores 74536 # Number of stores executed +system.cpu0.iew.exec_rate 1.790344 # Inst execution rate +system.cpu0.iew.wb_sent 385902 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 385522 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 228646 # num instructions producing a value +system.cpu0.iew.wb_consumers 231982 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.783787 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.985664 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.786470 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.985620 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13801 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13812 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1205 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186928 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.409398 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.152220 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1206 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 186239 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.420760 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.150366 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 35407 18.94% 18.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75555 40.42% 59.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1920 1.03% 60.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 633 0.34% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 494 0.26% 60.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71651 38.33% 99.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 511 0.27% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 494 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34563 18.56% 18.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75593 40.59% 59.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1959 1.05% 60.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 634 0.34% 60.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 503 0.27% 60.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71729 38.51% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 522 0.28% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186928 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 450384 # Number of instructions committed -system.cpu0.commit.committedOps 450384 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186239 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 450840 # Number of instructions committed +system.cpu0.commit.committedOps 450840 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219907 # Number of memory references committed -system.cpu0.commit.loads 146267 # Number of loads committed +system.cpu0.commit.refs 220135 # Number of memory references committed +system.cpu0.commit.loads 146419 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75527 # Number of branches committed +system.cpu0.commit.branches 75603 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 303686 # Number of committed integer instructions. +system.cpu0.commit.int_insts 303990 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72259 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 158134 35.11% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72335 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 158286 35.11% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction @@ -557,625 +551,625 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 146351 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73640 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 146503 32.50% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73716 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction -system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 649458 # The number of ROB reads -system.cpu0.rob.rob_writes 931043 # The number of ROB writes +system.cpu0.commit.op_class_0::total 450840 # Class of committed instruction +system.cpu0.commit.bw_lim_events 486 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 649244 # The number of ROB reads +system.cpu0.rob.rob_writes 931981 # The number of ROB writes system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26309 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 378041 # Number of Instructions Simulated -system.cpu0.committedOps 378041 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.571073 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.571073 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.751090 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.751090 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 690199 # number of integer regfile reads -system.cpu0.int_regfile_writes 311415 # number of integer regfile writes +system.cpu0.idleCycles 26906 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 378421 # Number of Instructions Simulated +system.cpu0.committedOps 378421 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.570267 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.570267 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.753565 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.753565 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 690917 # number of integer regfile reads +system.cpu0.int_regfile_writes 311762 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 224240 # number of misc regfile reads +system.cpu0.misc_regfile_reads 224455 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 140.939988 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148370 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.011743 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 148491 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 867.660819 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 868.368421 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 140.939988 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275273 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275273 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.011743 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275414 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 598524 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 598524 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75399 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75399 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73059 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73059 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 599051 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 599051 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75429 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75429 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73130 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73130 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148458 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148458 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148458 # number of overall hits -system.cpu0.dcache.overall_hits::total 148458 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 514 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 514 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 539 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 539 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 148559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 148559 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148559 # number of overall hits +system.cpu0.dcache.overall_hits::total 148559 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 540 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 540 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1053 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1053 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1053 # number of overall misses -system.cpu0.dcache.overall_misses::total 1053 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17626915 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17626915 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36442515 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36442515 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 680000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 680000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 54069430 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 54069430 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 54069430 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 54069430 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75913 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75913 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73598 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73598 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1084 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1084 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1084 # number of overall misses +system.cpu0.dcache.overall_misses::total 1084 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16932500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16932500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35823993 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 35823993 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 460000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 460000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 52756493 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 52756493 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 52756493 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 52756493 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75969 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75969 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73674 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73674 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149511 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149511 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 149511 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 149511 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006771 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006771 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007324 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007324 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 149643 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149643 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 149643 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 149643 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007108 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007108 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007384 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007384 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007043 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007043 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34293.608949 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34293.608949 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67611.345083 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67611.345083 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 32380.952381 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 32380.952381 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 51347.986705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 51347.986705 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007244 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007244 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007244 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007244 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31356.481481 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31356.481481 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65852.928309 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 65852.928309 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21904.761905 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 21904.761905 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48668.351476 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 48668.351476 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48668.351476 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 48668.351476 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 79.692308 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 330 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 330 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 362 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 362 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 692 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 692 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 692 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 184 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 357 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 357 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 369 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 369 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 726 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 726 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 726 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 726 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6770753 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6770753 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8530978 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8530978 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 646500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 646500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15301731 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15301731 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15301731 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15301731 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002405 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002405 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6813000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6813000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8643000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8643000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 439000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 439000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15456000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15456000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15456000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15456000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002409 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002375 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002375 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002415 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002415 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36797.570652 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36797.570652 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48197.615819 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48197.615819 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 30785.714286 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 30785.714286 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37229.508197 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37229.508197 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 49388.571429 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 49388.571429 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20904.761905 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20904.761905 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43173.184358 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43173.184358 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43173.184358 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43173.184358 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 323 # number of replacements -system.cpu0.icache.tags.tagsinuse 240.188663 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6428 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 240.334366 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6439 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.469055 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.486971 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.188663 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469118 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.469118 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.334366 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469403 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.469403 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7839 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7839 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6428 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6428 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6428 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6428 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6428 # number of overall hits -system.cpu0.icache.overall_hits::total 6428 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses -system.cpu0.icache.overall_misses::total 797 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40514746 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40514746 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40514746 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40514746 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40514746 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40514746 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7225 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7225 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7225 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7225 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7225 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7225 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110311 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110311 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110311 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110311 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110311 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110311 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50834.060226 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 50834.060226 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 50834.060226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 50834.060226 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 7852 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7852 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6439 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6439 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6439 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6439 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6439 # number of overall hits +system.cpu0.icache.overall_hits::total 6439 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 799 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 799 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 799 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 799 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 799 # number of overall misses +system.cpu0.icache.overall_misses::total 799 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40829000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40829000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40829000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40829000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40829000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40829000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7238 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7238 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7238 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7238 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7238 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7238 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110390 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110390 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110390 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110390 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110390 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110390 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51100.125156 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51100.125156 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51100.125156 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51100.125156 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 182 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 182 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 182 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 182 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31043001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31043001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31043001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31043001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31043001 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31043001 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085121 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085121 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085121 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 50476.424390 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31621000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31621000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31621000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31621000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31621000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31621000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084968 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084968 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084968 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51416.260163 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52261 # Number of BP lookups -system.cpu1.branchPred.condPredicted 48386 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1341 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 44394 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 43169 # Number of BTB hits +system.cpu1.branchPred.lookups 53963 # Number of BP lookups +system.cpu1.branchPred.condPredicted 50167 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1346 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 46229 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 44971 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.240618 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.278764 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 927 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 162232 # number of cpu cycles simulated +system.cpu1.numCycles 162372 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 31153 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 288417 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52261 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 44075 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 122623 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2833 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 29926 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 299894 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 53963 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 45898 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 123960 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2845 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1159 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 21623 # Number of cache lines fetched +system.cpu1.fetch.PendingTrapStallCycles 1155 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 20576 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 156364 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.844523 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.218152 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::samples 156476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.916550 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.231802 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 56063 35.85% 35.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 50599 32.36% 68.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6236 3.99% 72.20% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3531 2.26% 74.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 937 0.60% 75.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 32564 20.83% 95.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1222 0.78% 96.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 843 0.54% 97.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4369 2.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 52995 33.87% 33.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51987 33.22% 67.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5834 3.73% 70.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3448 2.20% 73.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 958 0.61% 73.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 34873 22.29% 95.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1256 0.80% 96.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 838 0.54% 97.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4287 2.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 156364 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.322137 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.777806 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 18077 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 54814 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 78767 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3280 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1416 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 271927 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1416 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18807 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 25020 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13667 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 79411 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 18033 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 268621 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 15397 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 31 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 156476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.332342 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.846956 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18007 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50929 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 83026 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3082 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1422 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 283749 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1422 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18719 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22929 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13387 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 84356 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 15653 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 280426 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 13898 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 189765 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 514915 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 401460 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 175087 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14678 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 22640 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 74986 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 35614 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 35483 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 30428 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 223482 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6146 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 225009 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13593 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10743 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 680 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 156364 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.439008 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.385420 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 198372 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 540599 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 420692 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 183271 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15101 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1203 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1280 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 20103 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 79058 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 37890 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 37399 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 32713 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 233810 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5671 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 234514 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 14000 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11968 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 653 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156476 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.498722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.383815 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 59519 38.06% 38.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 20894 13.36% 51.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 35016 22.39% 73.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 34585 22.12% 95.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3417 2.19% 98.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1600 1.02% 99.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 882 0.56% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 240 0.15% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 211 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 56669 36.22% 36.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 19562 12.50% 48.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 37085 23.70% 72.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 36801 23.52% 95.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3420 2.19% 98.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1602 1.02% 99.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 884 0.56% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 239 0.15% 99.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 214 0.14% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 156364 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156476 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 92 27.88% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 29 8.79% 36.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 87 24.58% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 58 16.38% 40.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 59.04% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 110922 49.30% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 79078 35.14% 84.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 35009 15.56% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 114757 48.93% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 82569 35.21% 84.14% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37188 15.86% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 225009 # Type of FU issued -system.cpu1.iq.rate 1.386958 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 330 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001467 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 606728 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 243255 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 223369 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 234514 # Type of FU issued +system.cpu1.iq.rate 1.444301 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 354 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001510 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 625904 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 253521 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 232777 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 225339 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 234868 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 30296 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 32465 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2626 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2830 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1552 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1669 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1416 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7338 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 266019 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 165 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 74986 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 35614 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1422 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6958 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 277649 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 222 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 79058 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 37890 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1125 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1578 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 223948 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 74035 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 481 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1587 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 233397 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 77941 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1117 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 36391 # number of nop insts executed -system.cpu1.iew.exec_refs 108940 # number of memory reference insts executed -system.cpu1.iew.exec_branches 45914 # Number of branches executed -system.cpu1.iew.exec_stores 34905 # Number of stores executed -system.cpu1.iew.exec_rate 1.380418 # Inst execution rate -system.cpu1.iew.wb_sent 223649 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 223369 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 126652 # num instructions producing a value -system.cpu1.iew.wb_consumers 133295 # num instructions consuming a value +system.cpu1.iew.exec_nop 38168 # number of nop insts executed +system.cpu1.iew.exec_refs 115010 # number of memory reference insts executed +system.cpu1.iew.exec_branches 47577 # Number of branches executed +system.cpu1.iew.exec_stores 37069 # Number of stores executed +system.cpu1.iew.exec_rate 1.437421 # Inst execution rate +system.cpu1.iew.wb_sent 233106 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 232777 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 132706 # num instructions producing a value +system.cpu1.iew.wb_consumers 139339 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.376849 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.950163 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.433603 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.952397 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14380 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5466 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1341 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 153714 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.636819 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.057713 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14853 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5018 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1346 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 153761 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.708866 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.078798 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 64759 42.13% 42.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 42554 27.68% 69.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5173 3.37% 73.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6281 4.09% 77.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1529 0.99% 78.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 30355 19.75% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 785 0.51% 98.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 966 0.63% 99.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1312 0.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61362 39.91% 39.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 44235 28.77% 68.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5219 3.39% 72.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5854 3.81% 75.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1519 0.99% 76.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 32513 21.15% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 819 0.53% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 953 0.62% 99.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1287 0.84% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 153714 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 251602 # Number of instructions committed -system.cpu1.commit.committedOps 251602 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 153761 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 262757 # Number of instructions committed +system.cpu1.commit.committedOps 262757 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 106422 # Number of memory references committed -system.cpu1.commit.loads 72360 # Number of loads committed -system.cpu1.commit.membars 4751 # Number of memory barriers committed -system.cpu1.commit.branches 44778 # Number of branches committed +system.cpu1.commit.refs 112449 # Number of memory references committed +system.cpu1.commit.loads 76228 # Number of loads committed +system.cpu1.commit.membars 4303 # Number of memory barriers committed +system.cpu1.commit.branches 46487 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 173320 # Number of committed integer instructions. +system.cpu1.commit.int_insts 181057 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 35567 14.14% 14.14% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 104862 41.68% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 77111 30.65% 86.46% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 34062 13.54% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 37276 14.19% 14.19% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 108729 41.38% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 80531 30.65% 86.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 36221 13.78% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 417798 # The number of ROB reads -system.cpu1.rob.rob_writes 534614 # The number of ROB writes +system.cpu1.commit.op_class_0::total 262757 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1287 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 429498 # The number of ROB reads +system.cpu1.rob.rob_writes 557934 # The number of ROB writes system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 46290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 211284 # Number of Instructions Simulated -system.cpu1.committedOps 211284 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.767839 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.767839 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.302357 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.302357 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 386957 # number of integer regfile reads -system.cpu1.int_regfile_writes 181537 # number of integer regfile writes +system.cpu1.idleCycles 5896 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46085 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 221178 # Number of Instructions Simulated +system.cpu1.committedOps 221178 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.734124 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.734124 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.362168 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.362168 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 405088 # number of integer regfile reads +system.cpu1.int_regfile_writes 189742 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 110600 # number of misc regfile reads +system.cpu1.misc_regfile_reads 116634 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.579817 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 40184 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.592984 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 42361 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1435.142857 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1512.892857 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.579817 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049961 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.049961 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.592984 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049986 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.049986 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 311400 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 311400 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 43257 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 43257 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 33840 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 33840 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 77097 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 77097 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 77097 # number of overall hits -system.cpu1.dcache.overall_hits::total 77097 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 466 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 466 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 153 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 153 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses -system.cpu1.dcache.overall_misses::total 619 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9865731 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9865731 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3999011 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3999011 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 673507 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 673507 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13864742 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13864742 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13864742 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13864742 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 43723 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 43723 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 33993 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 33993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.tags.tag_accesses 326938 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 326938 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 44990 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 44990 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 35982 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 35982 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 80972 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 80972 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 80972 # number of overall hits +system.cpu1.dcache.overall_hits::total 80972 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 461 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 461 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 170 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 170 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 631 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 631 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 631 # number of overall misses +system.cpu1.dcache.overall_misses::total 631 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8707500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8707500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4222000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4222000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 652500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 652500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12929500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12929500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12929500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12929500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 45451 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 45451 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 36152 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 36152 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 77716 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 77716 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 77716 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 77716 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010658 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.010658 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004501 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004501 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.826087 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007965 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007965 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007965 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007965 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21171.096567 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 21171.096567 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26137.326797 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26137.326797 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11815.912281 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 11815.912281 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22398.613893 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 22398.613893 # average overall miss latency +system.cpu1.dcache.demand_accesses::cpu1.data 81603 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 81603 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 81603 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 81603 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010143 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010143 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004702 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004702 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007733 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007733 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007733 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007733 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18888.286334 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18888.286334 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24835.294118 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24835.294118 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11651.785714 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 11651.785714 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20490.491284 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20490.491284 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20490.491284 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20490.491284 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1184,106 +1178,106 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 344 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 344 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 303 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 303 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 62 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 365 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 365 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 365 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 365 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 275 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 275 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1943270 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1943270 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1707489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1707489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 587993 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 587993 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3650759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3650759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3650759 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3650759 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003820 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003820 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003177 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003177 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.826087 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003539 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003539 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11636.347305 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11636.347305 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15810.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15810.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10315.666667 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10315.666667 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1924500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1924500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 596500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 596500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3884000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3884000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3884000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3884000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003476 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003476 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002987 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002987 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003260 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003260 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003260 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003260 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.379747 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12180.379747 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18143.518519 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18143.518519 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10651.785714 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10651.785714 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14601.503759 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14601.503759 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14601.503759 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14601.503759 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 385 # number of replacements -system.cpu1.icache.tags.tagsinuse 83.683741 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21045 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 42.344064 # Average number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 85.488179 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19990 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.980000 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 83.683741 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.163445 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.163445 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id +system.cpu1.icache.tags.occ_blocks::cpu1.inst 85.488179 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.166969 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.166969 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 115 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22120 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22120 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21045 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21045 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21045 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21045 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21045 # number of overall hits -system.cpu1.icache.overall_hits::total 21045 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 578 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 578 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 578 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 578 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 578 # number of overall misses -system.cpu1.icache.overall_misses::total 578 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14251747 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 14251747 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 14251747 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 14251747 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 14251747 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 14251747 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21623 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21623 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21623 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21623 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21623 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21623 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026731 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.026731 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026731 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.026731 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026731 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.026731 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24657.001730 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24657.001730 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24657.001730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24657.001730 # average overall miss latency +system.cpu1.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.224609 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 21076 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21076 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 19990 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19990 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19990 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19990 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19990 # number of overall hits +system.cpu1.icache.overall_hits::total 19990 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 586 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 586 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 586 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 586 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 586 # number of overall misses +system.cpu1.icache.overall_misses::total 586 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14253000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14253000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14253000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14253000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14253000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14253000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20576 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20576 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20576 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20576 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20576 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20576 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028480 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.028480 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028480 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028480 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028480 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028480 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24322.525597 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24322.525597 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24322.525597 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24322.525597 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1292,410 +1286,410 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11245503 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11245503 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11245503 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11245503 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11245503 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11245503 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022985 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022985 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022985 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22626.766600 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 86 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 86 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 86 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 86 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 500 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 500 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 500 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11778500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11778500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11778500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11778500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11778500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11778500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024300 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024300 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024300 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23557 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23557 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51309 # Number of BP lookups -system.cpu2.branchPred.condPredicted 47950 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1280 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 43975 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 43053 # Number of BTB hits +system.cpu2.branchPred.lookups 40179 # Number of BP lookups +system.cpu2.branchPred.condPredicted 36730 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1284 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 32851 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 31814 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.903354 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 96.843323 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 891 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 161860 # number of cpu cycles simulated +system.cpu2.numCycles 162000 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 31583 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 282068 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51309 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 43939 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 125716 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2717 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 38502 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 208114 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 40179 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 32705 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 119095 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2725 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1207 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 22884 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 412 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 159877 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.764281 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.167875 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1151 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 29772 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 430 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 160123 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.299713 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.967894 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 59518 37.23% 37.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51095 31.96% 69.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 7306 4.57% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3438 2.15% 75.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 997 0.62% 76.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 31616 19.78% 96.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1254 0.78% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 769 0.48% 97.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3884 2.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 78817 49.22% 49.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 43234 27.00% 76.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 10666 6.66% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3447 2.15% 85.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1063 0.66% 85.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 17019 10.63% 96.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1193 0.75% 97.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 770 0.48% 97.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3914 2.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 159877 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.316996 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.742667 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17468 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 61085 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 76240 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3716 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1358 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 267722 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1358 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18170 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 29188 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12834 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 77782 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 20535 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 264399 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 18336 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 160123 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.248019 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.284654 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17927 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 88037 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 47537 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5250 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1362 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 193193 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1362 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18611 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 44936 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13295 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 49321 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 32588 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 189743 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 29082 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 12 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 185298 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 503121 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 392507 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 170476 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 14822 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1180 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 25168 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 73362 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 34382 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 35300 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 29228 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 218628 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6983 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 220497 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13773 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12313 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 159877 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.379166 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.379581 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 129905 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 340650 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 270570 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 115581 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 14324 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1221 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1285 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 37412 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 47453 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 19802 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 23979 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 14667 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 152040 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10334 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 157175 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13577 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11994 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 160123 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.981589 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.305622 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 63376 39.64% 39.64% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23374 14.62% 54.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 33553 20.99% 75.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 33206 20.77% 96.02% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3423 2.14% 98.16% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1623 1.02% 99.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 877 0.55% 99.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 230 0.14% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 215 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 83163 51.94% 51.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 32837 20.51% 72.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 19129 11.95% 84.39% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 18742 11.70% 96.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3350 2.09% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1588 0.99% 99.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 888 0.55% 99.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 204 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 159877 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 160123 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 86 23.69% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 68 18.73% 42.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 85 23.42% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 69 19.01% 42.42% # attempts to use FU when none available system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 108751 49.32% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 78120 35.43% 84.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 33626 15.25% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 82729 52.63% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 55347 35.21% 87.85% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 19099 12.15% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 220497 # Type of FU issued -system.cpu2.iq.rate 1.362270 # Inst issue rate +system.cpu2.iq.FU_type_0::total 157175 # Type of FU issued +system.cpu2.iq.rate 0.970216 # Inst issue rate system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001646 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 601287 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 239427 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 218768 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fu_busy_rate 0.002310 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 474890 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 175995 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 155491 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 220860 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 157538 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 28926 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 14398 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2863 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2822 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1691 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1616 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1358 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 8128 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 261616 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 204 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 73362 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 34382 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1362 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 11555 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 187117 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 206 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 47453 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 19802 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1131 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1045 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1500 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 219377 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 72164 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1120 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 462 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1028 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1490 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 156065 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 46210 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1110 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 36005 # number of nop insts executed -system.cpu2.iew.exec_refs 105679 # number of memory reference insts executed -system.cpu2.iew.exec_branches 45327 # Number of branches executed -system.cpu2.iew.exec_stores 33515 # Number of stores executed -system.cpu2.iew.exec_rate 1.355350 # Inst execution rate -system.cpu2.iew.wb_sent 219089 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 218768 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 123331 # num instructions producing a value -system.cpu2.iew.wb_consumers 129941 # num instructions consuming a value +system.cpu2.iew.exec_nop 24743 # number of nop insts executed +system.cpu2.iew.exec_refs 65197 # number of memory reference insts executed +system.cpu2.iew.exec_branches 33975 # Number of branches executed +system.cpu2.iew.exec_stores 18987 # Number of stores executed +system.cpu2.iew.exec_rate 0.963364 # Inst execution rate +system.cpu2.iew.wb_sent 155796 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 155491 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 82775 # num instructions producing a value +system.cpu2.iew.wb_consumers 89322 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.351588 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.949131 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.959821 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.926703 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14642 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 6361 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1280 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 157221 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.570534 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.031430 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14525 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9553 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1284 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 157478 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.095639 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.783689 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 69336 44.10% 44.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 41971 26.70% 70.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5151 3.28% 74.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7156 4.55% 78.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1534 0.98% 79.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 28975 18.43% 98.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 827 0.53% 98.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1310 0.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 92218 58.56% 58.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 30640 19.46% 78.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5207 3.31% 81.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 10311 6.55% 87.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1532 0.97% 88.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 14554 9.24% 98.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 759 0.48% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 956 0.61% 99.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1301 0.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 157221 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 246921 # Number of instructions committed -system.cpu2.commit.committedOps 246921 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 157478 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 172539 # Number of instructions committed +system.cpu2.commit.committedOps 172539 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 103190 # Number of memory references committed -system.cpu2.commit.loads 70499 # Number of loads committed -system.cpu2.commit.membars 5644 # Number of memory barriers committed -system.cpu2.commit.branches 44296 # Number of branches committed +system.cpu2.commit.refs 62817 # Number of memory references committed +system.cpu2.commit.loads 44631 # Number of loads committed +system.cpu2.commit.membars 8825 # Number of memory barriers committed +system.cpu2.commit.branches 32966 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 169605 # Number of committed integer instructions. +system.cpu2.commit.int_insts 117894 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 35083 14.21% 14.21% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 103004 41.72% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 76143 30.84% 86.76% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 32691 13.24% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 23742 13.76% 13.76% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 77155 44.72% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 53456 30.98% 89.46% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 18186 10.54% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 416888 # The number of ROB reads -system.cpu2.rob.rob_writes 525783 # The number of ROB writes -system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1983 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 46662 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 206194 # Number of Instructions Simulated -system.cpu2.committedOps 206194 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.784989 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.784989 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.273903 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.273903 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 376797 # number of integer regfile reads -system.cpu2.int_regfile_writes 176595 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 172539 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 342655 # The number of ROB reads +system.cpu2.rob.rob_writes 376773 # The number of ROB writes +system.cpu2.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1877 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 46457 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 139972 # Number of Instructions Simulated +system.cpu2.committedOps 139972 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.157374 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.157374 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.864025 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.864025 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 255225 # number of integer regfile reads +system.cpu2.int_regfile_writes 121437 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 107278 # number of misc regfile reads +system.cpu2.misc_regfile_reads 66781 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 24.051885 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 38880 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 23.055357 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 24315 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1340.689655 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 838.448276 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.051885 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.046976 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.046976 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.055357 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045030 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.045030 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 303893 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 303893 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 42781 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42781 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 32487 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 32487 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 75268 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 75268 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 75268 # number of overall hits -system.cpu2.dcache.overall_hits::total 75268 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 440 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 440 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 573 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 573 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 573 # number of overall misses -system.cpu2.dcache.overall_misses::total 573 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7341783 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7341783 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2962762 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2962762 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 594005 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 594005 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 10304545 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 10304545 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 10304545 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 10304545 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 43221 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 32620 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 32620 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 75841 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 75841 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 75841 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 75841 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010180 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.010180 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004077 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004077 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.802817 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007555 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007555 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007555 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007555 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16685.870455 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16685.870455 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22276.406015 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 22276.406015 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10421.140351 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 10421.140351 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17983.499127 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17983.499127 # average overall miss latency +system.cpu2.dcache.tags.tag_accesses 200189 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 200189 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 31354 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 31354 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 17953 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 17953 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 17 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 17 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 49307 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 49307 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 49307 # number of overall hits +system.cpu2.dcache.overall_hits::total 49307 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 441 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 441 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 151 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 151 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 65 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 65 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 592 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 592 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 592 # number of overall misses +system.cpu2.dcache.overall_misses::total 592 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 6519500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 6519500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3142000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3142000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 710000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 710000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 9661500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 9661500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 9661500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 9661500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 31795 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 31795 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 18104 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 18104 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 82 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 82 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 49899 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 49899 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 49899 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 49899 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.013870 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.013870 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008341 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.008341 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.792683 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.792683 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.011864 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.011864 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.011864 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.011864 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14783.446712 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 14783.446712 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20807.947020 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20807.947020 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10923.076923 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10923.076923 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 16320.101351 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 16320.101351 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 16320.101351 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 16320.101351 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1704,106 +1698,106 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 285 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 31 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 316 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 316 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 316 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 257 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 257 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1424773 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1424773 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1555988 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1555988 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 508495 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 508495 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2980761 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2980761 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2980761 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2980761 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003586 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003586 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003127 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003127 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003389 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003389 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.083871 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.083871 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15254.784314 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15254.784314 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8920.964912 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8920.964912 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 54 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 54 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 321 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 321 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 321 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 321 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 174 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 97 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 97 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 65 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1675000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1675000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1750000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1750000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 645000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 645000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3425000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3425000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3425000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3425000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.005473 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.005473 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005358 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005358 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.792683 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.792683 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005431 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.005431 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005431 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.005431 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9626.436782 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9626.436782 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18041.237113 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18041.237113 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 9923.076923 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 9923.076923 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12638.376384 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12638.376384 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12638.376384 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12638.376384 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.tags.replacements 384 # number of replacements -system.cpu2.icache.tags.tagsinuse 78.035025 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 22324 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 494 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.190283 # Average number of references to valid blocks. +system.cpu2.icache.tags.replacements 387 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.683777 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 29208 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 58.887097 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 78.035025 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.152412 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.152412 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.683777 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.145867 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.145867 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 23378 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 23378 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 22324 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 22324 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 22324 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 22324 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 22324 # number of overall hits -system.cpu2.icache.overall_hits::total 22324 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 560 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 560 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 560 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 560 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 560 # number of overall misses -system.cpu2.icache.overall_misses::total 560 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8454990 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8454990 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8454990 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8454990 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8454990 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8454990 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 22884 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 22884 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 22884 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 22884 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 22884 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 22884 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024471 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024471 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024471 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024471 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024471 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024471 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15098.196429 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15098.196429 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15098.196429 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15098.196429 # average overall miss latency +system.cpu2.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 30268 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 30268 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 29208 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 29208 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 29208 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 29208 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 29208 # number of overall hits +system.cpu2.icache.overall_hits::total 29208 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 564 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 564 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 564 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 564 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 564 # number of overall misses +system.cpu2.icache.overall_misses::total 564 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7822000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7822000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7822000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7822000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7822000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7822000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 29772 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 29772 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 29772 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 29772 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 29772 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 29772 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018944 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.018944 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018944 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.018944 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018944 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.018944 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13868.794326 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13868.794326 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13868.794326 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13868.794326 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13868.794326 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13868.794326 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1812,409 +1806,409 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 66 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 66 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 66 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 66 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 494 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 494 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 494 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 494 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 494 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 494 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6668508 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6668508 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6668508 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6668508 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6668508 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6668508 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021587 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021587 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021587 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13499.004049 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 496 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 496 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 496 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 496 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6709500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6709500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6709500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6709500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6709500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6709500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.016660 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.016660 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.016660 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13527.217742 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 49957 # Number of BP lookups -system.cpu3.branchPred.condPredicted 46526 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1263 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 42773 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 41661 # Number of BTB hits +system.cpu3.branchPred.lookups 59537 # Number of BP lookups +system.cpu3.branchPred.condPredicted 56113 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1261 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 52336 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 51268 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.400229 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.959340 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 894 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 161075 # number of cpu cycles simulated +system.cpu3.numCycles 161647 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 32422 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 272949 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 49957 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 42547 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 124988 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2685 # Number of cycles fetch has spent squashing -system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.icacheStallCycles 26901 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 335954 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 59537 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 52162 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 130682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2681 # Number of cycles fetch has spent squashing +system.cpu3.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1170 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 23669 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 411 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 159935 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.706625 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.149562 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps +system.cpu3.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 18139 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 423 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 160153 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 2.097707 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.240976 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 61940 38.73% 38.73% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 50129 31.34% 70.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7684 4.80% 74.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3433 2.15% 77.02% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1026 0.64% 77.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 29810 18.64% 96.30% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1265 0.79% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 775 0.48% 97.58% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3873 2.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 45773 28.58% 28.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 56940 35.55% 64.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 4846 3.03% 67.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3496 2.18% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1060 0.66% 70.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 42180 26.34% 96.34% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1201 0.75% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 768 0.48% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3889 2.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 159935 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.310147 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.694546 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17524 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 64435 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 72722 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 3902 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1342 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 258692 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1342 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18198 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 31170 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12771 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 73832 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 22612 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 255419 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 23 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 160153 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.368315 # Number of branch fetches per cycle +system.cpu3.fetch.rate 2.078319 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 16971 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 42083 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 97172 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 2577 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1340 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 322134 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1340 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 17645 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 17747 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12855 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 98257 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 12299 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 318864 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 10783 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 178600 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 483471 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 377749 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 164114 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14486 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1167 # count of serializing insts renamed +system.cpu3.rename.RenamedOperands 225541 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 621446 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 481213 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 211532 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14009 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1171 # count of serializing insts renamed system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 27248 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 70256 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 32624 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33902 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 27488 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 210626 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7365 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 213102 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13428 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11687 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 617 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 159935 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.332429 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.375890 # Number of insts issued each cycle +system.cpu3.rename.skidInsts 16730 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 92339 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 45060 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 43467 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 39931 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 267326 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 4600 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 267770 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12807 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10139 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 551 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 160153 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.671964 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.354316 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 65625 41.03% 41.03% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 24603 15.38% 56.42% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 31869 19.93% 76.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 31495 19.69% 96.03% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3384 2.12% 98.15% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1646 1.03% 99.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 234 0.15% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 48755 30.44% 30.44% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 16655 10.40% 40.84% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 44376 27.71% 68.55% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 43948 27.44% 95.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3484 2.18% 98.17% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1651 1.03% 99.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 159935 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 160153 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 83 23.71% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 58 16.57% 40.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 59.71% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 86 25.67% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 40 11.94% 37.61% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 105687 49.59% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 75490 35.42% 85.02% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 31925 14.98% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 128178 47.87% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 95149 35.53% 83.40% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 44443 16.60% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 213102 # Type of FU issued -system.cpu3.iq.rate 1.322999 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 350 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001642 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 586529 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 231462 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 211399 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 267770 # Type of FU issued +system.cpu3.iq.rate 1.656511 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 335 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001251 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 696028 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 284773 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 266078 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 213452 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 268105 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 27230 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 39763 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2740 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2450 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1547 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1342 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8471 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 252649 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 70256 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 32624 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1081 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1340 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 5357 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 316296 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 170 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 92339 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 45060 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu3.iew.memOrderViolationEvents 40 # Number of memory order violations system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1012 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1478 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 211973 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 69143 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1129 # Number of squashed instructions skipped in execute +system.cpu3.iew.predictedNotTakenIncorrect 1001 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1467 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 266621 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 91475 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1149 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34658 # number of nop insts executed -system.cpu3.iew.exec_refs 100953 # number of memory reference insts executed -system.cpu3.iew.exec_branches 44015 # Number of branches executed -system.cpu3.iew.exec_stores 31810 # Number of stores executed -system.cpu3.iew.exec_rate 1.315989 # Inst execution rate -system.cpu3.iew.wb_sent 211700 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 211399 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 118601 # num instructions producing a value -system.cpu3.iew.wb_consumers 125234 # num instructions consuming a value +system.cpu3.iew.exec_nop 44370 # number of nop insts executed +system.cpu3.iew.exec_refs 135810 # number of memory reference insts executed +system.cpu3.iew.exec_branches 53906 # Number of branches executed +system.cpu3.iew.exec_stores 44335 # Number of stores executed +system.cpu3.iew.exec_rate 1.649403 # Inst execution rate +system.cpu3.iew.wb_sent 266372 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 266078 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 153535 # num instructions producing a value +system.cpu3.iew.wb_consumers 160065 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.312426 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.947035 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.646044 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.959204 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14249 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6748 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1263 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 157342 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.514834 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.009338 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 13497 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 4049 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1261 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157643 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.920440 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.127029 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 72048 45.79% 45.79% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 40652 25.84% 71.63% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5170 3.29% 74.91% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7572 4.81% 79.73% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1532 0.97% 80.70% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 27266 17.33% 98.03% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 833 0.53% 98.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 969 0.62% 99.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1300 0.83% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 52663 33.41% 33.41% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 50442 32.00% 65.40% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5240 3.32% 68.73% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 4903 3.11% 71.84% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1534 0.97% 72.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 39716 25.19% 98.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 903 0.57% 98.58% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 957 0.61% 99.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1285 0.82% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 157342 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 238347 # Number of instructions committed -system.cpu3.commit.committedOps 238347 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157643 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 302744 # Number of instructions committed +system.cpu3.commit.committedOps 302744 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 98515 # Number of memory references committed -system.cpu3.commit.loads 67516 # Number of loads committed -system.cpu3.commit.membars 6034 # Number of memory barriers committed -system.cpu3.commit.branches 42994 # Number of branches committed +system.cpu3.commit.refs 133402 # Number of memory references committed +system.cpu3.commit.loads 89889 # Number of loads committed +system.cpu3.commit.membars 3344 # Number of memory barriers committed +system.cpu3.commit.branches 52826 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 163632 # Number of committed integer instructions. +system.cpu3.commit.int_insts 208356 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 33784 14.17% 14.17% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 100014 41.96% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 73550 30.86% 86.99% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 30999 13.01% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 43625 14.41% 14.41% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 122373 40.42% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 93233 30.80% 85.63% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 43513 14.37% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 408052 # The number of ROB reads -system.cpu3.rob.rob_writes 507784 # The number of ROB writes +system.cpu3.commit.op_class_0::total 302744 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1285 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 472013 # The number of ROB reads +system.cpu3.rob.rob_writes 634991 # The number of ROB writes system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1140 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 47445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 198529 # Number of Instructions Simulated -system.cpu3.committedOps 198529 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.811342 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.811342 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.232525 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.232525 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 362535 # number of integer regfile reads -system.cpu3.int_regfile_writes 170128 # number of integer regfile writes +system.cpu3.idleCycles 1494 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 46809 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 255775 # Number of Instructions Simulated +system.cpu3.committedOps 255775 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.631989 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.631989 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.582306 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.582306 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 467282 # number of integer regfile reads +system.cpu3.int_regfile_writes 217631 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 102551 # number of misc regfile reads +system.cpu3.misc_regfile_reads 137439 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.026048 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 37058 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.171664 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 49547 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1323.500000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1769.535714 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.026048 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.044973 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.044973 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.171664 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047210 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047210 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 291822 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 291822 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 41456 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41456 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 30794 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 30794 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 72250 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 72250 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 72250 # number of overall hits -system.cpu3.dcache.overall_hits::total 72250 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 440 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 440 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 577 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 577 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 577 # number of overall misses -system.cpu3.dcache.overall_misses::total 577 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7521134 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 7521134 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3020012 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3020012 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 589507 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 589507 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 10541146 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 10541146 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 10541146 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 10541146 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41896 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41896 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 30931 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 30931 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 72827 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 72827 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 72827 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 72827 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010502 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010502 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004429 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004429 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007923 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007923 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007923 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007923 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17093.486364 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17093.486364 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22043.883212 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 22043.883212 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10916.796296 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 10916.796296 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18268.883882 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18268.883882 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 381069 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 381069 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 51168 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 51168 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 43290 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 43290 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 10 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 94458 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 94458 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 94458 # number of overall hits +system.cpu3.dcache.overall_hits::total 94458 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 527 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 527 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 164 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 164 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 49 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 49 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 691 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 691 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 691 # number of overall misses +system.cpu3.dcache.overall_misses::total 691 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8076500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8076500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3222500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3222500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 607500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 607500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11299000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11299000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11299000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11299000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 51695 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 51695 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 43454 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 43454 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 59 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 59 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 95149 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 95149 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 95149 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 95149 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010194 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.010194 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003774 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003774 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830508 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.830508 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007262 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007262 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007262 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007262 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15325.426945 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15325.426945 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19649.390244 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19649.390244 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12397.959184 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 12397.959184 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16351.664255 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16351.664255 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16351.664255 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16351.664255 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2223,385 +2217,389 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 288 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 322 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 322 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 322 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 255 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 255 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1429011 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1429011 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1527238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1527238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 508493 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 508493 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2956249 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2956249 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2956249 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2956249 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003628 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003628 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003330 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003330 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003501 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003501 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9401.388158 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9401.388158 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14827.553398 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14827.553398 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9416.537037 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9416.537037 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 382 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 434 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 434 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 434 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 145 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 145 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 112 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 112 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 49 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1368000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1368000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1719500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1719500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 558500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 558500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3087500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3087500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3087500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3087500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002805 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002805 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002577 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002577 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830508 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830508 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002701 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.002701 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002701 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.002701 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9434.482759 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9434.482759 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15352.678571 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15352.678571 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11397.959184 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11397.959184 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12013.618677 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12013.618677 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12013.618677 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12013.618677 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.tags.replacements 387 # number of replacements -system.cpu3.icache.tags.tagsinuse 75.442206 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 23109 # Total number of references to valid blocks. +system.cpu3.icache.tags.replacements 388 # number of replacements +system.cpu3.icache.tags.tagsinuse 77.972544 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 17573 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 46.403614 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 35.287149 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 75.442206 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.147348 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.147348 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.972544 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.152290 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.152290 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 24167 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 24167 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 23109 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23109 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23109 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23109 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23109 # number of overall hits -system.cpu3.icache.overall_hits::total 23109 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 560 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 560 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 560 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 560 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 560 # number of overall misses -system.cpu3.icache.overall_misses::total 560 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7349496 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7349496 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7349496 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7349496 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7349496 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7349496 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 23669 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 23669 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 23669 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 23669 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 23669 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 23669 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023660 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.023660 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023660 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.023660 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023660 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.023660 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13124.100000 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13124.100000 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13124.100000 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13124.100000 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 18637 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 18637 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 17573 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 17573 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 17573 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 17573 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 17573 # number of overall hits +system.cpu3.icache.overall_hits::total 17573 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 566 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 566 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 566 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 566 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 566 # number of overall misses +system.cpu3.icache.overall_misses::total 566 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7887000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7887000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7887000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7887000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7887000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7887000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 18139 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 18139 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 18139 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 18139 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 18139 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 18139 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.031203 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.031203 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.031203 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.031203 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.031203 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.031203 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13934.628975 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13934.628975 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13934.628975 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13934.628975 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13934.628975 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13934.628975 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 68 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 68 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 68 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 68 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6152504 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6152504 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6152504 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6152504 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6152504 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6152504 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021040 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.021040 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.021040 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12354.425703 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6839000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6839000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6839000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6839000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6839000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6839000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.027455 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.027455 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.027455 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13732.931727 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13732.931727 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13732.931727 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13732.931727 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13732.931727 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13732.931727 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 421.791819 # Cycle average of tags in use -system.l2c.tags.total_refs 1669 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 536 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.113806 # Average number of references to valid blocks. +system.l2c.tags.tagsinuse 422.903421 # Cycle average of tags in use +system.l2c.tags.total_refs 2336 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 538 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.342007 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.783957 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 289.037601 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 57.982294 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 60.100309 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5.287110 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 5.207527 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.713016 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.004391 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.675614 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.784815 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 289.208824 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.009977 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 62.701446 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.295227 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.676960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 5.511844 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.714328 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004410 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004413 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000885 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000917 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000957 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000079 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006436 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 536 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000084 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006453 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 538 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008179 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 20118 # Number of tag accesses -system.l2c.tags.data_accesses 20118 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 251 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 414 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 481 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 491 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1669 # number of ReadReq hits +system.l2c.tags.age_task_id_blocks_1024::2 139 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008209 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 25512 # Number of tag accesses +system.l2c.tags.data_accesses 25512 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 251 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 412 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 486 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 485 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1634 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 251 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 414 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 481 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 486 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 485 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1669 # number of demand (read+write) hits +system.l2c.demand_hits::total 1666 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 251 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 414 # number of overall hits +system.l2c.overall_hits::cpu1.inst 412 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 481 # number of overall hits +system.l2c.overall_hits::cpu2.inst 486 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 491 # number of overall hits +system.l2c.overall_hits::cpu3.inst 485 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1669 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 364 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 13 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 551 # number of ReadReq misses +system.l2c.overall_hits::total 1666 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 75 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 364 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 88 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 10 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 13 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 475 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 364 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 88 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 13 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 682 # number of demand (read+write) misses +system.l2c.demand_misses::total 690 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 364 # number of overall misses system.l2c.overall_misses::cpu0.data 169 # number of overall misses -system.l2c.overall_misses::cpu1.inst 83 # number of overall misses +system.l2c.overall_misses::cpu1.inst 88 # number of overall misses system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 13 # number of overall misses +system.l2c.overall_misses::cpu2.inst 10 # number of overall misses system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 7 # number of overall misses +system.l2c.overall_misses::cpu3.inst 13 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 682 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 27791500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 6004250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 6396000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 553250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 1121000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 96750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 495500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 42540750 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8131000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1125500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 956000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 926750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11139250 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 27791500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 14135250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 6396000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1678750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 1121000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1052750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 495500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 1009250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 53680000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 27791500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 14135250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 6396000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1678750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 1121000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1052750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 495500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 1009250 # number of overall miss cycles -system.l2c.overall_miss_latency::total 53680000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 615 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 494 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 498 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2220 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::total 690 # number of overall misses +system.l2c.ReadExReq_miss_latency::cpu0.data 7927500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1298500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1175000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 1075000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11476000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 28062500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6697000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 853500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 993000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 36606000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 5987000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 551500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 82500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 96500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 6717500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 28062500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 13914500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 6697000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1850000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 853500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1257500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 993000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1171500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 54799500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 28062500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 13914500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6697000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1850000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 853500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1257500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 993000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1171500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 54799500 # number of overall miss cycles system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 615 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 500 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 496 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 498 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 2109 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 80 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 12 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 12 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 116 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 615 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 500 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 494 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 496 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2351 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2356 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 615 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 500 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 494 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 496 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2351 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.591870 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.167002 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.026316 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.248198 # miss rate for ReadReq accesses +system.l2c.overall_accesses::total 2356 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.961538 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.591870 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.176000 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.020161 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.026104 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.225225 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.591870 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.167002 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.176000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.026316 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.020161 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.014056 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.026104 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.290089 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.292869 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.591870 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.167002 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.176000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.026316 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.020161 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.014056 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.026104 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.290089 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76350.274725 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 80056.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77060.240964 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 79035.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86230.769231 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 96750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 70785.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 77206.442831 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 86500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86576.923077 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79666.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 77229.166667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 85032.442748 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 78709.677419 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 78709.677419 # average overall miss latency +system.l2c.overall_miss_rate::total 0.292869 # miss rate for overall accesses +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84335.106383 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 99884.615385 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 97916.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 89583.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 87603.053435 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77094.780220 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 76102.272727 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 85350 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 76384.615385 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 77065.263158 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79826.666667 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 78785.714286 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 96500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 79970.238095 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 77094.780220 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 82334.319527 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76102.272727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 92500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 85350 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 96730.769231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 76384.615385 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 90115.384615 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 79419.565217 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 77094.780220 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 82334.319527 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76102.272727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 92500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 85350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 96730.769231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 76384.615385 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 90115.384615 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 79419.565217 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2610,222 +2608,216 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 10 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 4 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 80 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 539 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 14 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 75 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 363 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 85 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 9 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 457 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 7 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 85 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 5 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 9 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 670 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 672 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 85 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 5 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 9 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 23217750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5067250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 5227250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 465250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 423750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 83750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 339500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 70000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 34894500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 391522 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 320018 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 303517 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 337019 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1352076 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6964500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 963500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 806000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 776750 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9510750 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 23217750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 12031750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 5227250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1428750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 423750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 889750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 339500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 846750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 44405250 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 23217750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 12031750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 5227250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1428750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 423750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 889750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 339500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 846750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 44405250 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.242793 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_misses::total 672 # number of overall MSHR misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 456500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 395500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 290997 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 417000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1559997 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6987500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1168500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1055000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 955000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 10166000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 24396000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5728000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 584500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 30708500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5237000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 481500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 72500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 86500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 5877500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 24396000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12224500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 5728000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1650000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1127500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 584500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 1041500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 46752000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 24396000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12224500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 5728000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1650000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1127500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 584500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 1041500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 46752000 # number of overall MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.170000 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.018072 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.216690 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.170000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.018072 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284985 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.170000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.018072 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284985 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67563.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66464.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 83750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 67900 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 64739.332096 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17796.454545 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.777778 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17853.941176 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 17737.842105 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.473684 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74090.425532 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74115.384615 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67166.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 64729.166667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72601.145038 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20750 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20815.789474 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20785.500000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20850 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.960000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74335.106383 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89884.615385 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 87916.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 79583.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 77603.053435 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67206.611570 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 67388.235294 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 67195.842451 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69826.666667 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 68785.714286 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69970.238095 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67206.611570 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72334.319527 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67388.235294 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 86730.769231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 80115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69571.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67206.611570 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72334.319527 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67388.235294 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86730.769231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 80115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69571.428571 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 539 # Transaction distribution -system.membus.trans_dist::ReadResp 538 # Transaction distribution -system.membus.trans_dist::UpgradeReq 276 # Transaction distribution -system.membus.trans_dist::UpgradeResp 76 # Transaction distribution -system.membus.trans_dist::ReadExReq 171 # Transaction distribution +system.membus.trans_dist::ReadResp 540 # Transaction distribution +system.membus.trans_dist::UpgradeReq 281 # Transaction distribution +system.membus.trans_dist::UpgradeResp 75 # Transaction distribution +system.membus.trans_dist::ReadExReq 168 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1731 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1731 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42816 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 240 # Total snoops (count) -system.membus.snoop_fanout::samples 986 # Request fanout histogram +system.membus.trans_dist::ReadSharedReq 541 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42944 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 243 # Total snoops (count) +system.membus.snoop_fanout::samples 990 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 986 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 990 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 986 # Request fanout histogram -system.membus.reqLayer0.occupancy 941000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 990 # Request fanout histogram +system.membus.reqLayer0.occupancy 926003 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3702674 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3714925 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.4 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2762 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2761 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2768 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 401 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 401 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1229 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::CleanEvict 670 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2109 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 660 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1469 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 988 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5872 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1144 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1136 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 350 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6560 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 150464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1012 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram +system.toL2Bus.pkt_size::total 150784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1022 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4941 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -2836,29 +2828,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3443 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4941 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1736971 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 994999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4941 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2489462 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 921499 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 532769 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 506002 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 762997 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 751497 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 438748 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 425967 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 744992 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 748987 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 415244 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 449462 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 747996 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 748992 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 406758 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 400481 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 833acaaf7..6ed919c46 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1398636 # Simulator instruction rate (inst/s) -host_op_rate 1398593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181097192 # Simulator tick rate (ticks/s) -host_mem_usage 299844 # Number of bytes of host memory used -host_seconds 0.48 # Real time elapsed on the host +host_inst_rate 1750110 # Simulator instruction rate (inst/s) +host_op_rate 1750047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226603798 # Simulator tick rate (ticks/s) +host_mem_usage 303668 # Number of bytes of host memory used +host_seconds 0.39 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -59,255 +59,7 @@ system.physmem.bw_total::cpu2.data 9486130 # To system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 423 # Transaction distribution -system.membus.trans_dist::ReadResp 423 # Transaction distribution -system.membus.trans_dist::UpgradeReq 273 # Transaction distribution -system.membus.trans_dist::UpgradeResp 80 # Transaction distribution -system.membus.trans_dist::ReadExReq 412 # Transaction distribution -system.membus.trans_dist::ReadExResp 136 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1108 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1108 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 15456 # Number of tag accesses -system.l2c.tags.data_accesses 15456 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 185 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 355 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 423 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 3 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 1 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.trans_dist::ReadReq 2179 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 711 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 718 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5733 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2867 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 2867 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2867 # Request fanout histogram system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 175415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -367,54 +119,6 @@ system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 175388 # Class of executed instruction -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits -system.cpu0.icache.overall_hits::total 174921 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. @@ -481,6 +185,54 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits +system.cpu0.icache.overall_hits::total 174921 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173297 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -539,54 +291,6 @@ system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 167432 # Class of executed instruction -system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits -system.cpu1.icache.overall_hits::total 167074 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses -system.cpu1.icache.overall_misses::total 358 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. @@ -650,6 +354,54 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets nan system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 278 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits +system.cpu1.icache.overall_hits::total 167074 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses +system.cpu1.icache.overall_misses::total 358 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173296 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -708,54 +460,6 @@ system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Cl system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 167367 # Class of executed instruction -system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits -system.cpu2.icache.overall_hits::total 167009 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses -system.cpu2.icache.overall_misses::total 358 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. @@ -820,6 +524,54 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets nan system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.tags.replacements 278 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits +system.cpu2.icache.overall_hits::total 167009 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses +system.cpu2.icache.overall_misses::total 358 # number of overall misses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173297 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -878,54 +630,6 @@ system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Cl system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 167304 # Class of executed instruction -system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits -system.cpu3.icache.overall_hits::total 166945 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses -system.cpu3.icache.overall_misses::total 359 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. @@ -989,5 +693,307 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets nan system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.tags.replacements 279 # number of replacements +system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits +system.cpu3.icache.overall_hits::total 166945 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses +system.cpu3.icache.overall_misses::total 359 # number of overall misses +system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use +system.l2c.tags.total_refs 2271 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.394299 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 23864 # Number of tag accesses +system.l2c.tags.data_accesses 23864 # Number of data accesses +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 185 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 296 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits +system.l2c.overall_hits::cpu2.inst 355 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits +system.l2c.overall_hits::cpu3.inst 358 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::total 559 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 282 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 62 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 3 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 1 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses +system.l2c.overall_misses::total 559 # number of overall misses +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadResp 423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 273 # Transaction distribution +system.membus.trans_dist::UpgradeResp 80 # Transaction distribution +system.membus.trans_dist::ReadExReq 412 # Transaction distribution +system.membus.trans_dist::ReadExResp 136 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1108 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1108 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1051 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 0 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3918 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 67fefac90..89934d478 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000260 # Number of seconds simulated -sim_ticks 260037500 # Number of ticks simulated -final_tick 260037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 260073500 # Number of ticks simulated +final_tick 260073500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 961598 # Simulator instruction rate (inst/s) -host_op_rate 961579 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 379344878 # Simulator tick rate (ticks/s) -host_mem_usage 302744 # Number of bytes of host memory used -host_seconds 0.69 # Real time elapsed on the host -sim_insts 659142 # Number of instructions simulated -sim_ops 659142 # Number of ops (including micro ops) simulated +host_inst_rate 1077387 # Simulator instruction rate (inst/s) +host_op_rate 1077364 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 425087977 # Simulator tick rate (ticks/s) +host_mem_usage 303432 # Number of bytes of host memory used +host_seconds 0.61 # Real time elapsed on the host +sim_insts 659129 # Number of instructions simulated +sim_ops 659129 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 70143729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40609527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 1722828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3691775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 15013219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5660722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 246118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3691775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 140779695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 70143729 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 1722828 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 15013219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 246118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 87125895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 70143729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40609527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1722828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3691775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 15013219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5660722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 246118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3691775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 140779695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 70134020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40603906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 3445180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3937348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 13288551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5413854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 246084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3691264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140760208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 70134020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 3445180 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 13288551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 246084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 87113835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 70134020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40603906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 3445180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3937348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 13288551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5413854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 246084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3691264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 140760208 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 520075 # number of cpu cycles simulated +system.cpu0.numCycles 520147 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 157392 # Number of instructions committed -system.cpu0.committedOps 157392 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108420 # Number of integer alu accesses +system.cpu0.committedInsts 157434 # Number of instructions committed +system.cpu0.committedOps 157434 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108448 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25835 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108420 # number of integer instructions +system.cpu0.num_conditional_control_insts 25842 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108448 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 313418 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110026 # number of times the integer registers were written +system.cpu0.num_int_register_reads 313502 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110054 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73430 # number of memory refs -system.cpu0.num_load_insts 48613 # Number of load instructions -system.cpu0.num_store_insts 24817 # Number of store instructions +system.cpu0.num_mem_refs 73451 # number of memory refs +system.cpu0.num_load_insts 48627 # Number of load instructions +system.cpu0.num_store_insts 24824 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 520074.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 520146.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26700 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23427 14.88% 14.88% # Class of executed instruction -system.cpu0.op_class::IntAlu 60513 38.43% 53.31% # Class of executed instruction +system.cpu0.Branches 26707 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23434 14.88% 14.88% # Class of executed instruction +system.cpu0.op_class::IntAlu 60527 38.43% 53.31% # Class of executed instruction system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction @@ -114,36 +114,36 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::MemRead 48697 30.93% 84.24% # Class of executed instruction -system.cpu0.op_class::MemWrite 24817 15.76% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 48711 30.93% 84.24% # Class of executed instruction +system.cpu0.op_class::MemWrite 24824 15.76% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 157454 # Class of executed instruction +system.cpu0.op_class::total 157496 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.649829 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 72898 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.650768 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 72919 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 436.514970 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 436.640719 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.649829 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284472 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284472 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.650768 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284474 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284474 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 293953 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 293953 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48433 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48433 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24583 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24583 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 294037 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 294037 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48447 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48447 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24590 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24590 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73016 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73016 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73016 # number of overall hits -system.cpu0.dcache.overall_hits::total 73016 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73037 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73037 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73037 # number of overall hits +system.cpu0.dcache.overall_hits::total 73037 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -154,46 +154,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 353 # system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4637996 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4637996 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6976000 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4613500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4613500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6976500 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11613996 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11613996 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11613996 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11613996 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48603 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48603 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24766 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 11590000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11590000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11590000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11590000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48617 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48617 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24773 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24773 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73369 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73369 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73369 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73369 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003498 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003498 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007389 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007389 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73390 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73390 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73390 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73390 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003497 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003497 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007387 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007387 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004811 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004811 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004811 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004811 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27282.329412 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27282.329412 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38120.218579 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38120.218579 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004810 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004810 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004810 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004810 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27138.235294 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27138.235294 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38122.950820 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38122.950820 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32900.838527 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32900.838527 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32832.861190 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32832.861190 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,88 +214,88 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4372004 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4372004 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6701500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6701500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11073504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11073504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11073504 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11073504 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003498 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003498 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007389 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4443500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4443500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6793500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6793500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11237000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11237000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11237000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11237000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003497 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003497 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007387 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007387 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004811 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004811 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25717.670588 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25717.670588 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36620.218579 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36620.218579 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12307.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12307.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004810 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004810 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26138.235294 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26138.235294 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37122.950820 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37122.950820 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.581030 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 156988 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 212.583222 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157030 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 336.162741 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 336.252677 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.581030 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415197 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.415197 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.583222 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415202 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.415202 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 157922 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 157922 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 156988 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 156988 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 156988 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 156988 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 156988 # number of overall hits -system.cpu0.icache.overall_hits::total 156988 # number of overall hits +system.cpu0.icache.tags.tag_accesses 157964 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 157964 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157030 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157030 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157030 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157030 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157030 # number of overall hits +system.cpu0.icache.overall_hits::total 157030 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18041500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18041500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18041500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18041500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18041500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18041500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 157455 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 157455 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 157455 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 157455 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 157455 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 157455 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002966 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002966 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002966 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002966 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002966 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002966 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38632.762313 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38632.762313 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38632.762313 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38632.762313 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18042500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18042500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18042500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18042500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18042500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18042500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 157497 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 157497 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 157497 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 157497 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 157497 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 157497 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002965 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002965 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002965 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002965 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002965 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002965 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38634.903640 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38634.903640 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38634.903640 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38634.903640 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -310,158 +310,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17341000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17341000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17341000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17341000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17341000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17341000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002966 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002966 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002966 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37132.762313 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17575500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17575500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17575500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17575500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17575500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17575500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002965 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002965 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002965 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37634.903640 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 520075 # number of cpu cycles simulated +system.cpu1.numCycles 520147 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 168980 # Number of instructions committed -system.cpu1.committedOps 168980 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 110320 # Number of integer alu accesses +system.cpu1.committedInsts 165571 # Number of instructions committed +system.cpu1.committedOps 165571 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 111555 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 33339 # number of instructions that are conditional controls -system.cpu1.num_int_insts 110320 # number of integer instructions +system.cpu1.num_conditional_control_insts 31016 # number of instructions that are conditional controls +system.cpu1.num_int_insts 111555 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 270098 # number of times the integer registers were read -system.cpu1.num_int_register_writes 102062 # number of times the integer registers were written +system.cpu1.num_int_register_reads 284333 # number of times the integer registers were read +system.cpu1.num_int_register_writes 108565 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 53149 # number of memory refs -system.cpu1.num_load_insts 40825 # Number of load instructions -system.cpu1.num_store_insts 12324 # Number of store instructions +system.cpu1.num_mem_refs 56707 # number of memory refs +system.cpu1.num_load_insts 41448 # Number of load instructions +system.cpu1.num_store_insts 15259 # Number of store instructions system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles -system.cpu1.num_busy_cycles 452347.998260 # Number of busy cycles -system.cpu1.not_idle_fraction 0.869775 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.130225 # Percentage of idle cycles -system.cpu1.Branches 34992 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25772 15.25% 15.25% # Class of executed instruction -system.cpu1.op_class::IntAlu 74368 44.00% 59.25% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::MemRead 56548 33.46% 92.71% # Class of executed instruction -system.cpu1.op_class::MemWrite 12324 7.29% 100.00% # Class of executed instruction +system.cpu1.num_busy_cycles 452419.998260 # Number of busy cycles +system.cpu1.not_idle_fraction 0.869793 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.130207 # Percentage of idle cycles +system.cpu1.Branches 32668 # Number of branches fetched +system.cpu1.op_class::No_OpClass 23452 14.16% 14.16% # Class of executed instruction +system.cpu1.op_class::IntAlu 74986 45.28% 59.44% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::MemRead 51906 31.34% 90.79% # Class of executed instruction +system.cpu1.op_class::MemWrite 15259 9.21% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 169012 # Class of executed instruction +system.cpu1.op_class::total 165603 # Class of executed instruction system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.995164 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 26990 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 899.666667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.035238 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 32753 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1129.413793 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.995164 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050772 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050772 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.035238 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050850 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050850 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 212815 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 212815 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 40655 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40655 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 12144 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 12144 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 52799 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 52799 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 52799 # number of overall hits -system.cpu1.dcache.overall_hits::total 52799 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 162 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 162 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses -system.cpu1.dcache.overall_misses::total 270 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2619475 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2619475 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1982498 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1982498 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 237000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4601973 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4601973 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4601973 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4601973 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40817 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40817 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 12252 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 12252 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 53069 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 53069 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 53069 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 53069 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003969 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003969 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008815 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008815 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005088 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005088 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005088 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005088 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16169.598765 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16169.598765 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18356.462963 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18356.462963 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4232.142857 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17044.344444 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17044.344444 # average overall miss latency +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 227042 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 227042 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 41284 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41284 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 15082 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 15082 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 56366 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 56366 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 56366 # number of overall hits +system.cpu1.dcache.overall_hits::total 56366 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 156 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 156 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 265 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 265 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 265 # number of overall misses +system.cpu1.dcache.overall_misses::total 265 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2383000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2383000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2068000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2068000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 251500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 251500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4451000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4451000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4451000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4451000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41440 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41440 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 15191 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 15191 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 56631 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 56631 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 56631 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 56631 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003764 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007175 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.007175 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.833333 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004679 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004679 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004679 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004679 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15275.641026 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15275.641026 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18972.477064 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18972.477064 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4572.727273 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4572.727273 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16796.226415 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16796.226415 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,99 +470,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2358525 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2358525 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1818502 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1818502 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 153000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4177027 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4177027 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4177027 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4177027 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003969 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003969 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008815 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008815 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005088 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005088 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14558.796296 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14558.796296 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16837.981481 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16837.981481 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2732.142857 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2227000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2227000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 196500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 196500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4186000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4186000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4186000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4186000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003764 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007175 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007175 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.833333 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004679 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004679 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14275.641026 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14275.641026 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17972.477064 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17972.477064 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3572.727273 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3572.727273 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 65.697365 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 168647 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 65.699918 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 165238 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 460.784153 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 451.469945 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.697365 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128315 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.128315 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.699918 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128320 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.128320 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 169379 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 169379 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 168647 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 168647 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 168647 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 168647 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 168647 # number of overall hits -system.cpu1.icache.overall_hits::total 168647 # number of overall hits +system.cpu1.icache.tags.tag_accesses 165970 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 165970 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 165238 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 165238 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 165238 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 165238 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 165238 # number of overall hits +system.cpu1.icache.overall_hits::total 165238 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5333988 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5333988 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5333988 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5333988 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5333988 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5333988 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 169013 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 169013 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 169013 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 169013 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 169013 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 169013 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002166 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002166 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002166 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14573.737705 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14573.737705 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14573.737705 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14573.737705 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5351500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5351500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5351500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5351500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5351500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5351500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 165604 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 165604 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 165604 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 165604 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 165604 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 165604 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002210 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002210 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002210 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14621.584699 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14621.584699 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14621.584699 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14621.584699 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,158 +577,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4778012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4778012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4778012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4778012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4778012 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4778012 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13054.677596 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4985500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4985500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4985500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4985500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4985500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4985500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13621.584699 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 520075 # number of cpu cycles simulated +system.cpu2.numCycles 520146 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 164869 # Number of instructions committed -system.cpu2.committedOps 164869 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110069 # Number of integer alu accesses +system.cpu2.committedInsts 160598 # Number of instructions committed +system.cpu2.committedOps 160598 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 111601 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31409 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110069 # number of integer instructions +system.cpu2.num_conditional_control_insts 28506 # number of instructions that are conditional controls +system.cpu2.num_int_insts 111601 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 276820 # number of times the integer registers were read -system.cpu2.num_int_register_writes 105549 # number of times the integer registers were written +system.cpu2.num_int_register_reads 294560 # number of times the integer registers were read +system.cpu2.num_int_register_writes 113655 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 54829 # number of memory refs -system.cpu2.num_load_insts 40701 # Number of load instructions -system.cpu2.num_store_insts 14128 # Number of store instructions -system.cpu2.num_idle_cycles 67985.001739 # Number of idle cycles -system.cpu2.num_busy_cycles 452089.998261 # Number of busy cycles -system.cpu2.not_idle_fraction 0.869278 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.130722 # Percentage of idle cycles -system.cpu2.Branches 33062 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23842 14.46% 14.46% # Class of executed instruction -system.cpu2.op_class::IntAlu 74244 45.02% 59.48% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::MemRead 52687 31.95% 91.43% # Class of executed instruction -system.cpu2.op_class::MemWrite 14128 8.57% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 59264 # number of memory refs +system.cpu2.num_load_insts 41473 # Number of load instructions +system.cpu2.num_store_insts 17791 # Number of store instructions +system.cpu2.num_idle_cycles 67981.871041 # Number of idle cycles +system.cpu2.num_busy_cycles 452164.128959 # Number of busy cycles +system.cpu2.not_idle_fraction 0.869302 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.130698 # Percentage of idle cycles +system.cpu2.Branches 30158 # Number of branches fetched +system.cpu2.op_class::No_OpClass 20943 13.04% 13.04% # Class of executed instruction +system.cpu2.op_class::IntAlu 75009 46.70% 59.73% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::MemRead 46887 29.19% 88.92% # Class of executed instruction +system.cpu2.op_class::MemWrite 17791 11.08% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 164901 # Class of executed instruction +system.cpu2.op_class::total 160630 # Class of executed instruction system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.767003 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30481 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.808310 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 37821 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1051.068966 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1304.172414 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.767003 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054232 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.054232 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.808310 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054313 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.054313 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 219531 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 219531 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 40534 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40534 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 13949 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 13949 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54483 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54483 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54483 # number of overall hits -system.cpu2.dcache.overall_hits::total 54483 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 159 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 159 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses -system.cpu2.dcache.overall_misses::total 267 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2767480 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2767480 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2022500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2022500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 237000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4789980 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4789980 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4789980 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4789980 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40693 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40693 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14057 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14057 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 54750 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 54750 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 54750 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 54750 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003907 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003907 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007683 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007683 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004877 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004877 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004877 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004877 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17405.534591 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17405.534591 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18726.851852 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 18726.851852 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4232.142857 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17940 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17940 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17940 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17940 # average overall miss latency +system.cpu2.dcache.tags.tag_accesses 237265 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 237265 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 41314 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 41314 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 17614 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 17614 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 58928 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 58928 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 58928 # number of overall hits +system.cpu2.dcache.overall_hits::total 58928 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 151 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 261 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 261 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 261 # number of overall misses +system.cpu2.dcache.overall_misses::total 261 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2416500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2416500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2235500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2235500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 248000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 248000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4652000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4652000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4652000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4652000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 41465 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 41465 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 17724 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 17724 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 65 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 59189 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 59189 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 59189 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 59189 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003642 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003642 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006206 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006206 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.846154 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.846154 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004410 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004410 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004410 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004410 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.311258 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16003.311258 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20322.727273 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20322.727273 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4509.090909 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4509.090909 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17823.754789 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17823.754789 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,99 +737,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2514020 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2514020 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1860500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1860500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 153000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4374520 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4374520 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4374520 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4374520 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003907 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003907 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007683 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007683 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004877 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004877 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15811.446541 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15811.446541 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17226.851852 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17226.851852 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2732.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2265500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2265500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2125500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2125500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4391000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4391000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4391000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4391000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003642 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003642 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006206 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006206 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.846154 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004410 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004410 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15003.311258 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15003.311258 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19322.727273 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19322.727273 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3509.090909 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3509.090909 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 70.145256 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164536 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 70.147178 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 160265 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 449.551913 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 437.882514 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.145256 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137002 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.137002 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.147178 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137006 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.137006 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165268 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165268 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 164536 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164536 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164536 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164536 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164536 # number of overall hits -system.cpu2.icache.overall_hits::total 164536 # number of overall hits +system.cpu2.icache.tags.tag_accesses 160997 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 160997 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 160265 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 160265 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 160265 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 160265 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 160265 # number of overall hits +system.cpu2.icache.overall_hits::total 160265 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7445997 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7445997 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7445997 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7445997 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7445997 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7445997 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 164902 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 164902 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 164902 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 164902 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 164902 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 164902 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20344.254098 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 20344.254098 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 20344.254098 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 20344.254098 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7437500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7437500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7437500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7437500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7437500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7437500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 160631 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 160631 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 160631 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 160631 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 160631 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 160631 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002279 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002279 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002279 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002279 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002279 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002279 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20321.038251 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 20321.038251 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 20321.038251 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 20321.038251 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -844,158 +844,158 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6894003 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6894003 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6894003 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6894003 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6894003 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6894003 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 18836.073770 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7071500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7071500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7071500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7071500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7071500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7071500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002279 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002279 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002279 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19321.038251 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 520075 # number of cpu cycles simulated +system.cpu3.numCycles 520146 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167901 # Number of instructions committed -system.cpu3.committedOps 167901 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 110672 # Number of integer alu accesses +system.cpu3.committedInsts 175526 # Number of instructions committed +system.cpu3.committedOps 175526 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 107877 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 32621 # number of instructions that are conditional controls -system.cpu3.num_int_insts 110672 # number of integer instructions +system.cpu3.num_conditional_control_insts 37833 # number of instructions that are conditional controls +system.cpu3.num_int_insts 107877 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 274378 # number of times the integer registers were read -system.cpu3.num_int_register_writes 104026 # number of times the integer registers were written +system.cpu3.num_int_register_reads 242346 # number of times the integer registers were read +system.cpu3.num_int_register_writes 89400 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 54219 # number of memory refs -system.cpu3.num_load_insts 41000 # Number of load instructions -system.cpu3.num_store_insts 13219 # Number of store instructions -system.cpu3.num_idle_cycles 68239.001738 # Number of idle cycles -system.cpu3.num_busy_cycles 451835.998262 # Number of busy cycles -system.cpu3.not_idle_fraction 0.868790 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.131210 # Percentage of idle cycles -system.cpu3.Branches 34277 # Number of branches fetched -system.cpu3.op_class::No_OpClass 25056 14.92% 14.92% # Class of executed instruction -system.cpu3.op_class::IntAlu 74547 44.39% 59.31% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::MemRead 55111 32.82% 92.13% # Class of executed instruction -system.cpu3.op_class::MemWrite 13219 7.87% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 46213 # number of memory refs +system.cpu3.num_load_insts 39592 # Number of load instructions +system.cpu3.num_store_insts 6621 # Number of store instructions +system.cpu3.num_idle_cycles 68237.870548 # Number of idle cycles +system.cpu3.num_busy_cycles 451908.129452 # Number of busy cycles +system.cpu3.not_idle_fraction 0.868810 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.131190 # Percentage of idle cycles +system.cpu3.Branches 39491 # Number of branches fetched +system.cpu3.op_class::No_OpClass 30262 17.24% 17.24% # Class of executed instruction +system.cpu3.op_class::IntAlu 73148 41.67% 58.90% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::MemRead 65527 37.32% 96.23% # Class of executed instruction +system.cpu3.op_class::MemWrite 6621 3.77% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 167933 # Class of executed instruction +system.cpu3.op_class::total 175558 # Class of executed instruction system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 26.810589 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 28657 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 988.172414 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 26.732151 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 15554 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 518.466667 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.810589 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052364 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.052364 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.732151 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.052211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 217093 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 217093 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 40832 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 40832 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 13038 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 13038 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 53870 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 53870 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 53870 # number of overall hits -system.cpu3.dcache.overall_hits::total 53870 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 160 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 160 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2513476 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2513476 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2024000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2024000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 244500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 244500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4537476 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4537476 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4537476 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4537476 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 40992 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 40992 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 13146 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 13146 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 54138 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 54138 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 54138 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 54138 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003903 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003903 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008215 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008215 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.816901 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004950 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004950 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004950 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004950 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15709.225000 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 15709.225000 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18740.740741 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 18740.740741 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4215.517241 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4215.517241 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 16930.880597 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 16930.880597 # average overall miss latency +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 185088 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 185088 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 39402 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 39402 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 6435 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 6435 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 45837 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 45837 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 45837 # number of overall hits +system.cpu3.dcache.overall_hits::total 45837 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 182 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 182 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 60 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 60 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 287 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 287 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 287 # number of overall misses +system.cpu3.dcache.overall_misses::total 287 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3223000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 3223000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1728500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1728500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 276500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 276500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4951500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4951500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4951500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4951500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 39584 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 39584 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 6540 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 6540 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 46124 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 46124 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 46124 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 46124 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004598 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.004598 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016055 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.016055 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.759494 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.759494 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006222 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.006222 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006222 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.006222 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17708.791209 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17708.791209 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16461.904762 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16461.904762 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4608.333333 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4608.333333 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17252.613240 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17252.613240 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1004,99 +1004,99 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2256524 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2256524 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1862000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1862000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 157500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 157500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4118524 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4118524 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4118524 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4118524 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003903 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003903 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008215 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008215 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004950 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004950 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14103.275000 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14103.275000 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17240.740741 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17240.740741 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2715.517241 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2715.517241 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 182 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 60 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 287 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 287 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3041000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3041000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1623500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1623500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 216500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 216500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4664500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4664500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4664500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4664500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004598 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004598 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016055 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016055 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.759494 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.759494 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.006222 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.006222 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16708.791209 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16708.791209 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15461.904762 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15461.904762 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3608.333333 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3608.333333 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 67.819588 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 167567 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 67.821849 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 175192 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 456.585831 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 477.362398 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.819588 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132460 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.132460 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.821849 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132465 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.132465 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 168301 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 168301 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 167567 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 167567 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 167567 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 167567 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 167567 # number of overall hits -system.cpu3.icache.overall_hits::total 167567 # number of overall hits +system.cpu3.icache.tags.tag_accesses 175926 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 175926 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 175192 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 175192 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 175192 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 175192 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 175192 # number of overall hits +system.cpu3.icache.overall_hits::total 175192 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5144490 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5144490 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5144490 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5144490 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5144490 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5144490 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167934 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167934 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167934 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167934 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167934 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167934 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002185 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002185 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002185 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002185 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002185 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002185 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14017.683924 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14017.683924 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14017.683924 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14017.683924 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5136500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5136500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5136500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5136500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5136500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5136500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 175559 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 175559 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 175559 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 175559 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 175559 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 175559 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002090 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002090 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002090 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002090 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002090 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002090 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13995.912807 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13995.912807 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13995.912807 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13995.912807 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1111,46 +1111,46 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4586010 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4586010 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4586010 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4586010 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4586010 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4586010 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002185 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002185 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002185 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12495.940054 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4769500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4769500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4769500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4769500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4769500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4769500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002090 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002090 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002090 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12995.912807 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.350598 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 349.351676 # Cycle average of tags in use +system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.890412 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.950361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.237281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.226273 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.814088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 47.344433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.154120 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.888026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.845603 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.890425 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.950289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.237156 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.367865 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.832949 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 47.203910 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.135421 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.888032 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.845628 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000722 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000097 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000720 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy @@ -1159,21 +1159,22 @@ system.l2c.tags.occ_task_id_blocks::1024 429 # Oc system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 15709 # Number of tag accesses -system.l2c.tags.data_accesses 15709 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 302 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.tags.tag_accesses 19677 # Number of tag accesses +system.l2c.tags.data_accesses 19677 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 302 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits @@ -1192,25 +1193,26 @@ system.l2c.overall_hits::cpu2.data 3 # nu system.l2c.overall_hits::cpu3.inst 358 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 64 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 64 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 9 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 372 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses @@ -1229,59 +1231,61 @@ system.l2c.overall_misses::cpu2.data 23 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 16 # number of overall misses system.l2c.overall_misses::total 592 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 14963000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3465000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 714500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 3356500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 420000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 103500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23584500 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 744000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 791500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 740000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7473000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 14963000 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 735000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 797000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 744000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7473500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14964000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 740000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3341500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 453500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 19499000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 3465000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 105000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 419000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 104500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 4093500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 14964000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 8662500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 714500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 848000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 3356500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1211500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 458000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 843500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 31057500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 14963000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 740000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 840000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 3341500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1216000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 453500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 848500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 31066000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 14964000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 714500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 848000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 3356500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1211500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 843500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 31057500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 740000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 840000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 3341500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1216000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 453500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 848500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 31066000 # number of overall miss cycles system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses @@ -1300,15 +1304,6 @@ system.l2c.overall_accesses::cpu2.data 26 # nu system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses @@ -1319,6 +1314,16 @@ system.l2c.ReadExReq_miss_rate::cpu1.data 1 # m system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.237548 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses @@ -1337,38 +1342,39 @@ system.l2c.overall_miss_rate::cpu2.data 0.884615 # mi system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52501.754386 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51035.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52445.312500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50888.888889 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 51750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52410 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52766.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52857.142857 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52626.760563 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53133.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 53142.857143 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52630.281690 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52505.263158 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 52857.142857 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52210.937500 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 50388.888889 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 52416.666667 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 52500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 52500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 52375 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 52250 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 52480.769231 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51035.714286 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 53000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 52445.312500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 52673.913043 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 50888.888889 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52718.750000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52461.993243 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 52210.937500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52869.565217 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52476.351351 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51035.714286 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 53000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 52445.312500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 52673.913043 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 50888.888889 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52718.750000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52461.993243 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 52210.937500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52869.565217 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52476.351351 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1377,107 +1383,98 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 10 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 8 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 61 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 11 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 14 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 54 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 1 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 354 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 66 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 7 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 76 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 61 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 23 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 16 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 54 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 22 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 61 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 16 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 54 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 22 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11542500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2673000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 283500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2475000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 324000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 17419500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1134000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 649996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 648000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 688500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3120496 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4009500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 575500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 611500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 571000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5767500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 11542500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6682500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 283500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 616000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 2475000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 935500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 40500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 611500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 23187000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 11542500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6682500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 283500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 616000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 2475000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 935500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 40500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 611500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 23187000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1194000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 765000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 850000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 479492 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3288492 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 595000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 647000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 604000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6053500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 12114000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 600000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2295500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 42500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 15052000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 2805000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 85000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 297500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 42500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 3230000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 12114000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 7012500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 600000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 680000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 2295500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 944500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 42500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 646500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24335500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 12114000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 7012500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 600000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 680000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 2295500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 944500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 42500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 646500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24335500 # number of overall MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses @@ -1488,68 +1485,79 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.181818 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.636364 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.640000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.640000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40510.465116 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40624.750000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40525.922078 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41107.142857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40766.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40785.714286 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40616.197183 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 42642.857143 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 42500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 42500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43590.181818 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42707.688312 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43133.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42630.281690 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42500 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42519.774011 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 430 # Transaction distribution system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 272 # Transaction distribution system.membus.trans_dist::UpgradeResp 77 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) @@ -1565,26 +1573,28 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 914 # Request fanout histogram -system.membus.reqLayer0.occupancy 679142 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 665648 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2961502 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2948008 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2217 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2217 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4812 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 846 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5316 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) @@ -1594,8 +1604,8 @@ system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1029 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2921 # Request fanout histogram +system.toL2Bus.snoops 1037 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3986 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1606,29 +1616,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 2921 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3986 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2921 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1466989 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 3986 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1998491 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 503996 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 503490 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 552488 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 431973 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 419983 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 550497 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 423980 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 412483 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 554490 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 428476 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 467954 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |