diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux')
3 files changed, 2811 insertions, 2810 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 6295c2feb..aa46bcce7 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000110 # Number of seconds simulated -sim_ticks 110344500 # Number of ticks simulated -final_tick 110344500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000111 # Number of seconds simulated +sim_ticks 110804500 # Number of ticks simulated +final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97195 # Simulator instruction rate (inst/s) -host_op_rate 97194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10306929 # Simulator tick rate (ticks/s) -host_mem_usage 249456 # Number of bytes of host memory used -host_seconds 10.71 # Real time elapsed on the host -sim_insts 1040548 # Number of instructions simulated -sim_ops 1040548 # Number of ops (including micro ops) simulated +host_inst_rate 110530 # Simulator instruction rate (inst/s) +host_op_rate 110530 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11745373 # Simulator tick rate (ticks/s) +host_mem_usage 249508 # Number of bytes of host memory used +host_seconds 9.43 # Real time elapsed on the host +sim_insts 1042724 # Number of instructions simulated +sim_ops 1042724 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42176 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 4672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 73 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 206480613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97440289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 46400138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11600034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1740005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7540022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3480010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7540022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 382221135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 206480613 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 46400138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1740005 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3480010 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 258100766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 206480613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97440289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 46400138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11600034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1740005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7540022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3480010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7540022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 382221135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 205623418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97035770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 5775939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7508720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42164353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11551877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3465563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7508720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380634361 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205623418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 5775939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42164353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3465563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 257029272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205623418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 660 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 42176 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 75 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis @@ -100,7 +100,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 110316500 # Total gap between requests +system.physmem.totGap 110776500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -115,9 +115,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -180,9 +180,9 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 282 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.796288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.984215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.500000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.723314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 317.555625 # Bytes accessed per row activation system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation @@ -197,402 +197,402 @@ system.physmem.bytesPerActivate::704 2 1.56% 91.41% # By system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 0.78% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 0.78% 98.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation -system.physmem.totQLat 3607500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17921250 # Sum of mem lat for all requests +system.physmem.totQLat 3818750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 18118750 # Sum of mem lat for all requests system.physmem.totBusLat 3300000 # Total cycles spent in databus access -system.physmem.totBankLat 11013750 # Total cycles spent in bank access -system.physmem.avgQLat 5465.91 # Average queueing delay per request -system.physmem.avgBankLat 16687.50 # Average bank access latency per request +system.physmem.totBankLat 11000000 # Total cycles spent in bank access +system.physmem.avgQLat 5785.98 # Average queueing delay per request +system.physmem.avgBankLat 16666.67 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27153.41 # Average memory access latency -system.physmem.avgRdBW 382.22 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27452.65 # Average memory access latency +system.physmem.avgRdBW 380.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 382.22 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 380.63 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.99 # Data bus utilization in percentage +system.physmem.busUtil 2.97 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 532 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 167146.21 # Average gap between requests -system.membus.throughput 382221135 # Throughput (bytes/s) +system.physmem.avgGap 167843.18 # Average gap between requests +system.membus.throughput 380634361 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 529 # Transaction distribution system.membus.trans_dist::ReadResp 528 # Transaction distribution -system.membus.trans_dist::UpgradeReq 284 # Transaction distribution -system.membus.trans_dist::UpgradeResp 75 # Transaction distribution -system.membus.trans_dist::ReadExReq 164 # Transaction distribution +system.membus.trans_dist::UpgradeReq 287 # Transaction distribution +system.membus.trans_dist::UpgradeResp 76 # Transaction distribution +system.membus.trans_dist::ReadExReq 163 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 1711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1711 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 906000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 6286926 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 5.7 # Layer utilization (%) -system.toL2Bus.throughput 1697085038 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2531 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2530 # Transaction distribution +system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 585 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 356 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 371 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5415 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 135488 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 51776 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1621980 # Layer occupancy (ticks) +system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2642498 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1437498 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1913498 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1155972 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1929492 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1158481 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 1.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1936496 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 1.8 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1165479 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) -system.cpu0.branchPred.lookups 82851 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80650 # Number of conditional branches predicted +system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 82992 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80180 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78131 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.444500 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 220690 # number of cpu cycles simulated +system.cpu0.numCycles 221610 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17257 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 491686 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82851 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78643 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161395 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13763 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1562 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 494 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 196421 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503225 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215279 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35026 17.83% 17.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79943 40.70% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.50% 59.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76047 38.72% 98.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2457 1.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 196421 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.375418 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.227949 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17908 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15370 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160419 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 285 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2439 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 488842 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2439 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18575 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 759 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14008 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160070 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 570 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 485981 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 199 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 332328 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 969157 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 969157 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 319407 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing +system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename +system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 970872 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3600 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155469 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78571 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75822 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75638 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 406410 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 403726 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 135 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 196421 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055412 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097532 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34004 17.31% 17.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4909 2.50% 19.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77804 39.61% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77117 39.26% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1569 0.80% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 649 0.33% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 196421 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 170720 42.29% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155014 38.40% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77992 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 403726 # Type of FU issued -system.cpu0.iq.rate 1.829381 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000550 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1004230 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 418093 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 401910 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued +system.cpu0.iq.rate 1.824931 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 403948 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75361 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2176 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2439 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 333 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 32 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 483693 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155469 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78571 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 342 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1448 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 402662 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 154684 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1064 # Number of squashed instructions skipped in execute +system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76372 # number of nop insts executed -system.cpu0.iew.exec_refs 232577 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79993 # Number of branches executed -system.cpu0.iew.exec_stores 77893 # Number of stores executed -system.cpu0.iew.exec_rate 1.824559 # Inst execution rate -system.cpu0.iew.wb_sent 402239 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 401910 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238133 # num instructions producing a value -system.cpu0.iew.wb_consumers 240585 # num instructions consuming a value +system.cpu0.iew.exec_nop 76515 # number of nop insts executed +system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed +system.cpu0.iew.exec_branches 80132 # Number of branches executed +system.cpu0.iew.exec_stores 78029 # Number of stores executed +system.cpu0.iew.exec_rate 1.820098 # Inst execution rate +system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238549 # num instructions producing a value +system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.821152 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989808 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12210 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 193982 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430442 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136125 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34427 17.75% 17.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79760 41.12% 58.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2402 1.24% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 529 0.27% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75180 38.76% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 442 0.23% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 241 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 308 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 193982 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 471462 # Number of instructions committed -system.cpu0.commit.committedOps 471462 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 472284 # Number of instructions committed +system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 230446 # Number of memory references committed -system.cpu0.commit.loads 153293 # Number of loads committed +system.cpu0.commit.refs 230857 # Number of memory references committed +system.cpu0.commit.loads 153567 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79040 # Number of branches committed +system.cpu0.commit.branches 79177 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 317738 # Number of committed integer instructions. +system.cpu0.commit.int_insts 318286 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 308 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 676185 # The number of ROB reads -system.cpu0.rob.rob_writes 969800 # The number of ROB writes +system.cpu0.rob.rob_reads 677374 # The number of ROB reads +system.cpu0.rob.rob_writes 971507 # The number of ROB writes system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24269 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 395606 # Number of Instructions Simulated -system.cpu0.committedOps 395606 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 395606 # Number of Instructions Simulated -system.cpu0.cpi 0.557853 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.557853 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.792587 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.792587 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 720352 # number of integer regfile reads -system.cpu0.int_regfile_writes 324661 # number of integer regfile writes +system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 396291 # Number of Instructions Simulated +system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated +system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 721592 # number of integer regfile reads +system.cpu0.int_regfile_writes 325227 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 234400 # number of misc regfile reads +system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 297 # number of replacements -system.cpu0.icache.tagsinuse 241.066229 # Cycle average of tags in use -system.cpu0.icache.total_refs 5081 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.655877 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 241.066229 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.470832 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.470832 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5081 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5081 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5081 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5081 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5081 # number of overall hits -system.cpu0.icache.overall_hits::total 5081 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 754 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 754 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 754 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 754 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 754 # number of overall misses -system.cpu0.icache.overall_misses::total 754 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 34643000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 34643000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 34643000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 34643000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 34643000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 34643000 # number of overall miss cycles +system.cpu0.icache.tags.replacements 297 # number of replacements +system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits +system.cpu0.icache.overall_hits::total 5079 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses +system.cpu0.icache.overall_misses::total 756 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129220 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.129220 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129220 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.129220 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129220 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.129220 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 45945.623342 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 45945.623342 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 45945.623342 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 45945.623342 # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,582 +601,583 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27004002 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27004002 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27004002 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27004002 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27004002 # 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number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156653 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156653 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156653 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006082 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006082 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006082 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006082 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31405.172414 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31405.172414 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65129.324771 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65129.324771 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19833.333333 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19833.333333 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50731.842271 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50731.842271 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 499 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.761905 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 220 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 590 # 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number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6035502 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6035502 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7873000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7873000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13908502 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13908502 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13908502 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13908502 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002347 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002347 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002269 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002269 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32448.935484 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32448.935484 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44988.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44988.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 58259 # Number of BP lookups -system.cpu1.branchPred.condPredicted 55591 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 52252 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 51480 # Number of BTB hits +system.cpu1.branchPred.lookups 43495 # Number of BP lookups +system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.522545 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 650 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 176870 # number of cpu cycles simulated +system.cpu1.numCycles 177681 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 24483 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 332703 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 58259 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 52130 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 112942 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3669 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 23224 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 755 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 15523 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 171052 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.945040 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.217476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 58110 33.97% 33.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 56330 32.93% 66.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4061 2.37% 69.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3192 1.87% 71.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 642 0.38% 71.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 43436 25.39% 96.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1285 0.75% 97.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 751 0.44% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 171052 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.329389 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.881060 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27575 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 21737 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 108940 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3156 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2318 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 329200 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2318 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28271 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 9057 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11940 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 106039 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 6101 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 326983 # Number of instructions processed by rename -system.cpu1.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 231035 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 638817 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 638817 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 218174 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12861 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1086 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1205 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8759 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 95375 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 46677 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 44840 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 41648 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 274055 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 4247 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 274319 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 86 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10569 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10360 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 171052 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.603717 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.300528 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 420697 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 55274 32.31% 32.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16462 9.62% 41.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 46955 27.45% 69.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 47561 27.80% 97.19% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3274 1.91% 99.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1158 0.68% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 171052 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 6.05% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 54 19.22% 25.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 74.73% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 130533 47.58% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 97787 35.65% 83.23% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 45999 16.77% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 274319 # Type of FU issued -system.cpu1.iq.rate 1.550964 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 281 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001024 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 720057 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 288914 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 272470 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued +system.cpu1.iq.rate 1.067177 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 274600 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 41423 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2326 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2318 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 743 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 324068 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 95375 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 46677 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1041 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 924 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1387 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 273134 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 94466 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1185 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 45766 # number of nop insts executed -system.cpu1.iew.exec_refs 140389 # number of memory reference insts executed -system.cpu1.iew.exec_branches 55097 # Number of branches executed -system.cpu1.iew.exec_stores 45923 # Number of stores executed -system.cpu1.iew.exec_rate 1.544264 # Inst execution rate -system.cpu1.iew.wb_sent 272765 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 272470 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 157153 # num instructions producing a value -system.cpu1.iew.wb_consumers 161823 # num instructions consuming a value +system.cpu1.iew.exec_nop 30958 # number of nop insts executed +system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed +system.cpu1.iew.exec_branches 40129 # Number of branches executed +system.cpu1.iew.exec_stores 26101 # Number of stores executed +system.cpu1.iew.exec_rate 1.060603 # Inst execution rate +system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 102456 # num instructions producing a value +system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.540510 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.971141 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12117 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 3751 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161408 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.932674 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.096378 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 51564 31.95% 31.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 53244 32.99% 64.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6086 3.77% 68.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 4696 2.91% 71.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 41954 25.99% 98.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 476 0.29% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 816 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161408 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 311949 # Number of instructions committed -system.cpu1.commit.committedOps 311949 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 212432 # Number of instructions committed +system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 138308 # Number of memory references committed -system.cpu1.commit.loads 93049 # Number of loads committed -system.cpu1.commit.membars 3038 # Number of memory barriers committed -system.cpu1.commit.branches 54264 # Number of branches committed +system.cpu1.commit.refs 83673 # Number of memory references committed +system.cpu1.commit.loads 58239 # Number of loads committed +system.cpu1.commit.membars 7917 # Number of memory barriers committed +system.cpu1.commit.branches 39308 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 214693 # Number of committed integer instructions. +system.cpu1.commit.int_insts 145097 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 484071 # The number of ROB reads -system.cpu1.rob.rob_writes 650455 # The number of ROB writes -system.cpu1.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5818 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43818 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 263856 # Number of Instructions Simulated -system.cpu1.committedOps 263856 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 263856 # Number of Instructions Simulated -system.cpu1.cpi 0.670328 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.670328 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.491808 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.491808 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 479823 # number of integer regfile reads -system.cpu1.int_regfile_writes 223101 # number of integer regfile writes +system.cpu1.rob.rob_reads 388816 # The number of ROB reads +system.cpu1.rob.rob_writes 452512 # The number of ROB writes +system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 174425 # Number of Instructions Simulated +system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated +system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 315718 # number of integer regfile reads +system.cpu1.int_regfile_writes 148477 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 141972 # number of misc regfile reads +system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 82.334562 # Cycle average of tags in use -system.cpu1.icache.total_refs 15036 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 35.378824 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 82.334562 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.160810 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.160810 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 15036 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15036 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15036 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15036 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15036 # number of overall hits -system.cpu1.icache.overall_hits::total 15036 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 487 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 487 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 487 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 487 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 487 # number of overall misses -system.cpu1.icache.overall_misses::total 487 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 12109000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 12109000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 12109000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 12109000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 12109000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 12109000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15523 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15523 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15523 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15523 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031373 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.031373 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031373 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.031373 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031373 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.031373 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24864.476386 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24864.476386 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24864.476386 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24864.476386 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 318 # number of replacements +system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits +system.cpu1.icache.overall_hits::total 25178 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses +system.cpu1.icache.overall_misses::total 478 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9721502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 9721502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9721502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 9721502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9721502 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 9721502 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027379 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027379 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027379 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22874.122353 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 26.168894 # Cycle average of tags in use -system.cpu1.dcache.total_refs 51272 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1831.142857 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 26.168894 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.051111 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.051111 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 52686 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 52686 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 45050 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 45050 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 97736 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 97736 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 97736 # number of overall hits -system.cpu1.dcache.overall_hits::total 97736 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 340 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 340 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 482 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 482 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 482 # number of overall misses -system.cpu1.dcache.overall_misses::total 482 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5254500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5254500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3040000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3040000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 532000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 532000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8294500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8294500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8294500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8294500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 53026 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 53026 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 45192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 45192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 98218 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 98218 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 98218 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 98218 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.006412 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.006412 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003142 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003142 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.835821 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004907 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004907 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004907 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004907 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15454.411765 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15454.411765 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21408.450704 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21408.450704 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9500 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9500 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17208.506224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17208.506224 # average overall miss latency +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits +system.cpu1.dcache.overall_hits::total 62948 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses +system.cpu1.dcache.overall_misses::total 451 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,473 +1186,473 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 185 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1346027 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1346027 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1452501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1452501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 420000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 420000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2798528 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2798528 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2798528 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2798528 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002923 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002923 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.835821 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002678 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002678 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 8684.045161 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 8684.045161 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13449.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13449.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7500 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7500 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 40256 # Number of BP lookups -system.cpu2.branchPred.condPredicted 37554 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1244 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 34216 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 33404 # Number of BTB hits +system.cpu2.branchPred.lookups 51236 # Number of BP lookups +system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.626841 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 656 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 176505 # number of cpu cycles simulated +system.cpu2.numCycles 177316 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 35945 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 212693 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 40256 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 34060 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 82824 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3666 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 45362 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 27473 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 251 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 174585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.218278 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.916616 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 91761 52.56% 52.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 44191 25.31% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 10007 5.73% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3161 1.81% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 734 0.42% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 19642 11.25% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1038 0.59% 97.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 777 0.45% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3274 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 174585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.228073 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.205025 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 44684 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 38236 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 73287 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 8707 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2345 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 209159 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2345 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 45347 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 25711 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11752 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 64880 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 17224 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 207132 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 18 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 141115 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 375802 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 375802 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 128666 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12449 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1089 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1217 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19740 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 53610 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 22854 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 26965 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 17848 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 166370 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 10183 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 172186 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 129 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 10670 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10572 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 174585 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.986259 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.235789 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 537620 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 89355 51.18% 51.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 33684 19.29% 70.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 23026 13.19% 83.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 23727 13.59% 97.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3246 1.86% 99.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1164 0.67% 99.78% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 273 0.16% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 174585 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 12 4.35% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 54 19.57% 23.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 76.09% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 88373 51.32% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 61586 35.77% 87.09% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 22227 12.91% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 172186 # Type of FU issued -system.cpu2.iq.rate 0.975530 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 276 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001603 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 519362 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 187269 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 170462 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued +system.cpu2.iq.rate 1.322842 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 172462 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 17592 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2439 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1401 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2345 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 684 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 204373 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 344 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 53610 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 22854 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 451 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 900 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1351 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 171090 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 52536 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1096 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 27820 # number of nop insts executed -system.cpu2.iew.exec_refs 74679 # number of memory reference insts executed -system.cpu2.iew.exec_branches 36982 # Number of branches executed -system.cpu2.iew.exec_stores 22143 # Number of stores executed -system.cpu2.iew.exec_rate 0.969321 # Inst execution rate -system.cpu2.iew.wb_sent 170734 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 170462 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 91387 # num instructions producing a value -system.cpu2.iew.wb_consumers 96059 # num instructions consuming a value +system.cpu2.iew.exec_nop 38706 # number of nop insts executed +system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed +system.cpu2.iew.exec_branches 47927 # Number of branches executed +system.cpu2.iew.exec_stores 36792 # Number of stores executed +system.cpu2.iew.exec_rate 1.316311 # Inst execution rate +system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131730 # num instructions producing a value +system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.965763 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.951363 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12267 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9515 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1244 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 164914 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.164777 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.788510 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 91274 55.35% 55.35% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 35097 21.28% 76.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6075 3.68% 80.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 10441 6.33% 86.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1560 0.95% 87.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 18154 11.01% 98.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 495 0.30% 98.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 812 0.49% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 164914 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 192088 # Number of instructions committed -system.cpu2.commit.committedOps 192088 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 264916 # Number of instructions committed +system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 72624 # Number of memory references committed -system.cpu2.commit.loads 51171 # Number of loads committed -system.cpu2.commit.membars 8798 # Number of memory barriers committed -system.cpu2.commit.branches 36206 # Number of branches committed +system.cpu2.commit.refs 112806 # Number of memory references committed +system.cpu2.commit.loads 76707 # Number of loads committed +system.cpu2.commit.membars 5024 # Number of memory barriers committed +system.cpu2.commit.branches 47088 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 130952 # Number of committed integer instructions. +system.cpu2.commit.int_insts 182014 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 367870 # The number of ROB reads -system.cpu2.rob.rob_writes 411061 # The number of ROB writes -system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1920 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44183 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 156297 # Number of Instructions Simulated -system.cpu2.committedOps 156297 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 156297 # Number of Instructions Simulated -system.cpu2.cpi 1.129292 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.129292 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.885510 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.885510 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 282509 # number of integer regfile reads -system.cpu2.int_regfile_writes 133289 # number of integer regfile writes +system.cpu2.rob.rob_reads 437936 # The number of ROB reads +system.cpu2.rob.rob_writes 557643 # The number of ROB writes +system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 222015 # Number of Instructions Simulated +system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated +system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 403571 # number of integer regfile reads +system.cpu2.int_regfile_writes 188531 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 76201 # number of misc regfile reads +system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.replacements 318 # number of replacements -system.cpu2.icache.tagsinuse 76.657940 # Cycle average of tags in use -system.cpu2.icache.total_refs 26999 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 63.081776 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 76.657940 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.149723 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.149723 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 26999 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 26999 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 26999 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 26999 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 26999 # number of overall hits -system.cpu2.icache.overall_hits::total 26999 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 474 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 474 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 474 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 474 # number of overall misses -system.cpu2.icache.overall_misses::total 474 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6632500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6632500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6632500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6632500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6632500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6632500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 27473 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 27473 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 27473 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 27473 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 27473 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 27473 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.017253 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.017253 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.017253 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.017253 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.017253 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.017253 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13992.616034 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13992.616034 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13992.616034 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13992.616034 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked +system.cpu2.icache.tags.replacements 317 # number of replacements +system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits +system.cpu2.icache.overall_hits::total 19274 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses +system.cpu2.icache.overall_misses::total 493 # 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number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19767 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024941 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024941 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024941 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024941 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024941 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024941 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # 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number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 189 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 189 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 189 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1142519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1142519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1333500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1333500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 425000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 425000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2476019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2476019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2476019 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2476019 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004609 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004609 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004724 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004724 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.760563 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.760563 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004653 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004653 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7096.391304 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7096.391304 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13202.970297 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13202.970297 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7870.370370 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7870.370370 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 182 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 216 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 216 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 52069 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49356 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1283 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 46005 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 45233 # Number of BTB hits +system.cpu3.branchPred.lookups 56317 # Number of BP lookups +system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.321922 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 642 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 176161 # number of cpu cycles simulated +system.cpu3.numCycles 176970 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 28821 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 290359 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 52069 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45875 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 102938 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3745 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 32453 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7327 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 20536 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 174715 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.661901 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.131946 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 71777 41.08% 41.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 52540 30.07% 71.15% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6531 3.74% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3210 1.84% 76.73% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 677 0.39% 77.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 34730 19.88% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1243 0.71% 97.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 745 0.43% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3262 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 174715 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.295576 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.648259 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 34404 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 28518 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 96588 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5492 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2386 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 286754 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2386 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 35116 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 15951 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11812 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 91334 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 10789 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 284513 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 198512 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 543834 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 543834 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 185460 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 13052 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1098 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1218 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 13448 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 80352 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 37945 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 38583 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 32886 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 235223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6760 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 237671 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10910 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10900 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 576 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 174715 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.360335 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.308190 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 604346 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 69245 39.63% 39.63% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 23718 13.58% 53.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 38151 21.84% 75.04% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 38808 22.21% 97.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3275 1.87% 99.13% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1152 0.66% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 254 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 174715 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 17 5.94% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 59 20.63% 26.57% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 73.43% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 115348 48.53% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 85085 35.80% 84.33% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 37238 15.67% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 237671 # Type of FU issued -system.cpu3.iq.rate 1.349169 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 286 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001203 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 650461 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 252939 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 235820 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued +system.cpu3.iq.rate 1.478471 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 237957 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 32638 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2448 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2386 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 609 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 281506 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 80352 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 37945 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 925 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 236476 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 79331 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 39523 # number of nop insts executed -system.cpu3.iew.exec_refs 116486 # number of memory reference insts executed -system.cpu3.iew.exec_branches 48746 # Number of branches executed -system.cpu3.iew.exec_stores 37155 # Number of stores executed -system.cpu3.iew.exec_rate 1.342386 # Inst execution rate -system.cpu3.iew.wb_sent 236114 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 235820 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 133214 # num instructions producing a value -system.cpu3.iew.wb_consumers 137877 # num instructions consuming a value +system.cpu3.iew.exec_nop 43769 # number of nop insts executed +system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed +system.cpu3.iew.exec_branches 53091 # Number of branches executed +system.cpu3.iew.exec_stores 42613 # Number of stores executed +system.cpu3.iew.exec_rate 1.471764 # Inst execution rate +system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 148532 # num instructions producing a value +system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.338662 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.966180 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12531 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6184 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1283 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165002 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.630011 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.014402 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 67849 41.12% 41.12% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 46915 28.43% 69.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6084 3.69% 73.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7112 4.31% 77.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1576 0.96% 78.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 33196 20.12% 98.62% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 454 0.28% 98.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1000 0.61% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165002 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 268955 # Number of instructions committed -system.cpu3.commit.committedOps 268955 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 297438 # Number of instructions committed +system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 114381 # Number of memory references committed -system.cpu3.commit.loads 77904 # Number of loads committed -system.cpu3.commit.membars 5468 # Number of memory barriers committed -system.cpu3.commit.branches 47910 # Number of branches committed +system.cpu3.commit.refs 129728 # Number of memory references committed +system.cpu3.commit.loads 87775 # Number of loads committed +system.cpu3.commit.membars 4366 # Number of memory barriers committed +system.cpu3.commit.branches 52284 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 184410 # Number of committed integer instructions. +system.cpu3.commit.int_insts 204138 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 816 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 445085 # The number of ROB reads -system.cpu3.rob.rob_writes 565364 # The number of ROB writes -system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1446 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 224789 # Number of Instructions Simulated -system.cpu3.committedOps 224789 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 224789 # Number of Instructions Simulated -system.cpu3.cpi 0.783673 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.783673 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.276043 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.276043 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 408025 # number of integer regfile reads -system.cpu3.int_regfile_writes 190344 # number of integer regfile writes +system.cpu3.rob.rob_reads 473500 # The number of ROB reads +system.cpu3.rob.rob_writes 621006 # The number of ROB writes +system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 249993 # Number of Instructions Simulated +system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated +system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 453881 # number of integer regfile reads +system.cpu3.int_regfile_writes 211087 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 118055 # number of misc regfile reads +system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.replacements 319 # number of replacements -system.cpu3.icache.tagsinuse 80.505037 # Cycle average of tags in use -system.cpu3.icache.total_refs 20059 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 46.648837 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 80.505037 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.157236 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.157236 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 20059 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 20059 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 20059 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 20059 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 20059 # number of overall hits -system.cpu3.icache.overall_hits::total 20059 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses -system.cpu3.icache.overall_misses::total 477 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6428500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6428500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6428500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6428500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6428500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6428500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 20536 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 20536 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 20536 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 20536 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 20536 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 20536 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023228 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.023228 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023228 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.023228 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023228 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.023228 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13476.939203 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13476.939203 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13476.939203 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13476.939203 # average overall miss latency +system.cpu3.icache.tags.replacements 319 # number of replacements +system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits +system.cpu3.icache.overall_hits::total 17724 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses +system.cpu3.icache.overall_misses::total 475 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2027,106 +2028,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 47 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 47 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 47 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 47 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5181004 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5181004 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5181004 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5181004 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5181004 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5181004 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020939 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.020939 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.020939 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12048.846512 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 24.780818 # Cycle average of tags in use -system.cpu3.dcache.total_refs 42491 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1517.535714 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 24.780818 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.048400 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.048400 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 46335 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 46335 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 36269 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 36269 # number of WriteReq hits +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # 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miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2135,87 +2136,87 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 182 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 215 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 215 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1065020 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1065020 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1284501 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1284501 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 432500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 432500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2349521 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2349521 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2349521 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2349521 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003385 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003385 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002884 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002884 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828571 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828571 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003166 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003166 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.632911 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.632911 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12233.342857 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12233.342857 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7456.896552 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7456.896552 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # 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number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # 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Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 3.476542 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.732205 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004346 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000919 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000083 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000053 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006361 # 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number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 173 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses @@ -2527,7 +2528,7 @@ system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -2535,59 +2536,59 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 56749.527410 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10563.437500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.986667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66630.319149 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65711.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62937.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58604.166667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 65465.648855 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 3469c3943..42fbfc6a4 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -86,15 +86,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 175415 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use -system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits @@ -128,15 +128,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use -system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -210,15 +210,15 @@ system.cpu1.num_idle_cycles 7873.724337 # Nu system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles -system.cpu1.icache.replacements 278 # number of replacements -system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use -system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 278 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits @@ -252,15 +252,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use -system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits @@ -332,15 +332,15 @@ system.cpu2.num_idle_cycles 7936.951217 # Nu system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.icache.replacements 278 # number of replacements -system.cpu2.icache.tagsinuse 74.781015 # Cycle average of tags in use -system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.replacements 278 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits @@ -374,15 +374,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 29.605505 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits @@ -454,15 +454,15 @@ system.cpu3.num_idle_cycles 8001.119846 # Nu system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles -system.cpu3.icache.replacements 279 # number of replacements -system.cpu3.icache.tagsinuse 72.874497 # Cycle average of tags in use -system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.replacements 279 # number of replacements +system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits @@ -496,15 +496,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 28.795404 # Cycle average of tags in use -system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits @@ -554,31 +554,31 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets nan system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 366.582542 # Cycle average of tags in use -system.l2c.total_refs 1220 # Total number of references to valid blocks. -system.l2c.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.897862 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005594 # Average percentage of cache occupancy +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index a78d037d9..4a2827ac8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 262793500 # Number of ticks simulated -final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262794500 # Number of ticks simulated +final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1490059 # Simulator instruction rate (inst/s) -host_op_rate 1490014 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 590046557 # Simulator tick rate (ticks/s) -host_mem_usage 244196 # Number of bytes of host memory used -host_seconds 0.45 # Real time elapsed on the host -sim_insts 663601 # Number of instructions simulated -sim_ops 663601 # Number of ops (including micro ops) simulated +host_inst_rate 146225 # Simulator instruction rate (inst/s) +host_op_rate 146224 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57909206 # Simulator tick rate (ticks/s) +host_mem_usage 244388 # Number of bytes of host memory used +host_seconds 4.54 # Real time elapsed on the host +sim_insts 663567 # Number of instructions simulated +sim_ops 663567 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory @@ -34,30 +34,30 @@ system.physmem.num_reads::cpu2.data 15 # Nu system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 139303293 # Throughput (bytes/s) +system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 139302763 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 430 # Transaction distribution system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 272 # Transaction distribution @@ -70,11 +70,11 @@ system.membus.tot_pkt_size_system.l2c.mem_side 36608 system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 36608 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 855296 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 5423500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 2.1 # Layer utilization (%) -system.toL2Bus.throughput 646591335 # Throughput (bytes/s) +system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.toL2Bus.throughput 646588875 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution @@ -85,11 +85,11 @@ system.toL2Bus.trans_dist::ReadExResp 429 # Tr system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 388 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 355 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 359 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 352 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 401 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes) @@ -102,26 +102,26 @@ system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 116032 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1474488 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1650489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1281961 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1651987 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1173486 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1177490 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 525587 # number of cpu cycles simulated +system.cpu0.numCycles 525589 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 158574 # Number of instructions committed @@ -140,18 +140,18 @@ system.cpu0.num_mem_refs 74021 # nu system.cpu0.num_load_insts 49007 # Number of load instructions system.cpu0.num_store_insts 25014 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 525587 # Number of busy cycles +system.cpu0.num_busy_cycles 525589 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.401760 # Cycle average of tags in use -system.cpu0.icache.total_refs 158170 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 338.693790 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.401760 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits @@ -164,12 +164,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 467 # system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18147500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18147500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18147500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18147500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18147500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18147500 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses @@ -182,12 +182,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38859.743041 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38859.743041 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38859.743041 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38859.743041 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -202,34 +202,34 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17213500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17213500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17213500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17213500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17213500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17213500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36859.743041 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.572033 # Cycle average of tags in use -system.cpu0.dcache.total_refs 73489 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 440.053892 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.572033 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits @@ -250,16 +250,16 @@ system.cpu0.dcache.demand_misses::cpu0.data 353 # system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4582500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4582500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6978000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6978000 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11560500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11560500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11560500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11560500 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) @@ -280,16 +280,16 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26955.882353 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26955.882353 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38131.147541 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38131.147541 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32749.291785 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32749.291785 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -310,16 +310,16 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237519 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237519 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6612000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6612000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10849519 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10849519 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10849519 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10849519 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses @@ -330,84 +330,84 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24926.582353 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24926.582353 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36131.147541 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36131.147541 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 525587 # number of cpu cycles simulated +system.cpu1.numCycles 525588 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 173389 # Number of instructions committed -system.cpu1.committedOps 173389 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107707 # Number of integer alu accesses +system.cpu1.committedInsts 163471 # Number of instructions committed +system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36848 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107707 # number of integer instructions +system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls +system.cpu1.num_int_insts 111731 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 245634 # number of times the integer registers were read -system.cpu1.num_int_register_writes 91167 # number of times the integer registers were written +system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read +system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 47028 # number of memory refs -system.cpu1.num_load_insts 39502 # Number of load instructions -system.cpu1.num_store_insts 7526 # Number of store instructions -system.cpu1.num_idle_cycles 69346.001736 # Number of idle cycles -system.cpu1.num_busy_cycles 456240.998264 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868060 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131940 # Percentage of idle cycles -system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.017443 # Cycle average of tags in use -system.cpu1.icache.total_refs 173056 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 472.830601 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.017443 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 173056 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 173056 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 173056 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 173056 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 173056 # number of overall hits -system.cpu1.icache.overall_hits::total 173056 # number of overall hits +system.cpu1.num_mem_refs 58020 # number of memory refs +system.cpu1.num_load_insts 41540 # Number of load instructions +system.cpu1.num_store_insts 16480 # Number of store instructions +system.cpu1.num_idle_cycles 69347.869793 # Number of idle cycles +system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles +system.cpu1.icache.tags.replacements 280 # number of replacements +system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits +system.cpu1.icache.overall_hits::total 163138 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # 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number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 173422 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 173422 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002110 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002110 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002110 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002110 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002110 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002110 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20606.557377 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20606.557377 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20606.557377 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20606.557377 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,94 +422,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806511 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806511 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806511 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6806511 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806511 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6806511 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002110 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002110 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002110 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18597.024590 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6808012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6808012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6808012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6808012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6808012 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6808012 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.692937 # Cycle average of tags in use -system.cpu1.dcache.total_refs 17380 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 579.333333 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.692937 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054088 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054088 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 39322 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39322 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7334 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7334 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 19 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 46656 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 46656 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 46656 # number of overall hits -system.cpu1.dcache.overall_hits::total 46656 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 172 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 172 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 278 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 278 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 278 # number of overall misses -system.cpu1.dcache.overall_misses::total 278 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3331000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3331000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2174000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2174000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 282000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 282000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5505000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5505000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5505000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5505000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39494 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39494 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7440 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7440 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 84 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 84 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 46934 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 46934 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 46934 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 46934 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004355 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004355 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014247 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.014247 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.773810 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.773810 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005923 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005923 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005923 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005923 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19366.279070 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19366.279070 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20509.433962 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20509.433962 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4338.461538 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4338.461538 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19802.158273 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19802.158273 # average overall miss latency +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits +system.cpu1.dcache.overall_hits::total 57685 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses +system.cpu1.dcache.overall_misses::total 263 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,114 +518,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 278 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2972539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2972539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 152000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4934539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4934539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4934539 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4934539 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004355 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004355 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014247 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014247 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.773810 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.773810 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005923 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005923 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17282.203488 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17282.203488 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2338.461538 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2338.461538 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 525587 # number of cpu cycles simulated +system.cpu2.numCycles 525588 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 164870 # Number of instructions committed -system.cpu2.committedOps 164870 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112982 # Number of integer alu accesses +system.cpu2.committedInsts 164866 # Number of instructions committed +system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 29953 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112982 # number of integer instructions +system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls +system.cpu2.num_int_insts 112988 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 294323 # number of times the integer registers were read -system.cpu2.num_int_register_writes 112883 # number of times the integer registers were written +system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read +system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59198 # number of memory refs -system.cpu2.num_load_insts 42166 # Number of load instructions -system.cpu2.num_store_insts 17032 # Number of store instructions -system.cpu2.num_idle_cycles 69603.001735 # Number of idle cycles -system.cpu2.num_busy_cycles 455983.998265 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867571 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132429 # Percentage of idle cycles -system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 67.624903 # Cycle average of tags in use -system.cpu2.icache.total_refs 164537 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 449.554645 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 67.624903 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 164537 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164537 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164537 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164537 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164537 # number of overall hits -system.cpu2.icache.overall_hits::total 164537 # number of overall hits +system.cpu2.num_mem_refs 59208 # number of memory refs +system.cpu2.num_load_insts 42171 # Number of load instructions +system.cpu2.num_store_insts 17037 # Number of store instructions +system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles +system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles +system.cpu2.icache.tags.replacements 280 # number of replacements +system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits +system.cpu2.icache.overall_hits::total 164533 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # 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average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -736,114 +736,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 158 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 52 # 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number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3522514 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3522514 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3522514 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003748 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003748 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006424 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.838710 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.838710 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004516 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004516 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11481.101266 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11481.101266 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15674.311927 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15674.311927 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2115.384615 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2115.384615 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1710500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1710500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3520019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520019 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3520019 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15550 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15550 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023 # 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number of instructions that are conditional controls -system.cpu3.num_int_insts 112266 # number of integer instructions +system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls +system.cpu3.num_int_insts 108218 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 286233 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109194 # number of times the integer registers were written +system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read +system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57176 # number of memory refs -system.cpu3.num_load_insts 41805 # Number of load instructions -system.cpu3.num_store_insts 15371 # Number of store instructions -system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles -system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles -system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 65.598360 # Cycle average of tags in use -system.cpu3.icache.total_refs 166434 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 453.498638 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 65.598360 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 166434 # 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Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits +system.cpu3.icache.overall_hits::total 176322 # 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number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 166801 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 166801 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 166801 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 166801 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 166801 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 166801 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002200 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002200 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002200 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002200 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002200 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002200 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14029.972752 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14029.972752 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14029.972752 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14029.972752 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # 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number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -858,94 +858,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4414501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4414501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4414501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4414501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4414501 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4414501 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002200 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002200 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002200 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12028.613079 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4412501 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4412501 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4412501 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4412501 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4412501 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4412501 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # 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number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 15196 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 56834 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 56834 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 56834 # number of overall hits -system.cpu3.dcache.overall_hits::total 56834 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2247500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2247500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1908500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1908500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 217500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 217500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4156000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4156000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4156000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4156000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41797 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41797 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 15305 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 15305 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 57102 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 57102 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 57102 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 57102 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003804 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003804 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007122 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.007122 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.828125 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.828125 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004693 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004693 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004693 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004693 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 14135.220126 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 14135.220126 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17509.174312 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 17509.174312 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4103.773585 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4103.773585 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 15507.462687 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 15507.462687 # average overall miss latency +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 45779 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 45779 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 45779 # number of overall hits +system.cpu3.dcache.overall_hits::total 45779 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 183 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses +system.cpu3.dcache.overall_misses::total 288 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2098500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2098500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 5254973 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 5254973 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 5254973 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 5254973 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -954,72 +954,72 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 159 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1924510 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1924510 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1690500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1690500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 111500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 111500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3615010 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3615010 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3615010 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3615010 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003804 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003804 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.007122 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.007122 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828125 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828125 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004693 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004693 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004693 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004693 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 12103.836478 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 12103.836478 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15509.174312 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15509.174312 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2103.773585 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2103.773585 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13488.843284 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13488.843284 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13488.843284 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13488.843284 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1888500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 349.045938 # Cycle average of tags in use -system.l2c.total_refs 1220 # Total number of references to valid blocks. -system.l2c.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.843823 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 231.790377 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 51.556644 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.123911 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.843759 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 1.030265 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.831019 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000014 # 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Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000014 # 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number of ReadReq hits @@ -1061,9 +1061,9 @@ system.l2c.ReadReq_misses::cpu3.inst 9 # nu system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses @@ -1088,38 +1088,38 @@ system.l2c.overall_misses::cpu2.data 16 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 16 # 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number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) @@ -1196,38 +1196,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.640000 # mi system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52373.684211 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52083.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49833.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # 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n system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses @@ -1301,15 +1301,15 @@ system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 764491 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40236.368421 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40035.642857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40278.161972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency @@ -1391,8 +1391,8 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency @@ -1400,8 +1400,8 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |