diff options
| author | Steve Reinhardt <stever@gmail.com> | 2013-09-28 15:25:17 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2013-09-28 15:25:17 -0400 |
| commit | fbc1feb39ac19379983ca714f4c7fadcd9fdabf6 (patch) | |
| tree | 59e49142d5930eb044e9fc09d94c5060a810d545 /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux | |
| parent | e5c319db43751f45b2bcca1d018fc39d4561ef9c (diff) | |
| download | gem5-fbc1feb39ac19379983ca714f4c7fadcd9fdabf6.tar.xz | |
tests: update reference outputs
Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes. There are a few stats.txt updates too, but
they are in the minority.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux')
7 files changed, 728 insertions, 434 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 49d73401e..717f44afc 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -27,7 +28,12 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[1] +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain [system.cpu0] type=DerivO3CPU @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu0.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -133,10 +138,10 @@ predType=tournament [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +152,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=SparcTLB size=64 @@ -422,10 +436,10 @@ opLat=3 [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -436,12 +450,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=SparcInterrupts @@ -463,7 +486,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -488,7 +511,7 @@ backComSize=5 branchPred=system.cpu1.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -537,6 +560,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -566,11 +590,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -578,10 +600,10 @@ predType=tournament [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -592,12 +614,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=SparcTLB size=64 @@ -867,10 +898,10 @@ opLat=3 [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -881,12 +912,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=SparcInterrupts @@ -914,7 +954,7 @@ backComSize=5 branchPred=system.cpu2.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -963,6 +1003,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -992,11 +1033,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -1004,10 +1043,10 @@ predType=tournament [system.cpu2.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -1018,12 +1057,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] +[system.cpu2.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.dtb] type=SparcTLB size=64 @@ -1293,10 +1341,10 @@ opLat=3 [system.cpu2.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -1307,12 +1355,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] +[system.cpu2.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.interrupts] type=SparcInterrupts @@ -1340,7 +1397,7 @@ backComSize=5 branchPred=system.cpu3.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -1389,6 +1446,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -1418,11 +1476,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -1430,10 +1486,10 @@ predType=tournament [system.cpu3.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -1444,12 +1500,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] +[system.cpu3.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.dtb] type=SparcTLB size=64 @@ -1719,10 +1784,10 @@ opLat=3 [system.cpu3.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -1733,12 +1798,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] +[system.cpu3.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.interrupts] type=SparcInterrupts @@ -1752,12 +1826,17 @@ size=64 [system.cpu3.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -1768,39 +1847,52 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[0] +mem_side=system.membus.slave[1] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false width=8 master=system.physmem.port -slave=system.l2c.mem_side system.system_port +slave=system.system_port system.l2c.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -1811,13 +1903,11 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -1825,3 +1915,7 @@ width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 3c88e0e72..f522c13b1 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,47 +3,47 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:04:14 -gem5 started Mar 26 2013 15:04:37 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:07:31 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 2] Got lock [Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 3, Thread 1] Got lock [Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 Iteration 3 completed -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 Iteration 4 completed [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 @@ -52,33 +52,33 @@ Iteration 5 completed [Iteration 6, Thread 3] Got lock [Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 Iteration 6 completed -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 Iteration 7 completed -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 105945500 because target called exit() +Exiting @ tick 110804500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index 606c05841..aa7fc3405 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -27,14 +28,18 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[1] +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -65,10 +74,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -79,22 +88,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=SparcTLB size=64 [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -105,12 +123,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=SparcInterrupts @@ -132,7 +159,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -146,9 +173,8 @@ uid=100 [system.cpu1] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true @@ -167,6 +193,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -179,10 +209,10 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -193,22 +223,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=SparcTLB size=64 [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -219,12 +258,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=SparcInterrupts @@ -241,9 +289,8 @@ type=ExeTracer [system.cpu2] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=2 do_checkpoint_insts=true do_quiesce=true @@ -262,6 +309,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -274,10 +325,10 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -288,22 +339,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] +[system.cpu2.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.dtb] type=SparcTLB size=64 [system.cpu2.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -314,12 +374,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] +[system.cpu2.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.interrupts] type=SparcInterrupts @@ -336,9 +405,8 @@ type=ExeTracer [system.cpu3] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=3 do_checkpoint_insts=true do_quiesce=true @@ -357,6 +425,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -369,10 +441,10 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -383,22 +455,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] +[system.cpu3.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.dtb] type=SparcTLB size=64 [system.cpu3.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -409,12 +490,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] +[system.cpu3.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.interrupts] type=SparcInterrupts @@ -428,12 +518,17 @@ size=64 [system.cpu3.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -444,42 +539,54 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[0] +mem_side=system.membus.slave[1] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port -slave=system.l2c.mem_side system.system_port +slave=system.system_port system.l2c.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false -range=0:1073741823 -zero=false +range=0:134217727 port=system.membus.master[0] [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index e013c98f2..a3bbfbbb8 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:09:53 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:09:34 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 42fbfc6a4..8179c99d9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1256528 # Simulator instruction rate (inst/s) -host_op_rate 1256465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162691956 # Simulator tick rate (ticks/s) -host_mem_usage 1160656 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host +host_inst_rate 170274 # Simulator instruction rate (inst/s) +host_op_rate 170274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22048637 # Simulator tick rate (ticks/s) +host_mem_usage 246052 # Number of bytes of host memory used +host_seconds 3.98 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory @@ -60,6 +60,184 @@ system.physmem.bw_total::total 407903588 # To system.membus.throughput 407903588 # Throughput (bytes/s) system.membus.data_through_bus 35776 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number 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+system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) system.toL2Bus.data_through_bus 166080 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -86,15 +264,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 175415 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits @@ -128,15 +306,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -210,15 +388,15 @@ system.cpu1.num_idle_cycles 7873.724337 # Nu system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles -system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 278 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits @@ -252,15 +430,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits @@ -332,15 +510,15 @@ system.cpu2.num_idle_cycles 7936.951217 # Nu system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 278 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits @@ -374,15 +552,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits @@ -454,15 +632,15 @@ system.cpu3.num_idle_cycles 8001.119846 # Nu system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles -system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 279 # number of replacements +system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits @@ -496,15 +674,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits @@ -554,183 +732,5 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets nan system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 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-system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 2 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index b4eef5d4b..51f67db18 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -27,14 +28,18 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[1] +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu0.tracer @@ -61,10 +67,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,22 +81,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=SparcTLB size=64 [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -101,12 +116,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=SparcInterrupts @@ -128,7 +152,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -142,9 +166,8 @@ uid=100 [system.cpu1] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true @@ -162,6 +185,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu1.tracer @@ -171,10 +195,10 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -185,22 +209,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=SparcTLB size=64 [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -211,12 +244,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=SparcInterrupts @@ -233,9 +275,8 @@ type=ExeTracer [system.cpu2] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=2 do_checkpoint_insts=true do_quiesce=true @@ -253,6 +294,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu2.tracer @@ -262,10 +304,10 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -276,22 +318,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] +[system.cpu2.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.dtb] type=SparcTLB size=64 [system.cpu2.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -302,12 +353,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] +[system.cpu2.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.interrupts] type=SparcInterrupts @@ -324,9 +384,8 @@ type=ExeTracer [system.cpu3] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=3 do_checkpoint_insts=true do_quiesce=true @@ -344,6 +403,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu3.tracer @@ -353,10 +413,10 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -367,22 +427,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] +[system.cpu3.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.dtb] type=SparcTLB size=64 [system.cpu3.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -393,12 +462,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] +[system.cpu3.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.interrupts] type=SparcInterrupts @@ -412,12 +490,17 @@ size=64 [system.cpu3.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -428,40 +511,46 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[0] +mem_side=system.membus.slave[1] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false width=8 master=system.physmem.port -slave=system.l2c.mem_side system.system_port +slave=system.system_port system.l2c.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -469,3 +558,7 @@ width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index adbb7069b..7a29b18d1 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -3,75 +3,75 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:04:14 -gem5 started Mar 26 2013 15:04:37 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:10:12 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 2, Thread 1] Got lock [Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 Iteration 2 completed [Iteration 3, Thread 1] Got lock [Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 Iteration 3 completed [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 Iteration 4 completed [Iteration 5, Thread 1] Got lock [Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 Iteration 5 completed [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 Iteration 8 completed [Iteration 9, Thread 1] Got lock [Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 Iteration 9 completed [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 @@ -81,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 262970500 because target called exit() +Exiting @ tick 262794500 because target called exit() |