diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
| commit | 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch) | |
| tree | 64b85031cb791a21af6059778384d358d992b817 /tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux | |
| parent | dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff) | |
| download | gem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz | |
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux')
9 files changed, 207 insertions, 225 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 74f1370ce..dd37fedf9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -31,22 +31,18 @@ system_port=system.membus.slave[1] [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb tracer workload -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu0.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -69,23 +65,15 @@ forwardComSize=5 fuPool=system.cpu0.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu0.interrupts isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -97,7 +85,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -126,6 +113,24 @@ workload=system.cpu0.workload dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side +[system.cpu0.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu0.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -458,7 +463,7 @@ egid=100 env= errout=cerr euid=100 -executable=/gem5/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -471,22 +476,18 @@ uid=100 [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb tracer -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu1.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -509,23 +510,15 @@ forwardComSize=5 fuPool=system.cpu1.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu1.interrupts isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -537,7 +530,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -566,6 +558,24 @@ workload=system.cpu0.workload dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side +[system.cpu1.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu1.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -892,22 +902,18 @@ type=ExeTracer [system.cpu2] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb tracer -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu2.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -930,23 +936,15 @@ forwardComSize=5 fuPool=system.cpu2.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu2.interrupts isa=system.cpu2.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu2.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -958,7 +956,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -987,6 +984,24 @@ workload=system.cpu0.workload dcache_port=system.cpu2.dcache.cpu_side icache_port=system.cpu2.icache.cpu_side +[system.cpu2.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu2.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -1313,22 +1328,18 @@ type=ExeTracer [system.cpu3] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb tracer -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu3.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -1351,23 +1362,15 @@ forwardComSize=5 fuPool=system.cpu3.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu3.interrupts isa=system.cpu3.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu3.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -1379,7 +1382,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -1408,6 +1410,24 @@ workload=system.cpu0.workload dcache_port=system.cpu3.dcache.cpu_side icache_port=system.cpu3.icache.cpu_side +[system.cpu3.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu3.dcache] type=BaseCache addr_ranges=0:18446744073709551615 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 4d35b5bd4..9fd6655b7 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 4 2013 21:16:54 -gem5 started Jan 4 2013 21:59:48 -gem5 executing on u200540 +gem5 compiled Jan 23 2013 15:49:24 +gem5 started Jan 23 2013 16:01:12 +gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index a08676b4f..3f4fe5ffb 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000105 # Nu sim_ticks 104832500 # Number of ticks simulated final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49068 # Simulator instruction rate (inst/s) -host_op_rate 49068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4970400 # Simulator tick rate (ticks/s) -host_mem_usage 237836 # Number of bytes of host memory used -host_seconds 21.09 # Real time elapsed on the host +host_inst_rate 81452 # Simulator instruction rate (inst/s) +host_op_rate 81452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8250764 # Simulator tick rate (ticks/s) +host_mem_usage 293492 # Number of bytes of host memory used +host_seconds 12.71 # Real time elapsed on the host sim_insts 1034907 # Number of instructions simulated sim_ops 1034907 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory @@ -215,18 +215,19 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 159035.66 # Average gap between requests +system.cpu0.branchPred.lookups 82004 # Number of BP lookups +system.cpu0.branchPred.condPredicted 79765 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 79291 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 77227 # Number of BTB hits +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 97.396930 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 516 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 209666 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 82004 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 79765 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 79291 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 77227 # Number of BTB hits -system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 516 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered @@ -690,17 +691,18 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29186.111111 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 52905 # Number of BP lookups +system.cpu1.branchPred.condPredicted 50239 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1268 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 46829 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 46139 # Number of BTB hits +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 98.526554 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu1.numCycles 174086 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 52905 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 50239 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1268 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 46829 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 46139 # Number of BTB hits -system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 659 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered @@ -1163,17 +1165,18 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11196.153846 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.branchPred.lookups 43658 # Number of BP lookups +system.cpu2.branchPred.condPredicted 40905 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1282 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 37514 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 36718 # Number of BTB hits +system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.branchPred.BTBHitPct 97.878125 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu2.numCycles 173761 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 43658 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 40905 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1282 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 37514 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 36718 # Number of BTB hits -system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target. -system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered @@ -1637,17 +1640,18 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9416.974170 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.branchPred.lookups 53689 # Number of BP lookups +system.cpu3.branchPred.condPredicted 50963 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1276 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 47522 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 46772 # Number of BTB hits +system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu3.branchPred.BTBHitPct 98.421784 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 661 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu3.numCycles 173451 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 53689 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 50963 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1276 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 47522 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 46772 # Number of BTB hits -system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 661 # Number of times the RAS was used to get a target. -system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index 6cfde7057..606c05841 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -15,6 +15,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,11 +31,11 @@ system_port=system.membus.slave[1] [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -43,6 +44,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -53,6 +55,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu0.tracer width=1 @@ -67,21 +70,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -98,21 +96,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -121,6 +114,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=SparcInterrupts +[system.cpu0.isa] +type=SparcISA + [system.cpu0.itb] type=SparcTLB size=64 @@ -136,7 +132,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -149,11 +145,11 @@ uid=100 [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=1 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -162,6 +158,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -172,6 +169,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu1.tracer width=1 @@ -186,21 +184,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -217,21 +210,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -240,6 +228,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=SparcInterrupts +[system.cpu1.isa] +type=SparcISA + [system.cpu1.itb] type=SparcTLB size=64 @@ -249,11 +240,11 @@ type=ExeTracer [system.cpu2] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=2 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -262,6 +253,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu2.interrupts +isa=system.cpu2.isa itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -272,6 +264,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu2.tracer width=1 @@ -286,21 +279,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port @@ -317,21 +305,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port @@ -340,6 +323,9 @@ mem_side=system.toL2Bus.slave[4] [system.cpu2.interrupts] type=SparcInterrupts +[system.cpu2.isa] +type=SparcISA + [system.cpu2.itb] type=SparcTLB size=64 @@ -349,11 +335,11 @@ type=ExeTracer [system.cpu3] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=3 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -362,6 +348,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu3.interrupts +isa=system.cpu3.isa itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -372,6 +359,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu3.tracer width=1 @@ -386,21 +374,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port @@ -417,21 +400,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port @@ -440,6 +418,9 @@ mem_side=system.toL2Bus.slave[6] [system.cpu3.interrupts] type=SparcInterrupts +[system.cpu3.isa] +type=SparcISA + [system.cpu3.itb] type=SparcTLB size=64 @@ -454,21 +435,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index c63257902..e013c98f2 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 2 2012 11:45:16 -gem5 started Nov 2 2012 11:45:52 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 15:49:24 +gem5 started Jan 23 2013 16:09:53 +gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index bb7e4e4f9..45b73a0af 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174734 # Simulator instruction rate (inst/s) -host_op_rate 174733 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22625965 # Simulator tick rate (ticks/s) -host_mem_usage 1150028 # Number of bytes of host memory used -host_seconds 3.88 # Real time elapsed on the host +host_inst_rate 205117 # Simulator instruction rate (inst/s) +host_op_rate 205116 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26560282 # Simulator tick rate (ticks/s) +host_mem_usage 1206900 # Number of bytes of host memory used +host_seconds 3.30 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 244af9704..c755fbf49 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -15,6 +15,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,11 +31,11 @@ system_port=system.membus.slave[1] [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -42,6 +43,7 @@ dtb=system.cpu0.dtb function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -50,6 +52,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu0.tracer workload=system.cpu0.workload @@ -63,21 +66,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -94,21 +92,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -117,6 +110,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=SparcInterrupts +[system.cpu0.isa] +type=SparcISA + [system.cpu0.itb] type=SparcTLB size=64 @@ -132,7 +128,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -145,11 +141,11 @@ uid=100 [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=1 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -157,6 +153,7 @@ dtb=system.cpu1.dtb function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -165,6 +162,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu1.tracer workload=system.cpu0.workload @@ -178,21 +176,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -209,21 +202,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -232,6 +220,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=SparcInterrupts +[system.cpu1.isa] +type=SparcISA + [system.cpu1.itb] type=SparcTLB size=64 @@ -241,11 +232,11 @@ type=ExeTracer [system.cpu2] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=2 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -253,6 +244,7 @@ dtb=system.cpu2.dtb function_trace=false function_trace_start=0 interrupts=system.cpu2.interrupts +isa=system.cpu2.isa itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -261,6 +253,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu2.tracer workload=system.cpu0.workload @@ -274,21 +267,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port @@ -305,21 +293,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port @@ -328,6 +311,9 @@ mem_side=system.toL2Bus.slave[4] [system.cpu2.interrupts] type=SparcInterrupts +[system.cpu2.isa] +type=SparcISA + [system.cpu2.itb] type=SparcTLB size=64 @@ -337,11 +323,11 @@ type=ExeTracer [system.cpu3] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=3 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -349,6 +335,7 @@ dtb=system.cpu3.dtb function_trace=false function_trace_start=0 interrupts=system.cpu3.interrupts +isa=system.cpu3.isa itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -357,6 +344,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu3.tracer workload=system.cpu0.workload @@ -370,21 +358,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port @@ -401,21 +384,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port @@ -424,6 +402,9 @@ mem_side=system.toL2Bus.slave[6] [system.cpu3.interrupts] type=SparcInterrupts +[system.cpu3.isa] +type=SparcISA + [system.cpu3.itb] type=SparcTLB size=64 @@ -438,21 +419,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 3b151bc02..d217747b2 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 2 2012 11:45:16 -gem5 started Nov 2 2012 11:46:01 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 15:49:24 +gem5 started Jan 23 2013 15:51:52 +gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 6b9b27a43..03a5c597b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000262 # Nu sim_ticks 261623500 # Number of ticks simulated final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114971 # Simulator instruction rate (inst/s) -host_op_rate 114971 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45557694 # Simulator tick rate (ticks/s) -host_mem_usage 232524 # Number of bytes of host memory used -host_seconds 5.74 # Real time elapsed on the host +host_inst_rate 226128 # Simulator instruction rate (inst/s) +host_op_rate 226126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89603226 # Simulator tick rate (ticks/s) +host_mem_usage 289396 # Number of bytes of host memory used +host_seconds 2.92 # Real time elapsed on the host sim_insts 660239 # Number of instructions simulated sim_ops 660239 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory |