diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/quick/se/40.m5threads-test-atomic/ref/sparc | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc')
6 files changed, 2924 insertions, 2927 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 08b3f6997..e18da5544 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1773,7 +1773,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.l2c.mem_side system.system_port @@ -1795,7 +1795,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index b2cdd54e1..2447cd00c 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:06:58 -gem5 started Jun 28 2012 22:54:10 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:31:33 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -17,66 +17,66 @@ Init done Iteration 1 completed [Iteration 2, Thread 3] Got lock [Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed -[Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock [Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 Iteration 3 completed -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 Iteration 4 completed -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 Iteration 5 completed +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=2, now next=1 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 Iteration 6 completed -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1 Iteration 7 completed +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 8, Thread 3] Got lock [Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 Iteration 9 completed -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 111594500 because target called exit() +Exiting @ tick 113941500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index ea1876230..08b3d0977 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,958 +1,958 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000112 # Number of seconds simulated -sim_ticks 111594500 # Number of ticks simulated -final_tick 111594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000114 # Number of seconds simulated +sim_ticks 113941500 # Number of ticks simulated +final_tick 113941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200629 # Simulator instruction rate (inst/s) -host_op_rate 200629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20568067 # Simulator tick rate (ticks/s) -host_mem_usage 235024 # Number of bytes of host memory used -host_seconds 5.43 # Real time elapsed on the host -sim_insts 1088531 # Number of instructions simulated -sim_ops 1088531 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory +host_inst_rate 130117 # Simulator instruction rate (inst/s) +host_op_rate 130117 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13474596 # Simulator tick rate (ticks/s) +host_mem_usage 234988 # Number of bytes of host memory used +host_seconds 8.46 # Real time elapsed on the host +sim_insts 1100269 # Number of instructions simulated +sim_ops 1100269 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29120 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 43008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 670 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 207035293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 96922339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50468437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11470099 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1147010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7455565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2294020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7455565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 384248328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 207035293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50468437 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1147010 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2294020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 260944760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 207035293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 96922339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50468437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11470099 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1147010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7455565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2294020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7455565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 384248328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 672 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 203894104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 94364213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47182107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11233835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2808459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7301993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3370150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7301993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 377456853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 203894104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47182107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2808459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3370150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 257254819 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 203894104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 94364213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47182107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11233835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2808459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7301993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3370150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7301993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 377456853 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 223190 # number of cpu cycles simulated +system.cpu0.numCycles 227884 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 87370 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 85036 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1313 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 84895 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 82517 # Number of BTB hits +system.cpu0.BPredUnit.lookups 88195 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 85894 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1314 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 85741 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 83416 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 514 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17415 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 518858 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 87370 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83031 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 170328 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 4037 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13330 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17885 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 523742 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 88195 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83933 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 172058 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 4069 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 15014 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1404 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6152 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 508 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 205057 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.530311 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.210840 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1439 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6122 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 517 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 209007 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.505859 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.211450 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34729 16.94% 16.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 84380 41.15% 58.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 595 0.29% 58.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.47% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 523 0.26% 59.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 80298 39.16% 98.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 656 0.32% 98.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 373 0.18% 98.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2530 1.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 36949 17.68% 17.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 85270 40.80% 58.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 593 0.28% 58.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1005 0.48% 59.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 500 0.24% 59.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 81190 38.85% 98.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 659 0.32% 98.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 361 0.17% 98.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2480 1.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 205057 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391460 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.324737 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18107 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14779 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 169274 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 322 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2575 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 515764 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2575 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18814 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1415 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12654 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 168925 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 674 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 512400 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 350257 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1022076 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1022076 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 336320 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13937 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 921 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 951 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4116 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 164196 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 82879 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 80125 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 79869 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 428350 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 958 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 425359 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11411 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10569 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 399 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 205057 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.074345 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.084750 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 209007 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.387017 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.298283 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18552 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 16516 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 170985 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 348 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2606 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 520718 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2606 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 19281 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2206 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13583 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 170639 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 692 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 517471 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 300 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 353567 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1032190 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1032190 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 339600 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13967 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 909 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4082 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 165924 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 83735 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 81055 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 80764 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 432543 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 950 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 429278 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11501 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11387 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 391 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 209007 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.053893 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097042 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33897 16.53% 16.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5266 2.57% 19.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 81920 39.95% 59.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 81274 39.63% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1599 0.78% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 693 0.34% 99.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 302 0.15% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 36203 17.32% 17.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5360 2.56% 19.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 82686 39.56% 59.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 82056 39.26% 98.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1635 0.78% 99.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 680 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 282 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 11 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 205057 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 209007 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 54 22.69% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 72 30.25% 52.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 47.06% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 43 16.23% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 110 41.51% 57.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 42.26% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 179447 42.19% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 163633 38.47% 80.66% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82279 19.34% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 180966 42.16% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 165240 38.49% 80.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 83072 19.35% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 425359 # Type of FU issued -system.cpu0.iq.rate 1.905816 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 238 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000560 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1056189 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 440777 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 423418 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 429278 # Type of FU issued +system.cpu0.iq.rate 1.883757 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 265 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000617 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1068049 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 445050 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 427325 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 425597 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 429543 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 79599 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 80408 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2452 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2540 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1537 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2575 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1020 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 509980 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 329 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 164196 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 82879 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2606 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1701 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 86 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 515038 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 368 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 165924 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 83735 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 368 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1157 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 424238 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 163317 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1121 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 370 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1149 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 428170 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 164921 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 80672 # number of nop insts executed -system.cpu0.iew.exec_refs 245449 # number of memory reference insts executed -system.cpu0.iew.exec_branches 84313 # Number of branches executed -system.cpu0.iew.exec_stores 82132 # Number of stores executed -system.cpu0.iew.exec_rate 1.900793 # Inst execution rate -system.cpu0.iew.wb_sent 423777 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 423418 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 250898 # num instructions producing a value -system.cpu0.iew.wb_consumers 253433 # num instructions consuming a value +system.cpu0.iew.exec_nop 81545 # number of nop insts executed +system.cpu0.iew.exec_refs 247840 # number of memory reference insts executed +system.cpu0.iew.exec_branches 85100 # Number of branches executed +system.cpu0.iew.exec_stores 82919 # Number of stores executed +system.cpu0.iew.exec_rate 1.878895 # Inst execution rate +system.cpu0.iew.wb_sent 427676 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 427325 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 253224 # num instructions producing a value +system.cpu0.iew.wb_consumers 255650 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.897119 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989997 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.875186 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990510 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 496825 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 496825 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 13135 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 501745 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 501745 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 13260 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1313 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 202499 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.453469 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.133222 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1314 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 206418 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430723 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136815 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34446 17.01% 17.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 84010 41.49% 58.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2422 1.20% 59.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 711 0.35% 60.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 562 0.28% 60.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 79343 39.18% 99.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 465 0.23% 99.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 305 0.15% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 36760 17.81% 17.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 84779 41.07% 58.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2446 1.18% 60.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 715 0.35% 60.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 578 0.28% 60.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 80055 38.78% 99.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 554 0.27% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 230 0.11% 99.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 202499 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 496825 # Number of instructions committed -system.cpu0.commit.committedOps 496825 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 206418 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 501745 # Number of instructions committed +system.cpu0.commit.committedOps 501745 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 243122 # Number of memory references committed -system.cpu0.commit.loads 161744 # Number of loads committed +system.cpu0.commit.refs 245582 # Number of memory references committed +system.cpu0.commit.loads 163384 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 83266 # Number of branches committed +system.cpu0.commit.branches 84086 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 334650 # Number of committed integer instructions. +system.cpu0.commit.int_insts 337930 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 710993 # The number of ROB reads -system.cpu0.rob.rob_writes 1022511 # The number of ROB writes -system.cpu0.timesIdled 324 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18133 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 416744 # Number of Instructions Simulated -system.cpu0.committedOps 416744 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 416744 # Number of Instructions Simulated -system.cpu0.cpi 0.535557 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535557 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.867216 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.867216 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 758967 # number of integer regfile reads -system.cpu0.int_regfile_writes 341941 # number of integer regfile writes +system.cpu0.rob.rob_reads 719961 # The number of ROB reads +system.cpu0.rob.rob_writes 1032633 # The number of ROB writes +system.cpu0.timesIdled 343 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 18877 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 420844 # Number of Instructions Simulated +system.cpu0.committedOps 420844 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 420844 # Number of Instructions Simulated +system.cpu0.cpi 0.541493 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.541493 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.846747 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.846747 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 766075 # number of integer regfile reads +system.cpu0.int_regfile_writes 345063 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 247293 # number of misc regfile reads +system.cpu0.misc_regfile_reads 249668 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 307 # number of replacements -system.cpu0.icache.tagsinuse 248.147409 # Cycle average of tags in use -system.cpu0.icache.total_refs 5393 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 598 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.018395 # Average number of references to valid blocks. +system.cpu0.icache.replacements 308 # number of replacements +system.cpu0.icache.tagsinuse 248.197747 # Cycle average of tags in use +system.cpu0.icache.total_refs 5361 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 601 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.920133 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 248.147409 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.484663 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.484663 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5393 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5393 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5393 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5393 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5393 # number of overall hits -system.cpu0.icache.overall_hits::total 5393 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses -system.cpu0.icache.overall_misses::total 759 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28913000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28913000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 28913000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28913000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 28913000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28913000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6152 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6152 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6152 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6152 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6152 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6152 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123375 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.123375 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123375 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.123375 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123375 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.123375 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38093.544137 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38093.544137 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38093.544137 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38093.544137 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 248.197747 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.484761 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.484761 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5361 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5361 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5361 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5361 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5361 # number of overall hits +system.cpu0.icache.overall_hits::total 5361 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 761 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 761 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 761 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 761 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 761 # number of overall misses +system.cpu0.icache.overall_misses::total 761 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29540500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 29540500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 29540500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 29540500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 29540500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 29540500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6122 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6122 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6122 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6122 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6122 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6122 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.124306 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.124306 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.124306 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.124306 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.124306 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.124306 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38818.002628 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38818.002628 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38818.002628 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38818.002628 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38818.002628 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38818.002628 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 13500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13500 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 160 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 160 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 160 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 160 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 599 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 599 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 599 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21855500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21855500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21855500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21855500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21855500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21855500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097367 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.097367 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.097367 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36486.644407 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 159 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 159 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 159 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 159 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 159 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 159 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 602 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 602 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 602 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 602 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 602 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 602 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22436000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22436000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22436000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22436000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22436000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22436000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098334 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098334 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098334 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.098334 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098334 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.098334 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37269.102990 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37269.102990 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37269.102990 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37269.102990 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37269.102990 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37269.102990 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 144.541703 # Cycle average of tags in use -system.cpu0.dcache.total_refs 163878 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 958.350877 # Average number of references to valid blocks. +system.cpu0.dcache.tagsinuse 144.386808 # Cycle average of tags in use +system.cpu0.dcache.total_refs 165433 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 973.135294 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 144.541703 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.282308 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.282308 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 83150 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83150 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80790 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80790 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 163940 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 163940 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 163940 # number of overall hits -system.cpu0.dcache.overall_hits::total 163940 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 500 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 500 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1046 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1046 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1046 # number of overall misses -system.cpu0.dcache.overall_misses::total 1046 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13780500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13780500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24368986 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24368986 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 390500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38149486 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38149486 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38149486 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38149486 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83650 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83650 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81336 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 144.386808 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.282005 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.282005 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 83919 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83919 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 81593 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 81593 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 18 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 18 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165512 # number of demand (read+write) hits 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overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16325500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16325500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28838494 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 28838494 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 480000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 480000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 45163994 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 45163994 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 45163994 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 45163994 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 84444 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 84444 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82156 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82156 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 164986 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 164986 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164986 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164986 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005977 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005977 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006713 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006713 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006340 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006340 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006340 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006340 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27561 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27561 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44631.842491 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44631.842491 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18595.238095 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 18595.238095 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36471.783939 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36471.783939 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 166600 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 166600 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 166600 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 166600 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006217 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006217 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006853 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006853 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.571429 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.571429 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006531 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006531 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006531 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006531 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31096.190476 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31096.190476 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51222.902309 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 51222.902309 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20000 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41511.023897 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41511.023897 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41511.023897 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41511.023897 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 119500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6638.888889 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 320 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 371 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 371 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 691 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 691 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 691 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 691 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 345 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 345 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 392 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 392 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 737 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 737 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 737 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 737 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6275500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6275500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 327500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 327500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11208500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11208500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11208500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11208500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002152 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss 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15595.238095 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15595.238095 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 24 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 24 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5693511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5693511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6731000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6731000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 405000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 405000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12424511 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12424511 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12424511 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12424511 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.571429 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.571429 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002107 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002107 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002107 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002107 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31630.616667 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31630.616667 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39362.573099 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39362.573099 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16875 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16875 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35397.467236 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35397.467236 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35397.467236 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35397.467236 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 187839 # number of cpu cycles simulated +system.cpu1.numCycles 191339 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 50940 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 47890 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1510 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 44289 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 43310 # Number of BTB hits +system.cpu1.BPredUnit.lookups 49631 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 46572 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1528 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 42950 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 41997 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 805 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 31688 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 280910 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 50940 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 44139 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 100869 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4392 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 39081 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 33375 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 271825 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 49631 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 42802 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 98758 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4453 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 42292 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6575 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1045 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 22757 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 182067 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.542894 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.098462 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 6725 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 23889 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 185079 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.468697 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.066601 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 81198 44.60% 44.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 51887 28.50% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7438 4.09% 77.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3280 1.80% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 684 0.38% 79.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 31924 17.53% 96.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1209 0.66% 97.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 879 0.48% 98.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3568 1.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 86321 46.64% 46.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51121 27.62% 74.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7925 4.28% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3336 1.80% 80.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 734 0.40% 80.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 30013 16.22% 96.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1151 0.62% 97.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 885 0.48% 98.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3593 1.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 182067 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.271190 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.495483 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 38413 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 34373 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 93637 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 6265 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2804 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 276803 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2804 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 39183 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19194 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14318 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 87661 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 12332 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 274424 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 52 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 191179 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 520245 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 520245 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 175779 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15400 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1221 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 15085 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 76182 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 35431 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 36807 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 30214 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 225638 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7711 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 228522 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12774 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11561 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 182067 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.255153 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.306407 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 185079 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.259388 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.420646 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 40472 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 37211 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 91012 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6805 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2854 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 267804 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2854 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 41302 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 21637 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14674 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 84497 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 13390 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 265308 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 184298 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 499771 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 499771 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 168579 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15719 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1236 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 16177 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 72909 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 33507 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 35450 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 28267 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 217311 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 8226 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 220400 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 173 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 12222 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 185079 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.190843 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.296813 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 78861 43.31% 43.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 26436 14.52% 57.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 35607 19.56% 77.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 36159 19.86% 97.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3279 1.80% 99.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1252 0.69% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 353 0.19% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 59 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84217 45.50% 45.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27917 15.08% 60.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 33688 18.20% 78.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 34243 18.50% 97.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3324 1.80% 99.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1232 0.67% 99.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 345 0.19% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 182067 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 185079 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 20 6.62% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 72 23.84% 30.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 69.54% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 21 6.60% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 87 27.36% 33.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 66.04% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 112122 49.06% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 81642 35.73% 84.79% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 34758 15.21% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 108844 49.38% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 78735 35.72% 85.11% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 32821 14.89% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 228522 # Type of FU issued -system.cpu1.iq.rate 1.216584 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 302 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001322 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 639493 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 246163 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 226488 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 220400 # Type of FU issued +system.cpu1.iq.rate 1.151882 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 318 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001443 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 626370 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 238714 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 218326 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 228824 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 220718 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 30049 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 28122 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2733 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2824 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1558 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2804 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1582 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 271136 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 377 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 76182 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 35431 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1144 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2854 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2376 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 261974 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 434 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 72909 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 33507 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1131 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1182 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1676 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 227186 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 75112 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1336 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 510 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1187 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 219051 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 71704 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1349 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 37787 # number of nop insts executed -system.cpu1.iew.exec_refs 109780 # number of memory reference insts executed -system.cpu1.iew.exec_branches 47145 # Number of branches executed -system.cpu1.iew.exec_stores 34668 # Number of stores executed -system.cpu1.iew.exec_rate 1.209472 # Inst execution rate -system.cpu1.iew.wb_sent 226789 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 226488 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 126631 # num instructions producing a value -system.cpu1.iew.wb_consumers 131515 # num instructions consuming a value +system.cpu1.iew.exec_nop 36437 # number of nop insts executed +system.cpu1.iew.exec_refs 104435 # number of memory reference insts executed +system.cpu1.iew.exec_branches 45735 # Number of branches executed +system.cpu1.iew.exec_stores 32731 # Number of stores executed +system.cpu1.iew.exec_rate 1.144832 # Inst execution rate +system.cpu1.iew.wb_sent 218612 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 218326 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 121254 # num instructions producing a value +system.cpu1.iew.wb_consumers 126110 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.205756 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.962864 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.141043 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.961494 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 256347 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 256347 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 14788 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6949 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1510 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 172689 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.484443 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.966336 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 246738 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 246738 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 15223 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7427 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1528 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 175501 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.405907 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.932846 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 79222 45.88% 45.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 45065 26.10% 71.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6173 3.57% 75.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7849 4.55% 80.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1517 0.88% 80.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 30495 17.66% 98.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 550 0.32% 98.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 998 0.58% 99.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 820 0.47% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 84843 48.34% 48.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 43671 24.88% 73.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6232 3.55% 76.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8331 4.75% 81.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1551 0.88% 82.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 28453 16.21% 98.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 613 0.35% 98.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 993 0.57% 99.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 172689 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 256347 # Number of instructions committed -system.cpu1.commit.committedOps 256347 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 175501 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 246738 # Number of instructions committed +system.cpu1.commit.committedOps 246738 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 107314 # Number of memory references committed -system.cpu1.commit.loads 73449 # Number of loads committed -system.cpu1.commit.membars 6235 # Number of memory barriers committed -system.cpu1.commit.branches 46061 # Number of branches committed +system.cpu1.commit.refs 102034 # Number of memory references committed +system.cpu1.commit.loads 70085 # Number of loads committed +system.cpu1.commit.membars 6711 # Number of memory barriers committed +system.cpu1.commit.branches 44619 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 175498 # Number of committed integer instructions. +system.cpu1.commit.int_insts 168775 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 820 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 442417 # The number of ROB reads -system.cpu1.rob.rob_writes 545088 # The number of ROB writes -system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5772 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35349 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 213261 # Number of Instructions Simulated -system.cpu1.committedOps 213261 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 213261 # Number of Instructions Simulated -system.cpu1.cpi 0.880794 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.880794 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.135339 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.135339 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 389025 # number of integer regfile reads -system.cpu1.int_regfile_writes 181950 # number of integer regfile writes +system.cpu1.rob.rob_reads 436061 # The number of ROB reads +system.cpu1.rob.rob_writes 526790 # The number of ROB writes +system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6260 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 36543 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 204620 # Number of Instructions Simulated +system.cpu1.committedOps 204620 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 204620 # Number of Instructions Simulated +system.cpu1.cpi 0.935094 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.935094 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.069411 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.069411 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 373202 # number of integer regfile reads +system.cpu1.int_regfile_writes 174771 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 111436 # number of misc regfile reads +system.cpu1.misc_regfile_reads 106146 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 321 # number of replacements -system.cpu1.icache.tagsinuse 92.166456 # Cycle average of tags in use -system.cpu1.icache.total_refs 22247 # Total number of references to valid blocks. +system.cpu1.icache.replacements 322 # number of replacements +system.cpu1.icache.tagsinuse 90.902674 # Cycle average of tags in use +system.cpu1.icache.total_refs 23372 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 51.025229 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 53.605505 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 92.166456 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.180013 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.180013 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 22247 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 22247 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 22247 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 22247 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 22247 # number of overall hits -system.cpu1.icache.overall_hits::total 22247 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 510 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 510 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 510 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 510 # number of overall misses -system.cpu1.icache.overall_misses::total 510 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11347500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11347500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11347500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11347500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11347500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11347500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 22757 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 22757 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22757 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22757 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22757 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22757 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022411 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022411 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022411 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022411 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022411 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022411 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22250 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 22250 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22250 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 22250 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22250 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 22250 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 90.902674 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.177544 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.177544 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 23372 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 23372 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 23372 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 23372 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 23372 # number of overall hits +system.cpu1.icache.overall_hits::total 23372 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses +system.cpu1.icache.overall_misses::total 517 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11874500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11874500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11874500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11874500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11874500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11874500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23889 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23889 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23889 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23889 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23889 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23889 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021642 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.021642 # miss rate for ReadReq accesses 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-system.cpu1.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 74 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8591500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8591500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8591500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8591500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8591500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8591500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019159 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019159 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019159 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19705.275229 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8863000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8863000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8863000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8863000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8863000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8863000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018251 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018251 # mshr miss rate for ReadReq accesses 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20327.981651 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.650583 # Cycle average of tags in use -system.cpu1.dcache.total_refs 40148 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.508331 # Cycle average of tags in use +system.cpu1.dcache.total_refs 38240 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1384.413793 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1318.620690 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.650583 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054005 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054005 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 44622 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 44622 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 33643 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 33643 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 78265 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 78265 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 78265 # number of overall hits -system.cpu1.dcache.overall_hits::total 78265 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 425 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 425 # number of ReadReq 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0.764706 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007344 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007344 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007344 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007344 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21869.411765 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 21869.411765 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20405.844156 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20405.844156 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23442.307692 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 23442.307692 # average SwapReq miss latency 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+system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 74916 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 74916 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 74916 # number of overall hits +system.cpu1.dcache.overall_hits::total 74916 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 395 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 395 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 134 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 134 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 529 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 529 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 529 # number of overall misses +system.cpu1.dcache.overall_misses::total 529 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 11922500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 11922500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3308000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3308000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1319000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 1319000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15230500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15230500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15230500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15230500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 43566 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 43566 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 31879 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 31879 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 75445 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 75445 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 75445 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 75445 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009067 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009067 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004203 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004203 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007012 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007012 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007012 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007012 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 30183.544304 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 30183.544304 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24686.567164 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24686.567164 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23981.818182 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 23981.818182 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28791.115312 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 28791.115312 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28791.115312 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 28791.115312 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -961,366 +961,366 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 266 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 47 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 313 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 313 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 263 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 263 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 263 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2405000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2405000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1693500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1693500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1063000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1063000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4098500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4098500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4098500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4098500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003530 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003166 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003166 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.764706 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.764706 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003374 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003374 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15125.786164 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15125.786164 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15827.102804 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15827.102804 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20442.307692 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20442.307692 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3273504 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3273504 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1639000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1639000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1148500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1148500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4912504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4912504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4912504 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4912504 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003810 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003810 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003137 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003137 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003526 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003526 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003526 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003526 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19719.903614 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19719.903614 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16390 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16390 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20881.818182 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20881.818182 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18468.060150 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18468.060150 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18468.060150 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18468.060150 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 187552 # number of cpu cycles simulated +system.cpu2.numCycles 191032 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 49236 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 46105 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1532 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 42466 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 41429 # Number of BTB hits +system.cpu2.BPredUnit.lookups 57390 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 54193 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1550 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 50681 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 49645 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 825 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 804 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 33274 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 268508 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 49236 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 42254 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 98143 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4464 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 42536 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 29539 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 321276 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 57390 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 50449 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 112230 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4473 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 35583 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6571 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1082 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 24716 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 184466 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.455596 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.059567 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6761 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 20533 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 334 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 188044 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.708515 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.158633 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 86323 46.80% 46.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 50944 27.62% 74.41% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8337 4.52% 78.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3301 1.79% 80.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 755 0.41% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 29086 15.77% 96.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1170 0.63% 97.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 883 0.48% 98.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3667 1.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 75814 40.32% 40.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 56962 30.29% 70.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6138 3.26% 73.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3348 1.78% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 769 0.41% 76.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 39287 20.89% 96.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1207 0.64% 97.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 911 0.48% 98.08% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3608 1.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 184466 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.262519 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.431646 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 41063 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36807 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 89946 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 7224 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2855 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 264281 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2855 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 41843 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 22202 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13743 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 82992 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14260 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 261668 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 181221 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 490993 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 490993 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 165322 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15899 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1233 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1350 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 17036 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 71489 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 32632 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 34884 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 27362 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 213682 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8649 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 217360 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13263 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11908 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 765 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 184466 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.178320 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.292872 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 188044 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.300421 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.681792 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 35225 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 31967 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 106013 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5229 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2849 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 316907 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2849 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 36004 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 16323 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 14784 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 101094 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 10229 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 314547 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 220052 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605102 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 605102 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 204228 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15824 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1236 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1356 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12873 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 89800 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 42907 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 42940 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 37601 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 260749 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6485 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 262481 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 146 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13131 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11780 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 188044 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.395849 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.314415 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 84063 45.57% 45.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 29277 15.87% 61.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 32764 17.76% 79.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 33297 18.05% 97.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3312 1.80% 99.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1277 0.69% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 362 0.20% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73292 38.98% 38.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23055 12.26% 51.24% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 43065 22.90% 74.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 43582 23.18% 97.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3340 1.78% 99.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1248 0.66% 99.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 346 0.18% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 184466 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 188044 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 20 6.64% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 71 23.59% 30.23% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 107542 49.48% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 77871 35.83% 85.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 31947 14.70% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 126143 48.06% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 94161 35.87% 83.93% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 42177 16.07% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 217360 # Type of FU issued -system.cpu2.iq.rate 1.158932 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001385 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 619541 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 235636 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 215243 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 262481 # Type of FU issued +system.cpu2.iq.rate 1.374016 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 316 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 713468 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 280402 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 260315 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 217661 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 262797 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 27206 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 37443 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2801 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1615 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1644 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2855 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1726 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 258195 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 71489 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 32632 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2849 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1860 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 311245 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 407 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 89800 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 42907 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 74 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1199 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1712 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 215982 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 70400 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1378 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 516 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1201 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1717 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 261072 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 88760 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1409 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 35864 # number of nop insts executed -system.cpu2.iew.exec_refs 102255 # number of memory reference insts executed -system.cpu2.iew.exec_branches 45260 # Number of branches executed -system.cpu2.iew.exec_stores 31855 # Number of stores executed -system.cpu2.iew.exec_rate 1.151585 # Inst execution rate -system.cpu2.iew.wb_sent 215555 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 215243 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 119078 # num instructions producing a value -system.cpu2.iew.wb_consumers 124002 # num instructions consuming a value +system.cpu2.iew.exec_nop 44011 # number of nop insts executed +system.cpu2.iew.exec_refs 130847 # number of memory reference insts executed +system.cpu2.iew.exec_branches 53503 # Number of branches executed +system.cpu2.iew.exec_stores 42087 # Number of stores executed +system.cpu2.iew.exec_rate 1.366640 # Inst execution rate +system.cpu2.iew.wb_sent 260613 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 260315 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 147697 # num instructions producing a value +system.cpu2.iew.wb_consumers 152590 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.147644 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.960291 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.362677 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.967934 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 242999 # The number of committed instructions -system.cpu2.commit.commitCommittedOps 242999 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 15188 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7884 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1532 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 175041 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.388240 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.921152 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 296145 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 296145 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 15092 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5798 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1550 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 178435 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.659680 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.032759 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 85384 48.78% 48.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 43145 24.65% 73.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6226 3.56% 76.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8763 5.01% 81.99% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1523 0.87% 82.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 27601 15.77% 98.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 589 0.34% 98.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 998 0.57% 99.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 72400 40.57% 40.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 51371 28.79% 69.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6245 3.50% 72.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6660 3.73% 76.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1539 0.86% 77.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 37793 21.18% 98.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 621 0.35% 98.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 991 0.56% 99.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 175041 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 242999 # Number of instructions committed -system.cpu2.commit.committedOps 242999 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 178435 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 296145 # Number of instructions committed +system.cpu2.commit.committedOps 296145 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 99705 # Number of memory references committed -system.cpu2.commit.loads 68688 # Number of loads committed -system.cpu2.commit.membars 7170 # Number of memory barriers committed -system.cpu2.commit.branches 44148 # Number of branches committed +system.cpu2.commit.refs 128361 # Number of memory references committed +system.cpu2.commit.loads 87098 # Number of loads committed +system.cpu2.commit.membars 5084 # Number of memory barriers committed +system.cpu2.commit.branches 52312 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 165976 # Number of committed integer instructions. +system.cpu2.commit.int_insts 202794 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 431829 # The number of ROB reads -system.cpu2.rob.rob_writes 519243 # The number of ROB writes -system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3086 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 200891 # Number of Instructions Simulated -system.cpu2.committedOps 200891 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 200891 # Number of Instructions Simulated -system.cpu2.cpi 0.933601 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.933601 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.071122 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.071122 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 366578 # number of integer regfile reads -system.cpu2.int_regfile_writes 171642 # number of integer regfile writes +system.cpu2.rob.rob_reads 488270 # The number of ROB reads +system.cpu2.rob.rob_writes 625337 # The number of ROB writes +system.cpu2.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 2988 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 36850 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 247959 # Number of Instructions Simulated +system.cpu2.committedOps 247959 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 247959 # Number of Instructions Simulated +system.cpu2.cpi 0.770418 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.770418 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.297997 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.297997 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 452595 # number of integer regfile reads +system.cpu2.int_regfile_writes 210629 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 103931 # number of misc regfile reads +system.cpu2.misc_regfile_reads 132559 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 324 # number of replacements -system.cpu2.icache.tagsinuse 83.306019 # Cycle average of tags in use -system.cpu2.icache.total_refs 24210 # Total number of references to valid blocks. +system.cpu2.icache.replacements 322 # number of replacements +system.cpu2.icache.tagsinuse 84.182173 # Cycle average of tags in use +system.cpu2.icache.total_refs 20037 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 55.273973 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 45.746575 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 83.306019 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.162707 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.162707 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 24210 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 24210 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 24210 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 24210 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 24210 # number of overall hits -system.cpu2.icache.overall_hits::total 24210 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 506 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 506 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 506 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 506 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 506 # number of overall misses -system.cpu2.icache.overall_misses::total 506 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7060500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7060500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7060500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7060500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7060500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7060500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 24716 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 24716 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 24716 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 24716 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 24716 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 24716 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020473 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.020473 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020473 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.020473 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020473 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.020473 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13953.557312 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13953.557312 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13953.557312 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13953.557312 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 84.182173 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.164418 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.164418 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 20037 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 20037 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 20037 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 20037 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 20037 # number of overall hits +system.cpu2.icache.overall_hits::total 20037 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 496 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 496 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 496 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 496 # number of overall misses +system.cpu2.icache.overall_misses::total 496 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7608500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7608500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7608500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7608500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7608500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7608500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 20533 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 20533 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 20533 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 20533 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 20533 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 20533 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024156 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024156 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024156 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024156 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024156 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024156 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15339.717742 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15339.717742 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15339.717742 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15339.717742 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15339.717742 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15339.717742 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1329,106 +1329,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 58 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 58 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 58 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 58 # number of overall MSHR hits system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5136000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5136000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5136000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5136000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5136000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5136000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017721 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.017721 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.017721 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11726.027397 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5673500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5673500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5673500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5673500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5673500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5673500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021332 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021332 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021332 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021332 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021332 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021332 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12953.196347 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12953.196347 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12953.196347 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12953.196347 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12953.196347 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12953.196347 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 24.973314 # Cycle average of tags in use -system.cpu2.dcache.total_refs 37203 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 24.868946 # Cycle average of tags in use +system.cpu2.dcache.total_refs 47444 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1328.678571 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1694.428571 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.973314 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048776 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048776 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 42731 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42731 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 30798 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 30798 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 73529 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 73529 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 73529 # number of overall hits -system.cpu2.dcache.overall_hits::total 73529 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 443 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 443 # number of ReadReq misses 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Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.048572 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.048572 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 50906 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 50906 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 41055 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 41055 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 91961 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 91961 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 91961 # number of overall hits +system.cpu2.dcache.overall_hits::total 91961 # number of overall hits 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number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 41195 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 74123 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 74123 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 74123 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 74123 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010261 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.010261 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004879 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004879 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794118 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008014 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.008014 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008014 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.008014 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22261.851016 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 22261.851016 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18582.781457 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 18582.781457 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21731.481481 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 21731.481481 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 21326.599327 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 21326.599327 # average overall miss latency +system.cpu2.dcache.demand_accesses::cpu2.data 92493 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 92493 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 92493 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 92493 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007642 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.007642 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003398 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003398 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005752 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005752 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005752 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005752 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 25846.938776 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 25846.938776 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24225 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 24225 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21919.642857 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 21919.642857 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25420.112782 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 25420.112782 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25420.112782 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 25420.112782 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1437,366 +1437,366 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 279 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 326 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 326 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 164 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2336000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2336000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1419000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1419000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1011500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1011500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3755000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3755000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3755000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3755000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003799 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003799 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003360 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003360 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794118 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003616 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003616 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14243.902439 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14243.902439 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13644.230769 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13644.230769 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18731.481481 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18731.481481 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 276 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 276 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 276 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 276 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 256 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 256 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 256 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2456507 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2456507 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1732500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1732500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1052000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1052000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4189007 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4189007 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4189007 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4189007 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002944 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002549 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002549 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002768 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.002768 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002768 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.002768 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16268.258278 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16268.258278 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16500 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16500 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18785.714286 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18785.714286 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16363.308594 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16363.308594 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16363.308594 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16363.308594 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 187286 # number of cpu cycles simulated +system.cpu3.numCycles 190752 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 59110 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 55955 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1573 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 52456 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 51388 # Number of BTB hits +system.cpu3.BPredUnit.lookups 53643 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 50394 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1547 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 46912 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 45897 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 831 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 838 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 27555 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 332776 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 59110 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 52219 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 115081 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4575 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 31846 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 31381 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 296607 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 53643 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 46735 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 105748 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4379 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 39758 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6567 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1060 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 19062 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 185045 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.798352 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.183167 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6743 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 22503 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 187456 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.582275 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.112091 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 69964 37.81% 37.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 58012 31.35% 69.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 5498 2.97% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3553 1.92% 74.05% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 717 0.39% 74.44% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 41629 22.50% 96.93% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1211 0.65% 97.59% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 858 0.46% 98.05% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3603 1.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 81708 43.59% 43.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 54260 28.95% 72.53% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7170 3.82% 76.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3258 1.74% 78.10% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 706 0.38% 78.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 34710 18.52% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1204 0.64% 97.63% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 885 0.47% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3555 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 185045 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.315614 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.776833 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 32638 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 28853 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 109537 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4519 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2931 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 328437 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2931 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 33475 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14026 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 105232 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 8844 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 325744 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 59 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 228226 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 629601 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 629601 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 212325 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15901 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1261 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 11670 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 93735 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 45116 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 44692 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 39822 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 270564 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6038 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 271349 # Number of instructions issued +system.cpu3.fetch.rateDist::total 187456 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.281219 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.554935 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 37941 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 35250 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 98653 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 6106 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2763 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 292333 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2763 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 38724 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 18900 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 15518 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 92845 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 11963 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 289904 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 201915 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 552179 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 552179 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 186764 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15151 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1285 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1418 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 14719 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 81367 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 38245 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 39205 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 32957 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 238924 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7473 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 241868 # Number of instructions issued system.cpu3.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13410 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 12382 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 838 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 185045 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.466395 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.313251 # Number of insts issued each cycle +system.cpu3.iq.iqSquashedInstsExamined 12521 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10991 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 722 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 187456 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.290265 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.307286 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 67828 36.65% 36.65% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 21223 11.47% 48.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 45218 24.44% 72.56% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 45760 24.73% 97.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3300 1.78% 99.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1261 0.68% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 79218 42.26% 42.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 25849 13.79% 56.05% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 38415 20.49% 76.54% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 38999 20.80% 97.35% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3297 1.76% 99.10% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1241 0.66% 99.77% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 322 0.17% 99.94% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 185045 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 187456 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 21 6.80% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 78 25.24% 32.04% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 67.96% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 22 7.19% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 74 24.18% 31.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 68.63% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 129621 47.77% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 97351 35.88% 83.65% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 44377 16.35% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 117603 48.62% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 86736 35.86% 84.48% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 37529 15.52% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 271349 # Type of FU issued -system.cpu3.iq.rate 1.448848 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 728169 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 290051 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 269261 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 241868 # Type of FU issued +system.cpu3.iq.rate 1.267971 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 306 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001265 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 671615 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 258950 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 239863 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 271658 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 242174 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 39639 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 32833 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2895 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1672 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2526 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1583 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2931 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1690 # Number of cycles IEW is blocking +system.cpu3.iew.iewSquashCycles 2763 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1788 # Number of cycles IEW is blocking system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 322365 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 93735 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 45116 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1181 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewDispatchedInsts 286739 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 413 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 81367 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 38245 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1210 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 528 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1218 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1746 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 269989 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 92559 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1360 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 503 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1210 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1713 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 240581 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 80413 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1287 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 45763 # number of nop insts executed -system.cpu3.iew.exec_refs 136843 # number of memory reference insts executed -system.cpu3.iew.exec_branches 55022 # Number of branches executed -system.cpu3.iew.exec_stores 44284 # Number of stores executed -system.cpu3.iew.exec_rate 1.441587 # Inst execution rate -system.cpu3.iew.wb_sent 269584 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 269261 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 153664 # num instructions producing a value -system.cpu3.iew.wb_consumers 158539 # num instructions consuming a value +system.cpu3.iew.exec_nop 40342 # number of nop insts executed +system.cpu3.iew.exec_refs 117868 # number of memory reference insts executed +system.cpu3.iew.exec_branches 49825 # Number of branches executed +system.cpu3.iew.exec_stores 37455 # Number of stores executed +system.cpu3.iew.exec_rate 1.261224 # Inst execution rate +system.cpu3.iew.wb_sent 240146 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 239863 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 134653 # num instructions producing a value +system.cpu3.iew.wb_consumers 139524 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.437700 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.969250 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.257460 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.965088 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 306791 # The number of committed instructions -system.cpu3.commit.commitCommittedOps 306791 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 15574 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5200 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1573 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 175548 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.747619 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.056560 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 272332 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 272332 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 14381 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6751 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1547 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 177951 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.530376 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.985731 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 66312 37.77% 37.77% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 53003 30.19% 67.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6220 3.54% 71.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6065 3.45% 74.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1526 0.87% 75.83% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 40098 22.84% 98.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 522 0.30% 98.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 989 0.56% 99.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 79207 44.51% 44.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 47739 26.83% 71.34% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6222 3.50% 74.83% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7617 4.28% 79.11% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1549 0.87% 79.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 33224 18.67% 98.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 582 0.33% 98.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 998 0.56% 99.54% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 175548 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 306791 # Number of instructions committed -system.cpu3.commit.committedOps 306791 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 177951 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 272332 # Number of instructions committed +system.cpu3.commit.committedOps 272332 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 134284 # Number of memory references committed -system.cpu3.commit.loads 90840 # Number of loads committed -system.cpu3.commit.membars 4481 # Number of memory barriers committed -system.cpu3.commit.branches 53890 # Number of branches committed +system.cpu3.commit.refs 115503 # Number of memory references committed +system.cpu3.commit.loads 78841 # Number of loads committed +system.cpu3.commit.membars 6036 # Number of memory barriers committed +system.cpu3.commit.branches 48661 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 210289 # Number of committed integer instructions. +system.cpu3.commit.int_insts 186284 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 496513 # The number of ROB reads -system.cpu3.rob.rob_writes 647676 # The number of ROB writes -system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2241 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 35902 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 257635 # Number of Instructions Simulated -system.cpu3.committedOps 257635 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 257635 # Number of Instructions Simulated -system.cpu3.cpi 0.726943 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.726943 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.375623 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.375623 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 470214 # number of integer regfile reads -system.cpu3.int_regfile_writes 218594 # number of integer regfile writes +system.cpu3.rob.rob_reads 463264 # The number of ROB reads +system.cpu3.rob.rob_writes 576197 # The number of ROB writes +system.cpu3.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 3296 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 37130 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 226846 # Number of Instructions Simulated +system.cpu3.committedOps 226846 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 226846 # Number of Instructions Simulated +system.cpu3.cpi 0.840888 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.840888 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.189220 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.189220 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 413495 # number of integer regfile reads +system.cpu3.int_regfile_writes 192863 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 138505 # number of misc regfile reads +system.cpu3.misc_regfile_reads 119579 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 322 # number of replacements -system.cpu3.icache.tagsinuse 87.207959 # Cycle average of tags in use -system.cpu3.icache.total_refs 18566 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 42.582569 # Average number of references to valid blocks. +system.cpu3.icache.replacements 323 # number of replacements +system.cpu3.icache.tagsinuse 88.254899 # Cycle average of tags in use +system.cpu3.icache.total_refs 21999 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 439 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 50.111617 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 87.207959 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.170328 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.170328 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 18566 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 18566 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 18566 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 18566 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 18566 # number of overall hits -system.cpu3.icache.overall_hits::total 18566 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 496 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 496 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 496 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 496 # number of overall misses -system.cpu3.icache.overall_misses::total 496 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6966500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6966500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6966500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6966500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6966500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6966500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 19062 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 19062 # number of ReadReq accesses(hits+misses) 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+system.cpu3.dcache.demand_miss_rate::total 0.005953 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005953 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005953 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 26177.285319 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 26177.285319 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23775 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 23775 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 23736.363636 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 23736.363636 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 25505.988024 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 25505.988024 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 25505.988024 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 25505.988024 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1913,288 +1913,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 264 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 310 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 310 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 310 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 61 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 61 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1797000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1797000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1508500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1508500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 978500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 978500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3305500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3305500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3305500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3305500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003025 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003025 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002398 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002398 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835616 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835616 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002742 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002742 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002742 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002742 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 11231.250000 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 11231.250000 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14504.807692 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14504.807692 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 16040.983607 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 16040.983607 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 206 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 206 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 239 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 239 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses 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miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4320504 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003259 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003259 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002924 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002924 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797101 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003113 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003113 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003113 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003113 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16680.670968 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16680.670968 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16214.953271 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16214.953271 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20627.272727 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20627.272727 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16490.473282 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16490.473282 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16490.473282 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16490.473282 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 436.530480 # Cycle average of tags in use -system.l2c.total_refs 1479 # Total number of references to valid blocks. -system.l2c.sampled_refs 536 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.759328 # Average number of references to valid blocks. +system.l2c.tagsinuse 436.890326 # Cycle average of tags in use +system.l2c.total_refs 1480 # Total number of references to valid blocks. +system.l2c.sampled_refs 538 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.750929 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.840422 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 294.533073 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.606311 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 70.480803 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.728880 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.673039 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.734409 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 2.156423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.777117 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.838452 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 294.676580 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.534459 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 68.181124 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.702984 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2.344879 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.730463 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 4.107761 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.773625 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004494 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000910 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001075 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004496 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000908 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001040 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000026 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000033 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000063 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006661 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 238 # number of ReadReq hits +system.l2c.occ_percent::total 0.006666 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 239 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 347 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 350 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 431 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 428 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1479 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1480 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 238 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 239 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 347 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 350 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 431 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 428 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 431 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1479 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 238 # number of overall hits +system.l2c.demand_hits::total 1480 # number of demand (read+write) hits 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number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 81 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 75 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses 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rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.310761 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40226.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.310967 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44358.108108 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39981.447124 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41319.778189 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40026.315789 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40006.172840 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40335.106383 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40192.307692 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40291.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40297.709924 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40263.157895 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40120 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42755.319149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42625 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43057.251908 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43461.309524 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 41658.482143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43461.309524 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 41658.482143 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index cf4b383de..55888365a 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -449,7 +449,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.l2c.mem_side system.system_port @@ -471,7 +471,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 145ab230c..900805018 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:06:58 -gem5 started Jun 28 2012 22:54:12 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:32:06 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second @@ -10,73 +10,73 @@ info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 Iteration 1 completed -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 Iteration 2 completed +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 Iteration 3 completed -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 Iteration 4 completed +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 5, Thread 2] Got lock [Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 Iteration 5 completed -[Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 Iteration 6 completed +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 7, Thread 2] Got lock [Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 Iteration 7 completed -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 Iteration 8 completed +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 9, Thread 2] Got lock [Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 262299000 because target called exit() +Exiting @ tick 268912000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index c654a221f..ea05c2e9c 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000262 # Number of seconds simulated -sim_ticks 262299000 # Number of ticks simulated -final_tick 262299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000269 # Number of seconds simulated +sim_ticks 268912000 # Number of ticks simulated +final_tick 268912000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1271827 # Simulator instruction rate (inst/s) -host_op_rate 1271784 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 503510999 # Simulator tick rate (ticks/s) -host_mem_usage 230932 # Number of bytes of host memory used -host_seconds 0.52 # Real time elapsed on the host -sim_insts 662502 # Number of instructions simulated -sim_ops 662502 # Number of ops (including micro ops) simulated +host_inst_rate 548575 # Simulator instruction rate (inst/s) +host_op_rate 548567 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 220132321 # Simulator tick rate (ticks/s) +host_mem_usage 230896 # Number of bytes of host memory used +host_seconds 1.22 # Real time elapsed on the host +sim_insts 670117 # Number of instructions simulated +sim_ops 670117 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69538961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40259399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14395785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5367920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2195967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3903942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 243996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3659945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139565915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69538961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14395785 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2195967 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 243996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86374710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69538961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40259399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14395785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5367920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2195967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3903942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 243996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3659945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139565915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 67828881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 39269352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14041768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5235914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 475992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3569941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1903969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3807937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136133754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 67828881 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14041768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 475992 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1903969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84250610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 67828881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 39269352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14041768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5235914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 475992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3569941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1903969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3807937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 136133754 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 524598 # number of cpu cycles simulated +system.cpu0.numCycles 537824 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158353 # Number of instructions committed -system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses +system.cpu0.committedInsts 160927 # Number of instructions committed +system.cpu0.committedOps 160927 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 110780 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25994 # number of instructions that are conditional controls -system.cpu0.num_int_insts 109064 # number of integer instructions +system.cpu0.num_conditional_control_insts 26423 # number of instructions that are conditional controls +system.cpu0.num_int_insts 110780 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written +system.cpu0.num_int_register_reads 320484 # number of times the integer registers were read +system.cpu0.num_int_register_writes 112387 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73905 # number of memory refs -system.cpu0.num_load_insts 48930 # Number of load instructions -system.cpu0.num_store_insts 24975 # Number of store instructions +system.cpu0.num_mem_refs 75192 # number of memory refs +system.cpu0.num_load_insts 49788 # Number of load instructions +system.cpu0.num_store_insts 25404 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 524598 # Number of busy cycles +system.cpu0.num_busy_cycles 537824 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.479251 # Cycle average of tags in use -system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.253377 # Cycle average of tags in use +system.cpu0.icache.total_refs 160523 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 343.732334 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.479251 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414999 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414999 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits -system.cpu0.icache.overall_hits::total 157949 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.253377 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414557 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414557 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 160523 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 160523 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 160523 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 160523 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 160523 # number of overall hits +system.cpu0.icache.overall_hits::total 160523 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002948 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002948 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002948 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 39665.952891 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 39665.952891 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 39665.952891 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18554000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18554000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18554000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18554000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18554000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18554000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 160990 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 160990 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 160990 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 160990 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 160990 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 160990 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002901 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002901 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002901 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002901 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002901 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002901 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 39730.192719 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 39730.192719 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,44 +139,44 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002948 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002948 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002948 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36665.952891 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17153000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17153000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17153000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17153000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17153000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17153000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002901 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002901 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36730.192719 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.603716 # Cycle average of tags in use -system.cpu0.dcache.total_refs 73381 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.513886 # Cycle average of tags in use +system.cpu0.dcache.total_refs 74668 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 439.407186 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 447.113772 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.603716 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284382 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284382 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.513886 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284207 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284207 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 49616 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 49616 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 25170 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 25170 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits -system.cpu0.dcache.overall_hits::total 73499 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 74786 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 74786 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 74786 # number of overall hits +system.cpu0.dcache.overall_hits::total 74786 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -187,46 +187,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4747000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4747000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7176000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7176000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 389000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 389000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11923000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11923000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11923000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11923000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5171000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5171000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7310000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7310000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 522000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 522000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 12481000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 12481000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 12481000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 12481000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 49778 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 49778 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 25353 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 25353 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003312 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007342 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 75131 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 75131 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 75131 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 75131 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003254 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003254 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007218 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007218 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29302.469136 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29302.469136 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39213.114754 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39213.114754 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14961.538462 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 14961.538462 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34559.420290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34559.420290 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004592 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004592 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004592 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004592 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31919.753086 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31919.753086 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39945.355191 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39945.355191 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20076.923077 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 20076.923077 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36176.811594 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -247,104 +247,104 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4261000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4261000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6627000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6627000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10888000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10888000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10888000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10888000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4684001 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4684001 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6761000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6761000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 444000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 444000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11445001 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11445001 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11445001 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11445001 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003254 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003254 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007218 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007218 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26302.469136 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26302.469136 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36213.114754 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36213.114754 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11961.538462 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11961.538462 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004592 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004592 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28913.586420 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28913.586420 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36945.355191 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36945.355191 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17076.923077 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17076.923077 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 524598 # number of cpu cycles simulated +system.cpu1.numCycles 537824 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 172389 # Number of instructions committed -system.cpu1.committedOps 172389 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107964 # Number of integer alu accesses +system.cpu1.committedInsts 159902 # Number of instructions committed +system.cpu1.committedOps 159902 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 114536 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36219 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107964 # number of integer instructions +system.cpu1.num_conditional_control_insts 26689 # number of instructions that are conditional controls +system.cpu1.num_int_insts 114536 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 249169 # number of times the integer registers were read -system.cpu1.num_int_register_writes 92792 # number of times the integer registers were written +system.cpu1.num_int_register_reads 313629 # number of times the integer registers were read +system.cpu1.num_int_register_writes 121810 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 47914 # number of memory refs -system.cpu1.num_load_insts 39632 # Number of load instructions -system.cpu1.num_store_insts 8282 # Number of store instructions -system.cpu1.num_idle_cycles 68732.001738 # Number of idle cycles -system.cpu1.num_busy_cycles 455865.998262 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868982 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131018 # Percentage of idle cycles +system.cpu1.num_mem_refs 64016 # number of memory refs +system.cpu1.num_load_insts 42937 # Number of load instructions +system.cpu1.num_store_insts 21079 # Number of store instructions +system.cpu1.num_idle_cycles 71606.001734 # Number of idle cycles +system.cpu1.num_busy_cycles 466217.998266 # Number of busy cycles +system.cpu1.not_idle_fraction 0.866860 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.133140 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.077944 # Cycle average of tags in use -system.cpu1.icache.total_refs 172056 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 69.902178 # Cycle average of tags in use +system.cpu1.icache.total_refs 159569 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 470.098361 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 435.980874 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.077944 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136871 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136871 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 172056 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 172056 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 172056 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 172056 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 172056 # number of overall hits -system.cpu1.icache.overall_hits::total 172056 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 69.902178 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136528 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136528 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 159569 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 159569 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 159569 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 159569 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 159569 # number of overall hits +system.cpu1.icache.overall_hits::total 159569 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7921500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7921500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7921500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7921500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7921500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7921500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 172422 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 172422 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 172422 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 172422 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 172422 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 172422 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21643.442623 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21643.442623 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21643.442623 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21643.442623 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7984500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7984500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7984500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7984500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7984500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7984500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 159935 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 159935 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 159935 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 159935 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 159935 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 159935 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002288 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002288 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002288 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002288 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002288 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002288 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21815.573770 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21815.573770 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21815.573770 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21815.573770 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +359,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6823000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6823000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6823000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6823000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18642.076503 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6886000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6886000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6886000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6886000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6886000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6886000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002288 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18814.207650 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.731444 # Cycle average of tags in use -system.cpu1.dcache.total_refs 18765 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.730072 # Cycle average of tags in use +system.cpu1.dcache.total_refs 44449 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 647.068966 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1532.724138 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.731444 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054163 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054163 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 39445 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39445 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 47544 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 47544 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 47544 # number of overall hits -system.cpu1.dcache.overall_hits::total 47544 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 179 # 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WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 47821 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 47821 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 47821 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 47821 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004517 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004517 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005792 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005792 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005792 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005792 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20575.418994 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20575.418994 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18755.102041 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18755.102041 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19931.407942 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19931.407942 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 27.730072 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.054160 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.054160 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 42776 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 42776 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 20903 # number of WriteReq hits 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+system.cpu1.dcache.demand_miss_latency::total 5440000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5440000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5440000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 42929 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 42929 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 21009 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 21009 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 63938 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 63938 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 63938 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 63938 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003564 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003564 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005045 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.005045 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.852941 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004051 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004051 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004051 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004051 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19803.921569 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19803.921569 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22735.849057 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22735.849057 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13310.344828 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 13310.344828 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21003.861004 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21003.861004 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,114 +455,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 179 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 277 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 277 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3146000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3146000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1544000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1544000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4690000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4690000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4690000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4690000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004517 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004517 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005792 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005792 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17575.418994 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17575.418994 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15755.102041 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15755.102041 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2570001 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2570001 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2092000 # number of WriteReq MSHR miss cycles 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for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.852941 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004051 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004051 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16797.392157 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16797.392157 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19735.849057 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19735.849057 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10310.344828 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10310.344828 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 524598 # number of cpu cycles simulated +system.cpu2.numCycles 537824 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165564 # Number of instructions committed -system.cpu2.committedOps 165564 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112387 # Number of integer alu accesses +system.cpu2.committedInsts 177221 # Number of instructions committed +system.cpu2.committedOps 177221 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 109567 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30599 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112387 # number of integer instructions +system.cpu2.num_conditional_control_insts 37840 # number of instructions that are conditional controls +system.cpu2.num_int_insts 109567 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 289349 # number of times the integer registers were read -system.cpu2.num_int_register_writes 110679 # number of times the integer registers were written +system.cpu2.num_int_register_reads 249142 # number of times the integer registers were read +system.cpu2.num_int_register_writes 92045 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 57957 # number of memory refs -system.cpu2.num_load_insts 41868 # Number of load instructions -system.cpu2.num_store_insts 16089 # Number of store instructions -system.cpu2.num_idle_cycles 68998.001737 # Number of idle cycles -system.cpu2.num_busy_cycles 455599.998263 # Number of busy cycles -system.cpu2.not_idle_fraction 0.868475 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.131525 # Percentage of idle cycles -system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 65.602896 # Cycle average of tags in use -system.cpu2.icache.total_refs 165231 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 451.450820 # Average number of references to valid blocks. +system.cpu2.num_mem_refs 47896 # number of memory refs +system.cpu2.num_load_insts 40447 # Number of load instructions +system.cpu2.num_store_insts 7449 # Number of store instructions +system.cpu2.num_idle_cycles 71882.001733 # Number of idle cycles +system.cpu2.num_busy_cycles 465941.998267 # Number of busy cycles +system.cpu2.not_idle_fraction 0.866347 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.133653 # Percentage of idle cycles +system.cpu2.icache.replacements 281 # number of replacements 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for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002210 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15433.060109 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15433.060109 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 67.531468 # Average occupied blocks per requestor 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latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15557.220708 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15557.220708 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -571,100 +571,100 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed 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0.006802 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004543 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004543 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004543 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004543 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16220.779221 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16220.779221 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18633.027523 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 18633.027523 # average WriteReq miss latency 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+system.cpu2.dcache.ReadReq_miss_latency::total 3995000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2318000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2318000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 814000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 814000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 6313000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 6313000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 6313000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 6313000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40439 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40439 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 7378 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 7378 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 47817 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 47817 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 47817 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 47817 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004278 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.004278 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.014231 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.014231 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.739130 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.739130 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005814 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005814 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005814 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005814 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23092.485549 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 23092.485549 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22076.190476 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22076.190476 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15960.784314 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 15960.784314 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 22708.633094 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 22708.633094 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,114 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 154 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 173 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 263 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 263 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2036000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2036000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3740000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3740000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3740000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3740000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003679 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004543 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004543 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13220.779221 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13220.779221 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15633.027523 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15633.027523 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.demand_mshr_misses::cpu2.data 278 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 278 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 3476000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 3476000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2003000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2003000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 661000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 661000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5479000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 5479000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5479000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 5479000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004278 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004278 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014231 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.014231 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.739130 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.739130 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.005814 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.005814 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20092.485549 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 20092.485549 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19076.190476 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19076.190476 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 12960.784314 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 12960.784314 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 524598 # number of cpu cycles simulated +system.cpu3.numCycles 537824 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 166196 # Number of instructions committed -system.cpu3.committedOps 166196 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 112131 # Number of integer alu accesses +system.cpu3.committedInsts 172067 # Number of instructions committed +system.cpu3.committedOps 172067 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 111206 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 31040 # number of instructions that are conditional controls -system.cpu3.num_int_insts 112131 # number of integer instructions +system.cpu3.num_conditional_control_insts 34437 # number of instructions that are conditional controls +system.cpu3.num_int_insts 111206 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 286557 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109409 # number of times the integer registers were written +system.cpu3.num_int_register_reads 269314 # number of times the integer registers were read +system.cpu3.num_int_register_writes 101322 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57260 # number of memory refs -system.cpu3.num_load_insts 41737 # Number of load instructions -system.cpu3.num_store_insts 15523 # Number of store instructions -system.cpu3.num_idle_cycles 69252.001736 # Number of idle cycles -system.cpu3.num_busy_cycles 455345.998264 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867990 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132010 # Percentage of idle cycles -system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 67.739564 # Cycle average of tags in use -system.cpu3.icache.total_refs 165862 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 451.940054 # Average number of references to valid blocks. +system.cpu3.num_mem_refs 52937 # number of memory refs +system.cpu3.num_load_insts 41268 # Number of load instructions +system.cpu3.num_store_insts 11669 # Number of store instructions +system.cpu3.num_idle_cycles 72158.001732 # Number of idle cycles +system.cpu3.num_busy_cycles 465665.998268 # Number of busy cycles +system.cpu3.not_idle_fraction 0.865833 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.134167 # Percentage of idle cycles +system.cpu3.icache.replacements 280 # number of replacements +system.cpu3.icache.tagsinuse 65.342080 # Cycle average of tags in use +system.cpu3.icache.total_refs 171734 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 469.218579 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 67.739564 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.132304 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.132304 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 165862 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 165862 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 165862 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 165862 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 165862 # number of overall hits -system.cpu3.icache.overall_hits::total 165862 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 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-system.cpu3.icache.demand_accesses::total 166229 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 166229 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 166229 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002208 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002208 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002208 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002208 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002208 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002208 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15077.656676 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15077.656676 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15077.656676 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15077.656676 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 65.342080 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.127621 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.127621 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 171734 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 171734 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 171734 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 171734 # number of demand (read+write) hits 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cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5645500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5645500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 172100 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 172100 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 172100 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 172100 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 172100 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 172100 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002127 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002127 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002127 # miss rate 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# number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -789,100 +789,100 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 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# average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 26.774212 # Cycle average of tags in use -system.cpu3.dcache.total_refs 33417 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 25.848817 # Cycle average of tags in use +system.cpu3.dcache.total_refs 25744 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1113.900000 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 858.133333 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle 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# average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17349.809886 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17349.809886 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 25.848817 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.050486 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.050486 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41084 # number of ReadReq hits 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of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2072000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2072000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1702000 # 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system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 367 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 366 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 11 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 71 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 27 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) @@ -1082,34 +1082,34 @@ system.l2c.demand_accesses::cpu0.inst 467 # nu system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 367 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 366 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 367 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 366 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.032698 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.021858 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.268862 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.971831 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.977273 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1119,52 +1119,52 @@ system.l2c.demand_miss_rate::cpu0.inst 0.610278 # mi system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.032698 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.021858 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.326159 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.032698 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.021858 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency +system.l2c.overall_miss_rate::total 0.326159 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52028.070175 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51545.454545 # average ReadReq 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system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 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number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 880000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 361000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22883000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 600000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 322000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22890000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.971831 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.977273 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1288,29 +1285,29 @@ system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.976744 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40023.255814 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency @@ -1321,24 +1318,24 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |