stats: updates due to recent changes.

3 files changed, 191 insertions, 218 deletions

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index fe47308ed..692f001a6 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -150,7 +150,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -170,7 +170,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu0.fuPool.FUList0.opList
 [system.cpu0.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList1]
 type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 [system.cpu0.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu0.fuPool.FUList2]
 type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 sys
 [system.cpu0.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList3]
 type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 sys
 [system.cpu0.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu0.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu0.fuPool.FUList4]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu0.fuPool.FUList4.opList
 [system.cpu0.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5]
 type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 s
 [system.cpu0.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList6]
 type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu0.fuPool.FUList6.opList
 [system.cpu0.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList7]
 type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 [system.cpu0.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList8]
 type=FUDesc
@@ -493,12 +492,12 @@ opList=system.cpu0.fuPool.FUList8.opList
 [system.cpu0.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -518,7 +517,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -560,7 +558,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 kvmInSE=false
@@ -679,7 +677,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -688,7 +686,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -699,7 +697,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
@@ -735,9 +732,9 @@ opList=system.cpu1.fuPool.FUList0.opList
 [system.cpu1.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList1]
 type=FUDesc
@@ -749,16 +746,16 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 [system.cpu1.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu1.fuPool.FUList2]
 type=FUDesc
@@ -770,23 +767,23 @@ opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 sys
 [system.cpu1.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList3]
 type=FUDesc
@@ -798,23 +795,23 @@ opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 sys
 [system.cpu1.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu1.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu1.fuPool.FUList4]
 type=FUDesc
@@ -826,9 +823,9 @@ opList=system.cpu1.fuPool.FUList4.opList
 [system.cpu1.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5]
 type=FUDesc
@@ -840,142 +837,142 @@ opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 s
 [system.cpu1.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList6]
 type=FUDesc
@@ -987,9 +984,9 @@ opList=system.cpu1.fuPool.FUList6.opList
 [system.cpu1.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList7]
 type=FUDesc
@@ -1001,16 +998,16 @@ opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
 [system.cpu1.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList8]
 type=FUDesc
@@ -1022,12 +1019,12 @@ opList=system.cpu1.fuPool.FUList8.opList
 [system.cpu1.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -1036,7 +1033,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -1047,7 +1044,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
@@ -1185,7 +1181,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu2.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -1194,7 +1190,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -1205,7 +1201,6 @@ size=32768
 system=system
 tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
@@ -1241,9 +1236,9 @@ opList=system.cpu2.fuPool.FUList0.opList
 [system.cpu2.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList1]
 type=FUDesc
@@ -1255,16 +1250,16 @@ opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
 [system.cpu2.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu2.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu2.fuPool.FUList2]
 type=FUDesc
@@ -1276,23 +1271,23 @@ opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 sys
 [system.cpu2.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList3]
 type=FUDesc
@@ -1304,23 +1299,23 @@ opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 sys
 [system.cpu2.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu2.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu2.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu2.fuPool.FUList4]
 type=FUDesc
@@ -1332,9 +1327,9 @@ opList=system.cpu2.fuPool.FUList4.opList
 [system.cpu2.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5]
 type=FUDesc
@@ -1346,142 +1341,142 @@ opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 s
 [system.cpu2.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList6]
 type=FUDesc
@@ -1493,9 +1488,9 @@ opList=system.cpu2.fuPool.FUList6.opList
 [system.cpu2.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7]
 type=FUDesc
@@ -1507,16 +1502,16 @@ opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
 [system.cpu2.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList8]
 type=FUDesc
@@ -1528,12 +1523,12 @@ opList=system.cpu2.fuPool.FUList8.opList
 [system.cpu2.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu2.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -1542,7 +1537,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -1553,7 +1548,6 @@ size=32768
 system=system
 tags=system.cpu2.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
@@ -1691,7 +1685,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu3.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -1700,7 +1694,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -1711,7 +1705,6 @@ size=32768
 system=system
 tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
@@ -1747,9 +1740,9 @@ opList=system.cpu3.fuPool.FUList0.opList
 [system.cpu3.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList1]
 type=FUDesc
@@ -1761,16 +1754,16 @@ opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1
 [system.cpu3.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu3.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu3.fuPool.FUList2]
 type=FUDesc
@@ -1782,23 +1775,23 @@ opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 sys
 [system.cpu3.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu3.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu3.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu3.fuPool.FUList3]
 type=FUDesc
@@ -1810,23 +1803,23 @@ opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 sys
 [system.cpu3.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu3.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu3.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu3.fuPool.FUList4]
 type=FUDesc
@@ -1838,9 +1831,9 @@ opList=system.cpu3.fuPool.FUList4.opList
 [system.cpu3.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5]
 type=FUDesc
@@ -1852,142 +1845,142 @@ opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 s
 [system.cpu3.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList6]
 type=FUDesc
@@ -1999,9 +1992,9 @@ opList=system.cpu3.fuPool.FUList6.opList
 [system.cpu3.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList7]
 type=FUDesc
@@ -2013,16 +2006,16 @@ opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
 [system.cpu3.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu3.fuPool.FUList8]
 type=FUDesc
@@ -2034,12 +2027,12 @@ opList=system.cpu3.fuPool.FUList8.opList
 [system.cpu3.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu3.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -2048,7 +2041,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -2059,7 +2052,6 @@ size=32768
 system=system
 tags=system.cpu3.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
@@ -2108,7 +2100,7 @@ sys_clk_domain=system.clk_domain
 transition_latency=100000000
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -2117,7 +2109,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -2128,7 +2120,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 0b278b17c..e0e7586ea 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -82,7 +82,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -91,7 +91,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -102,7 +102,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -123,7 +122,7 @@ eventq_index=0
 size=64
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -132,7 +131,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -143,7 +142,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -236,7 +234,7 @@ dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -245,7 +243,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -256,7 +254,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
@@ -277,7 +274,7 @@ eventq_index=0
 size=64
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -286,7 +283,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -297,7 +294,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
@@ -367,7 +363,7 @@ dcache_port=system.cpu2.dcache.cpu_side
 icache_port=system.cpu2.icache.cpu_side
 
 [system.cpu2.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -376,7 +372,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -387,7 +383,6 @@ size=32768
 system=system
 tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
@@ -408,7 +403,7 @@ eventq_index=0
 size=64
 
 [system.cpu2.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -417,7 +412,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -428,7 +423,6 @@ size=32768
 system=system
 tags=system.cpu2.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
@@ -498,7 +492,7 @@ dcache_port=system.cpu3.dcache.cpu_side
 icache_port=system.cpu3.icache.cpu_side
 
 [system.cpu3.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -507,7 +501,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -518,7 +512,6 @@ size=32768
 system=system
 tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
@@ -539,7 +532,7 @@ eventq_index=0
 size=64
 
 [system.cpu3.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -548,7 +541,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -559,7 +552,6 @@ size=32768
 system=system
 tags=system.cpu3.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
@@ -608,7 +600,7 @@ sys_clk_domain=system.clk_domain
 transition_latency=100000000
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -617,7 +609,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -628,7 +620,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 68e115348..413a26622 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -78,7 +78,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -87,7 +87,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -98,7 +98,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -119,7 +118,7 @@ eventq_index=0
 size=64
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -128,7 +127,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -139,7 +138,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -228,7 +226,7 @@ dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -237,7 +235,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -248,7 +246,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
@@ -269,7 +266,7 @@ eventq_index=0
 size=64
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -278,7 +275,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -289,7 +286,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
@@ -355,7 +351,7 @@ dcache_port=system.cpu2.dcache.cpu_side
 icache_port=system.cpu2.icache.cpu_side
 
 [system.cpu2.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -364,7 +360,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -375,7 +371,6 @@ size=32768
 system=system
 tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
@@ -396,7 +391,7 @@ eventq_index=0
 size=64
 
 [system.cpu2.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -405,7 +400,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -416,7 +411,6 @@ size=32768
 system=system
 tags=system.cpu2.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
@@ -482,7 +476,7 @@ dcache_port=system.cpu3.dcache.cpu_side
 icache_port=system.cpu3.icache.cpu_side
 
 [system.cpu3.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -491,7 +485,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -502,7 +496,6 @@ size=32768
 system=system
 tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
@@ -523,7 +516,7 @@ eventq_index=0
 size=64
 
 [system.cpu3.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -532,7 +525,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -543,7 +536,6 @@ size=32768
 system=system
 tags=system.cpu3.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
@@ -592,7 +584,7 @@ sys_clk_domain=system.clk_domain
 transition_latency=100000000
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -601,7 +593,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -612,7 +604,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]