diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/quick/se/40.m5threads-test-atomic/ref | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref')
3 files changed, 2972 insertions, 2974 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 459938f5d..31446f740 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 107836000 # Number of ticks simulated -final_tick 107836000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107700000 # Number of ticks simulated +final_tick 107700000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68965 # Simulator instruction rate (inst/s) -host_op_rate 68965 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7480497 # Simulator tick rate (ticks/s) -host_mem_usage 247424 # Number of bytes of host memory used -host_seconds 14.42 # Real time elapsed on the host -sim_insts 994171 # Number of instructions simulated -sim_ops 994171 # Number of ops (including micro ops) simulated +host_inst_rate 155633 # Simulator instruction rate (inst/s) +host_op_rate 155632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16853882 # Simulator tick rate (ticks/s) +host_mem_usage 312924 # Number of bytes of host memory used +host_seconds 6.39 # Real time elapsed on the host +sim_insts 994522 # Number of instructions simulated +sim_ops 994522 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42560 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 665 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 213657777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 100300456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47479506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11869876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1780481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7715420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 4154457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7715420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 394673393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213657777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47479506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1780481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 4154457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267072221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213657777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 100300456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47479506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11869876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1780481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7715420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 4154457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7715420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 394673393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213927577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100427112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 48727948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11884865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 3565460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7725162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1188487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7725162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 395171773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213927577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 48727948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 3565460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1188487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267409471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213927577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100427112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 48727948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11884865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 3565460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7725162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1188487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7725162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 395171773 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 666 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue @@ -70,7 +70,7 @@ system.physmem.bytesReadSys 42624 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 30 # Per bank write bursts @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107808000 # Total gap between requests +system.physmem.totGap 107672000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -230,15 +230,15 @@ system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # By system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation -system.physmem.totQLat 6565250 # Total ticks spent queuing -system.physmem.totMemAccLat 19052750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6586250 # Total ticks spent queuing +system.physmem.totMemAccLat 19073750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9857.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9889.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28607.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 395.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28639.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 395.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 395.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 395.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.09 # Data bus utilization in percentage @@ -250,169 +250,169 @@ system.physmem.readRowHits 510 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 161873.87 # Average gap between requests +system.physmem.avgGap 161669.67 # Average gap between requests system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 38088540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27477750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 76044960 # Total energy per rank (pJ) -system.physmem_0.averagePower 749.349855 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47969250 # Time in different power states +system.physmem_0.actBackEnergy 38199690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27380250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76058610 # Total energy per rank (pJ) +system.physmem_0.averagePower 749.484363 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 47670750 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 52649750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 52812250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 32065065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32761500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 74015040 # Total energy per rank (pJ) -system.physmem_1.averagePower 729.346948 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57811250 # Time in different power states +system.physmem_1.actBackEnergy 32151420 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32685750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 74025645 # Total energy per rank (pJ) +system.physmem_1.averagePower 729.451450 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57549250 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 43803750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 43929750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81652 # Number of BP lookups -system.cpu0.branchPred.condPredicted 79008 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 81595 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78953 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78985 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 76270 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 78929 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 76214 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.562638 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 96.560200 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 215673 # number of cpu cycles simulated +system.cpu0.numCycles 215401 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19729 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 482689 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81652 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76915 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 165939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.icacheStallCycles 19727 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 482343 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81595 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76859 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165670 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6734 # Number of cache lines fetched +system.cpu0.fetch.PendingTrapStallCycles 1993 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6732 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 189011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.553761 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.213837 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 188739 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.555609 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.213598 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30617 16.20% 16.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78326 41.44% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 798 0.42% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1203 0.64% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 614 0.32% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 73725 39.01% 98.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 672 0.36% 98.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 403 0.21% 98.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2653 1.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30459 16.14% 16.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78270 41.47% 57.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 797 0.42% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1203 0.64% 58.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 613 0.32% 58.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73671 39.03% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2652 1.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 189011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.378592 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.238059 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15475 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18570 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 153063 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 653 # Number of cycles decode is unblocking +system.cpu0.fetch.rateDist::total 188739 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.378805 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.239279 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15463 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18382 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152999 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 645 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 472193 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 471851 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16079 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2117 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15116 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 153063 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1386 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 469016 # Number of instructions processed by rename +system.cpu0.rename.IdleCycles 16060 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2005 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15072 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152998 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1354 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 468673 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 320676 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 935403 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 706479 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 307583 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13093 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4383 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 150037 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75873 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 73364 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72959 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 392343 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.SQFullEvents 851 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 320440 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 934717 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 705961 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 307367 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13073 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4337 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 149926 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75817 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 73307 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72919 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 392051 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 388906 # Number of instructions issued +system.cpu0.iq.iqInstsIssued 388622 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12322 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11733 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedInstsExamined 12300 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11714 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 189011 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.057584 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.125737 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 188739 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.059045 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.124370 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33687 17.82% 17.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4243 2.24% 20.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 74165 39.24% 59.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73776 39.03% 98.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1622 0.86% 99.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 405 0.21% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33524 17.76% 17.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4207 2.23% 19.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 74141 39.28% 59.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73776 39.09% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1579 0.84% 99.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 884 0.47% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 404 0.21% 99.88% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 189011 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 188739 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61 21.18% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 124 43.06% 64.24% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 35.76% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 164396 42.27% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164274 42.27% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued @@ -441,40 +441,40 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 149390 38.41% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 75120 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 149282 38.41% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 75066 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 388906 # Type of FU issued -system.cpu0.iq.rate 1.803221 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000743 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 967143 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405616 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 387054 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 388622 # Type of FU issued +system.cpu0.iq.rate 1.804179 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 288 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000741 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 966302 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405302 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 386770 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 389195 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 388910 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 72474 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 72419 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1676 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2081 # Number of cycles IEW is blocking +system.cpu0.iew.iewBlockCycles 1969 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 466895 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispatchedInsts 466549 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 150037 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75873 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 149926 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75817 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -482,53 +482,53 @@ system.cpu0.iew.memOrderViolationEvents 63 # Nu system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 387894 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 149051 # Number of load instructions executed +system.cpu0.iew.iewExecutedInsts 387610 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 148943 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 73663 # number of nop insts executed -system.cpu0.iew.exec_refs 224021 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76988 # Number of branches executed -system.cpu0.iew.exec_stores 74970 # Number of stores executed -system.cpu0.iew.exec_rate 1.798528 # Inst execution rate -system.cpu0.iew.wb_sent 387462 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 387054 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 229603 # num instructions producing a value -system.cpu0.iew.wb_consumers 232649 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.794634 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986907 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 13111 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 73609 # number of nop insts executed +system.cpu0.iew.exec_refs 223859 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76931 # Number of branches executed +system.cpu0.iew.exec_stores 74916 # Number of stores executed +system.cpu0.iew.exec_rate 1.799481 # Inst execution rate +system.cpu0.iew.wb_sent 387178 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 386770 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 229443 # num instructions producing a value +system.cpu0.iew.wb_consumers 232488 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.795581 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986903 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 13089 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186547 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.432234 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.149146 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 186278 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.434007 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.148610 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33930 18.19% 18.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 76047 40.77% 58.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 670 0.36% 60.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 524 0.28% 60.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 72154 38.68% 99.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 534 0.29% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33753 18.12% 18.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 76007 40.80% 58.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 664 0.36% 60.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 518 0.28% 60.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 72154 38.73% 99.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 496 0.27% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186547 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 453726 # Number of instructions committed -system.cpu0.commit.committedOps 453726 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186278 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453402 # Number of instructions committed +system.cpu0.commit.committedOps 453402 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 221578 # Number of memory references committed -system.cpu0.commit.loads 147381 # Number of loads committed +system.cpu0.commit.refs 221416 # Number of memory references committed +system.cpu0.commit.loads 147273 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 76084 # Number of branches committed +system.cpu0.commit.branches 76030 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 305914 # Number of committed integer instructions. +system.cpu0.commit.int_insts 305698 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72816 16.05% 16.05% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 159248 35.10% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72762 16.05% 16.05% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 159140 35.10% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction @@ -557,103 +557,103 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 147465 32.50% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 74197 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 147357 32.50% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 74143 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 453726 # Class of committed instruction +system.cpu0.commit.op_class_0::total 453402 # Class of committed instruction system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 651740 # The number of ROB reads -system.cpu0.rob.rob_writes 936154 # The number of ROB writes +system.cpu0.rob.rob_reads 651125 # The number of ROB reads +system.cpu0.rob.rob_writes 935459 # The number of ROB writes system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 26662 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 380826 # Number of Instructions Simulated -system.cpu0.committedOps 380826 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.566330 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.566330 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.765756 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.765756 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 693989 # number of integer regfile reads -system.cpu0.int_regfile_writes 312909 # number of integer regfile writes +system.cpu0.committedInsts 380556 # Number of Instructions Simulated +system.cpu0.committedOps 380556 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.566017 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.566017 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.766733 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.766733 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 693485 # number of integer regfile reads +system.cpu0.int_regfile_writes 312678 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 225890 # number of misc regfile reads +system.cpu0.misc_regfile_reads 225727 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.137199 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 149509 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.118700 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149407 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 874.321637 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 873.725146 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.137199 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275659 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275659 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.118700 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275622 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275622 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 603167 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 603167 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75961 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75961 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73598 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73598 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 602739 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 602739 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75912 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75912 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73546 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73546 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149559 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149559 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149559 # number of overall hits -system.cpu0.dcache.overall_hits::total 149559 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 557 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 557 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 149458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 149458 # number of overall hits +system.cpu0.dcache.overall_hits::total 149458 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 553 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 553 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses -system.cpu0.dcache.overall_misses::total 1114 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17293500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17293500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34774980 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 34774980 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1108 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1108 # number of overall misses +system.cpu0.dcache.overall_misses::total 1108 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16789000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16789000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34744480 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 34744480 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 52068480 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 52068480 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 52068480 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 52068480 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 76518 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 76518 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74155 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74155 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 51533480 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 51533480 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 51533480 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 51533480 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 76465 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 76465 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74101 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74101 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 150673 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 150673 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150673 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150673 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007279 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.007279 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007511 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007511 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 150566 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 150566 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150566 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150566 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007232 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007232 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007490 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007490 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007393 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007393 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007393 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007393 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31047.576302 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31047.576302 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62432.639138 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 62432.639138 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007359 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007359 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007359 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007359 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30359.855335 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30359.855335 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62602.666667 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 62602.666667 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46740.107720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46740.107720 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46510.361011 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46510.361011 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -664,107 +664,107 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 375 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 375 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 378 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 378 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 748 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 748 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 748 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 748 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6892000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6892000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8487000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8487000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8423500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8423500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15379000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15379000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15379000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15379000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002379 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002379 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002400 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15276500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15276500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15276500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15276500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002393 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002393 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002389 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002389 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002389 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37868.131868 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37868.131868 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47679.775281 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47679.775281 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002391 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002391 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37448.087432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37448.087432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47590.395480 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47590.395480 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 315 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.200073 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5951 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 241.159002 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.803954 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.200073 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471094 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471094 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.159002 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471014 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471014 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7341 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7341 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5951 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5951 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5951 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5951 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5951 # number of overall hits -system.cpu0.icache.overall_hits::total 5951 # number of overall hits +system.cpu0.icache.tags.tag_accesses 7339 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7339 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits +system.cpu0.icache.overall_hits::total 5949 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 783 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 783 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 783 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 783 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 783 # number of overall misses system.cpu0.icache.overall_misses::total 783 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40367500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40367500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40367500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40367500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40367500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40367500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6734 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6734 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6734 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6734 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6734 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6734 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116276 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116276 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116276 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116276 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116276 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116276 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51554.916986 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 51554.916986 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 51554.916986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 51554.916986 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40394500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40394500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40394500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40394500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40394500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40394500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6732 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6732 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6732 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6732 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116310 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116310 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116310 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116310 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116310 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116310 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51589.399745 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51589.399745 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51589.399745 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51589.399745 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -787,396 +787,397 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31309500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31309500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31309500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31309500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31309500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31309500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090288 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090288 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090288 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51495.888158 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31312500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31312500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31312500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31312500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31312500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31312500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090315 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090315 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090315 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51500.822368 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 53782 # Number of BP lookups -system.cpu1.branchPred.condPredicted 50347 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1277 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46315 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 45397 # Number of BTB hits +system.cpu1.branchPred.lookups 52270 # Number of BP lookups +system.cpu1.branchPred.condPredicted 48857 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1261 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 45038 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 43957 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.017921 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.599805 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 912 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 162898 # number of cpu cycles simulated +system.cpu1.numCycles 162626 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 29679 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 299544 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53782 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46296 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 124703 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 30636 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 289541 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52270 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 44869 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 123502 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20165 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 457 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 156846 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.909797 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.217375 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 21117 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 458 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.849098 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199028 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 53057 33.83% 33.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52143 33.24% 67.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5878 3.75% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3526 2.25% 73.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 939 0.60% 73.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 35272 22.49% 96.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1247 0.80% 96.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 803 0.51% 97.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3981 2.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 55186 35.24% 35.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51235 32.72% 67.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6397 4.09% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3507 2.24% 74.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 942 0.60% 74.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 33361 21.31% 96.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1213 0.77% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 812 0.52% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3932 2.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 156846 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.330158 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.838844 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17882 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 51023 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 83554 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3022 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1355 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 284108 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1355 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18601 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22664 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13899 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 84840 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 15477 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 280728 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 13732 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 156585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.321412 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.780410 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17913 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 54188 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 79912 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3224 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1338 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 274398 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1338 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18610 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 24678 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13550 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 81416 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 16983 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 271226 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 15241 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 198394 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 541219 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 420944 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 184552 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13842 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1192 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 20109 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 79403 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 37516 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 32939 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 234221 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5649 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 235400 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12841 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 661 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 156846 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.500835 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.378978 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 191192 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 520363 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 405271 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 177667 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13525 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 21370 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 76128 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 36144 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 36135 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 31079 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 225686 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6135 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 227404 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12625 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.452272 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.380275 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 56627 36.10% 36.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 19405 12.37% 48.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 37510 23.92% 72.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 37026 23.61% 96.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3380 2.15% 98.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1607 1.02% 99.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 891 0.57% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 204 0.13% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 58755 37.52% 37.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 20747 13.25% 50.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35642 22.76% 73.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 35172 22.46% 96.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3374 2.15% 98.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1612 1.03% 99.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 878 0.56% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 207 0.13% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 198 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 156846 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156585 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 79 24.38% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 36 11.11% 35.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 64.51% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 79 24.01% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 41 12.46% 36.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 63.53% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 114995 48.85% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 82971 35.25% 84.10% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37434 15.90% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 111654 49.10% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 80158 35.25% 84.35% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 35592 15.65% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 235400 # Type of FU issued -system.cpu1.iq.rate 1.445076 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 324 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001376 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 627977 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 252747 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 233879 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 227404 # Type of FU issued +system.cpu1.iq.rate 1.398325 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 329 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001447 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 611730 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 244482 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 225916 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 235724 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 227733 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 32768 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30932 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2551 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1483 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1427 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6889 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 278263 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 133 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 79403 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7175 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 268817 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 146 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 76128 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 36144 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 442 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 234388 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 78381 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 440 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1492 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 226425 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 75137 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 979 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 38393 # number of nop insts executed -system.cpu1.iew.exec_refs 115730 # number of memory reference insts executed -system.cpu1.iew.exec_branches 47858 # Number of branches executed -system.cpu1.iew.exec_stores 37349 # Number of stores executed -system.cpu1.iew.exec_rate 1.438864 # Inst execution rate -system.cpu1.iew.wb_sent 234148 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 233879 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 133368 # num instructions producing a value -system.cpu1.iew.wb_consumers 139978 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.435739 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.952778 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 13605 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4988 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1277 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 154309 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.714761 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.081585 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 36996 # number of nop insts executed +system.cpu1.iew.exec_refs 110644 # number of memory reference insts executed +system.cpu1.iew.exec_branches 46426 # Number of branches executed +system.cpu1.iew.exec_stores 35507 # Number of stores executed +system.cpu1.iew.exec_rate 1.392305 # Inst execution rate +system.cpu1.iew.wb_sent 226182 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 225916 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 128242 # num instructions producing a value +system.cpu1.iew.wb_consumers 134834 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.389175 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.951110 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 13383 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5429 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1261 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 154086 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.657380 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.063453 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61394 39.79% 39.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 44430 28.79% 68.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5247 3.40% 71.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5803 3.76% 75.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1533 0.99% 76.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 32828 21.27% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 824 0.53% 98.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1304 0.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 63982 41.52% 41.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 43006 27.91% 69.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5237 3.40% 72.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6258 4.06% 76.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1532 0.99% 77.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30979 20.11% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 844 0.55% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1302 0.84% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 154309 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 264603 # Number of instructions committed -system.cpu1.commit.committedOps 264603 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 154086 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 255379 # Number of instructions committed +system.cpu1.commit.committedOps 255379 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 113401 # Number of memory references committed -system.cpu1.commit.loads 76852 # Number of loads committed -system.cpu1.commit.membars 4272 # Number of memory barriers committed -system.cpu1.commit.branches 46786 # Number of branches committed +system.cpu1.commit.refs 108350 # Number of memory references committed +system.cpu1.commit.loads 73633 # Number of loads committed +system.cpu1.commit.membars 4715 # Number of memory barriers committed +system.cpu1.commit.branches 45393 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 182306 # Number of committed integer instructions. +system.cpu1.commit.int_insts 175866 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 37574 14.20% 14.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 109356 41.33% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 81124 30.66% 86.19% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 36549 13.81% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 36183 14.17% 14.17% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 106131 41.56% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 78348 30.68% 86.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 34717 13.59% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 264603 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 430627 # The number of ROB reads -system.cpu1.rob.rob_writes 558953 # The number of ROB writes -system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6052 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.commit.op_class_0::total 255379 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1302 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 420960 # The number of ROB reads +system.cpu1.rob.rob_writes 540023 # The number of ROB writes +system.cpu1.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6041 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 45271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 222757 # Number of Instructions Simulated -system.cpu1.committedOps 222757 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.731281 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.731281 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.367463 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.367463 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 407061 # number of integer regfile reads -system.cpu1.int_regfile_writes 190501 # number of integer regfile writes +system.cpu1.committedInsts 214481 # Number of Instructions Simulated +system.cpu1.committedOps 214481 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.758230 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.758230 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.318860 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.318860 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391734 # number of integer regfile reads +system.cpu1.int_regfile_writes 183502 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 117378 # number of misc regfile reads +system.cpu1.misc_regfile_reads 112279 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.769381 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 42560 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1520 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.736588 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 40830 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1407.931034 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.769381 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.736588 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050267 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050267 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 328816 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 328816 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 45076 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 45076 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 36319 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 36319 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 81395 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 81395 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 81395 # number of overall hits -system.cpu1.dcache.overall_hits::total 81395 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 515 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 515 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 675 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 675 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 675 # number of overall misses -system.cpu1.dcache.overall_misses::total 675 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10357000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 10357000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3384000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3384000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 705000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 705000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13741000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13741000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13741000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13741000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 45591 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 45591 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 36479 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 36479 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 82070 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 82070 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 82070 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 82070 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011296 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011296 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004386 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004386 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008225 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.008225 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008225 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.008225 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20110.679612 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20110.679612 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21150 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21150 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12589.285714 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 12589.285714 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20357.037037 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20357.037037 # average overall miss latency +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 315852 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 315852 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 43688 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 43688 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 34492 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 34492 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 17 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 17 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 78180 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 78180 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 78180 # number of overall hits +system.cpu1.dcache.overall_hits::total 78180 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 495 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 495 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 157 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 157 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # 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number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12331000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12331000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12331000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 44183 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 44183 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 34649 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 34649 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 78832 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 78832 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 78832 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 78832 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011203 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011203 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004531 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004531 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.750000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.750000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008271 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.008271 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008271 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.008271 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18115.151515 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18115.151515 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21426.751592 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21426.751592 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11745.098039 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 11745.098039 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18912.576687 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18912.576687 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,106 +1186,106 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 349 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 349 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 402 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 402 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 402 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 273 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 273 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2153500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2153500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1760500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1760500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 649000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 649000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3914000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3914000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3914000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3914000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003641 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003641 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002933 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002933 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003326 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003326 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12972.891566 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12972.891566 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16453.271028 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16453.271028 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11589.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11589.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 331 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 51 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 382 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 382 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 382 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1748500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 548000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 548000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3736500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3736500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3736500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3736500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003712 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003712 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003059 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003059 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.750000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003425 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003425 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12121.951220 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12121.951220 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16495.283019 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16495.283019 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10745.098039 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10745.098039 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 383 # number of replacements -system.cpu1.icache.tags.tagsinuse 84.449474 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19585 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 84.417280 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20534 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.485887 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 41.399194 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.449474 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164940 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.164940 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.417280 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164877 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.164877 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 20661 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 20661 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 19585 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19585 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19585 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19585 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19585 # number of overall hits -system.cpu1.icache.overall_hits::total 19585 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 580 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 580 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 580 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 580 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 580 # number of overall misses -system.cpu1.icache.overall_misses::total 580 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14033000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 14033000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 14033000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 14033000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 14033000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 14033000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20165 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20165 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20165 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20165 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20165 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20165 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028763 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.028763 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028763 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.028763 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028763 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.028763 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24194.827586 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24194.827586 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24194.827586 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24194.827586 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21613 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21613 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20534 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20534 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20534 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20534 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20534 # number of overall hits +system.cpu1.icache.overall_hits::total 20534 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 583 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 583 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 583 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 583 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 583 # number of overall misses +system.cpu1.icache.overall_misses::total 583 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14299500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14299500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14299500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14299500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14299500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14299500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21117 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21117 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21117 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21117 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21117 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21117 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027608 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.027608 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027608 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.027608 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027608 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.027608 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24527.444254 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24527.444254 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24527.444254 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24527.444254 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1295,408 +1296,407 @@ system.cpu1.icache.fast_writes 0 # nu system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 383 # number of writebacks system.cpu1.icache.writebacks::total 383 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 84 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 84 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 84 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 84 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 87 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 87 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11668000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11668000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11668000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11668000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11668000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11668000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024597 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024597 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024597 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23524.193548 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11785500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11785500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11785500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11785500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11785500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11785500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023488 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023488 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023488 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23761.088710 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 46151 # Number of BP lookups -system.cpu2.branchPred.condPredicted 42669 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1261 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 38744 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 37721 # Number of BTB hits +system.cpu2.branchPred.lookups 51016 # Number of BP lookups +system.cpu2.branchPred.condPredicted 47608 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1273 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 43707 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 42688 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.359591 # BTB Hit Percentage +system.cpu2.branchPred.BTBHitPct 97.668566 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 903 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 162526 # number of cpu cycles simulated +system.cpu2.numCycles 162253 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 35053 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 247865 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 46151 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 38624 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 123337 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2679 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 31836 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 280333 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51016 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 43591 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 126252 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2703 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 26088 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 160896 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.540529 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.092892 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1153 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 22874 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 160605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.745481 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.165535 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 69454 43.17% 43.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 47444 29.49% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8853 5.50% 78.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3439 2.14% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 969 0.60% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 24720 15.36% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1203 0.75% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 808 0.50% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4006 2.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 60810 37.86% 37.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 50841 31.66% 69.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7311 4.55% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3498 2.18% 76.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 961 0.60% 76.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 31234 19.45% 96.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1226 0.76% 97.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 786 0.49% 97.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3938 2.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 160896 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.283961 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.525079 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17877 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 74268 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 63015 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4387 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1339 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 232406 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1339 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18566 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 36272 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13923 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 64728 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 26058 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 229231 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 23352 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 160605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.314423 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.727752 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17488 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 62772 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 75260 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3724 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1351 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 265175 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1351 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18185 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 29493 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13900 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 76790 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 20876 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 262017 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 18650 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 159189 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 426806 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 335096 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 145681 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13508 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1198 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1266 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 30557 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 61312 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 27565 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 29913 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 22477 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 187400 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8554 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 191519 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 12551 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10065 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 160896 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.190328 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.355636 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 183428 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 498093 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 388599 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 169446 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13982 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1189 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1258 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 25354 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 72684 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33991 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 34917 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 28890 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 216663 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7106 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 219007 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11098 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 160605 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.363637 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.376138 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73129 45.45% 45.45% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 27885 17.33% 62.78% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 27023 16.80% 79.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 26608 16.54% 96.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3367 2.09% 98.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 866 0.54% 99.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 64456 40.13% 40.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23625 14.71% 54.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33318 20.75% 75.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 32915 20.49% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3374 2.10% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 893 0.56% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 160896 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 160605 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 80 24.02% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 44 13.21% 37.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 96792 50.54% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 67722 35.36% 85.90% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 27005 14.10% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 108075 49.35% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 77606 35.44% 84.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 33326 15.22% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 191519 # Type of FU issued -system.cpu2.iq.rate 1.178390 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 333 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001739 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 544280 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 208542 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 190032 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 219007 # Type of FU issued +system.cpu2.iq.rate 1.349787 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001566 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 598981 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 236927 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 217448 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 191852 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 219350 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 22329 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 28643 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2475 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2671 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1441 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1575 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1339 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9482 # Number of cycles IEW is blocking +system.cpu2.iew.iewSquashCycles 1351 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 8096 # Number of cycles IEW is blocking system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 226726 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 61312 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 27565 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1142 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewDispatchedInsts 259522 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 72684 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33991 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1139 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 190532 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 60316 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 987 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1062 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 217972 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 71586 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1035 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 30772 # number of nop insts executed -system.cpu2.iew.exec_refs 87235 # number of memory reference insts executed -system.cpu2.iew.exec_branches 40210 # Number of branches executed -system.cpu2.iew.exec_stores 26919 # Number of stores executed -system.cpu2.iew.exec_rate 1.172317 # Inst execution rate -system.cpu2.iew.wb_sent 190296 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 190032 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 104798 # num instructions producing a value -system.cpu2.iew.wb_consumers 111375 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.169241 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.940947 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 13298 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7823 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1261 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 158397 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.347140 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.933730 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 35753 # number of nop insts executed +system.cpu2.iew.exec_refs 104818 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45124 # Number of branches executed +system.cpu2.iew.exec_stores 33232 # Number of stores executed +system.cpu2.iew.exec_rate 1.343408 # Inst execution rate +system.cpu2.iew.wb_sent 217734 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 217448 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 122408 # num instructions producing a value +system.cpu2.iew.wb_consumers 129014 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.340179 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.948796 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 13957 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6419 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1273 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 158015 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.553777 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.025126 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 80708 50.95% 50.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 36780 23.22% 74.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5258 3.32% 77.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8633 5.45% 82.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1531 0.97% 83.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 22393 14.14% 98.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 849 0.54% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 955 0.60% 99.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1290 0.81% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 70555 44.65% 44.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 41677 26.38% 71.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5250 3.32% 74.35% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7214 4.57% 78.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1535 0.97% 79.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28695 18.16% 98.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 838 0.53% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 950 0.60% 99.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1301 0.82% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 158397 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 213383 # Number of instructions committed -system.cpu2.commit.committedOps 213383 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 158015 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 245520 # Number of instructions committed +system.cpu2.commit.committedOps 245520 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 84961 # Number of memory references committed -system.cpu2.commit.loads 58837 # Number of loads committed -system.cpu2.commit.membars 7109 # Number of memory barriers committed -system.cpu2.commit.branches 39190 # Number of branches committed +system.cpu2.commit.refs 102429 # Number of memory references committed +system.cpu2.commit.loads 70013 # Number of loads committed +system.cpu2.commit.membars 5702 # Number of memory barriers committed +system.cpu2.commit.branches 44083 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 146276 # Number of committed integer instructions. +system.cpu2.commit.int_insts 168630 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 29980 14.05% 14.05% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 91333 42.80% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 65946 30.90% 87.76% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 26124 12.24% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 34870 14.20% 14.20% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 102519 41.76% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 75715 30.84% 86.80% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 32416 13.20% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 213383 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1290 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 383202 # The number of ROB reads -system.cpu2.rob.rob_writes 455861 # The number of ROB writes -system.cpu2.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1630 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.commit.op_class_0::total 245520 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 415605 # The number of ROB reads +system.cpu2.rob.rob_writes 521544 # The number of ROB writes +system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1648 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 45643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 176294 # Number of Instructions Simulated -system.cpu2.committedOps 176294 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.921903 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.921903 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.084713 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.084713 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 321409 # number of integer regfile reads -system.cpu2.int_regfile_writes 151400 # number of integer regfile writes +system.cpu2.committedInsts 204948 # Number of Instructions Simulated +system.cpu2.committedOps 204948 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.791679 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.791679 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.263138 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.263138 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 374158 # number of integer regfile reads +system.cpu2.int_regfile_writes 175347 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88848 # number of misc regfile reads +system.cpu2.misc_regfile_reads 106430 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 23.120660 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 32242 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1111.793103 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 23.147052 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 38440 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1372.857143 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.120660 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045158 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.045158 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.147052 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045209 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.045209 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 256599 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 256599 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 37491 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 37491 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 25903 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 25903 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 63394 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 63394 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 63394 # number of overall hits -system.cpu2.dcache.overall_hits::total 63394 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 473 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 473 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 153 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 153 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 626 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 626 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 626 # number of overall misses -system.cpu2.dcache.overall_misses::total 626 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7957500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7957500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3701500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3701500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 605000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 605000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 11659000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 11659000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 11659000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 11659000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 37964 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 37964 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 26056 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 26056 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 64020 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 64020 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 64020 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 64020 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012459 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.012459 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005872 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.005872 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.720588 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.720588 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009778 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.009778 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009778 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.009778 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16823.467230 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16823.467230 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24192.810458 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 24192.810458 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12346.938776 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 12346.938776 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 18624.600639 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 18624.600639 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 301603 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 301603 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42391 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42391 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 32186 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 32186 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 74577 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 74577 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 74577 # number of overall hits +system.cpu2.dcache.overall_hits::total 74577 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 529 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 529 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 688 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 688 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 688 # number of overall misses +system.cpu2.dcache.overall_misses::total 688 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8601000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 8601000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3593000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3593000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 655000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 655000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 12194000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 12194000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 12194000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 12194000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42920 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42920 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 32345 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 32345 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 75265 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 75265 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 75265 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 75265 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012325 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.012325 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004916 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004916 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009141 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.009141 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009141 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.009141 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16258.979206 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16258.979206 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22597.484277 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22597.484277 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11293.103448 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 11293.103448 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17723.837209 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17723.837209 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1705,106 +1705,106 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 50 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 50 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 361 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 361 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1647500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1647500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1967500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1967500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 556000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 556000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3615000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3615000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3615000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3615000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004267 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004267 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003953 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003953 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.720588 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.720588 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004139 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004139 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10169.753086 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10169.753086 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19101.941748 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19101.941748 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11346.938776 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11346.938776 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 359 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 359 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 412 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 412 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 276 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 276 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1653000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1653000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1845000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 597000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 597000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3498000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3498000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3498000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3498000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003961 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003961 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003277 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003667 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003667 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9723.529412 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9723.529412 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17405.660377 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17405.660377 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10293.103448 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10293.103448 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 386 # number of replacements -system.cpu2.icache.tags.tagsinuse 77.580266 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 25515 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 77.661611 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 22304 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 51.030000 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 44.608000 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.580266 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151524 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.151524 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.661611 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151683 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.151683 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 26588 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 26588 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 25515 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 25515 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 25515 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 25515 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 25515 # number of overall hits -system.cpu2.icache.overall_hits::total 25515 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses -system.cpu2.icache.overall_misses::total 573 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7955500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7955500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7955500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7955500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7955500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7955500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 26088 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 26088 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 26088 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 26088 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 26088 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 26088 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021964 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.021964 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021964 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.021964 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021964 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.021964 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13883.944154 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13883.944154 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13883.944154 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13883.944154 # average overall miss latency +system.cpu2.icache.tags.tag_accesses 23374 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 23374 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 22304 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 22304 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 22304 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 22304 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 22304 # number of overall hits +system.cpu2.icache.overall_hits::total 22304 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses +system.cpu2.icache.overall_misses::total 570 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8095000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8095000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8095000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8095000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8095000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8095000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 22874 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 22874 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 22874 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 22874 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 22874 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 22874 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024919 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024919 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024919 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024919 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024919 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024919 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14201.754386 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14201.754386 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14201.754386 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14201.754386 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1815,407 +1815,407 @@ system.cpu2.icache.fast_writes 0 # nu system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks::writebacks 386 # number of writebacks system.cpu2.icache.writebacks::total 386 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 70 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 70 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 70 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6895000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6895000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6895000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6895000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6895000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6895000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019166 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.019166 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.019166 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13790 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13790 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7049500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7049500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7049500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7049500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7049500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7049500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021859 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021859 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021859 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14099 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14099 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 52678 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49211 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1284 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 45275 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 44303 # Number of BTB hits +system.cpu3.branchPred.lookups 49230 # Number of BP lookups +system.cpu3.branchPred.condPredicted 45728 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1271 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 41796 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 40803 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.853120 # BTB Hit Percentage +system.cpu3.branchPred.BTBHitPct 97.624175 # BTB Hit Percentage system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 162161 # number of cpu cycles simulated +system.cpu3.numCycles 161890 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 30846 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 291154 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 52678 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45209 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 126827 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2723 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 32992 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 268412 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49230 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 41709 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 124419 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2697 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 21882 # Number of cache lines fetched +system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24017 # Number of cache lines fetched system.cpu3.fetch.IcacheSquashes 451 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 160213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.817293 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.188011 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::samples 159937 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.678236 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.146445 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 57700 36.01% 36.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51927 32.41% 68.43% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6814 4.25% 72.68% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3535 2.21% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 932 0.58% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 33301 20.79% 96.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1242 0.78% 97.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 787 0.49% 97.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3975 2.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 63357 39.61% 39.61% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 49486 30.94% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7847 4.91% 75.46% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3455 2.16% 77.62% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 942 0.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 28830 18.03% 96.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1207 0.75% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 797 0.50% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 4016 2.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 160213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.324850 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.795463 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17433 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 58368 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 79576 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 3465 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1361 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 275763 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1361 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18155 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 26788 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 14101 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 81078 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 18720 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 272367 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 16743 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 159937 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.304095 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.657990 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17620 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 66098 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 70935 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3926 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1348 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 252986 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1348 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18323 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 31370 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 72885 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 22031 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 249675 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 20026 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 191251 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 520897 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 405695 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 177247 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14004 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1196 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 23402 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 76309 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 36069 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 36463 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 30962 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 226032 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6585 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 227862 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13164 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10986 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 709 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 160213 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.422244 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.377526 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 174506 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 471658 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 368736 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 160859 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 13647 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1202 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1275 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 26657 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 68456 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 31644 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33001 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 26549 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 205848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7559 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 208921 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12739 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10220 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 712 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 159937 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.306271 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.372225 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 61467 38.37% 38.37% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 22016 13.74% 52.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 35438 22.12% 74.23% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 35000 21.85% 96.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3395 2.12% 98.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1603 1.00% 99.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 883 0.55% 99.74% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 200 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 67005 41.89% 41.89% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24940 15.59% 57.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31075 19.43% 76.92% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 30637 19.16% 96.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3376 2.11% 98.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1620 1.01% 99.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 871 0.54% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 214 0.13% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 160213 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 159937 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 82 24.12% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 49 14.41% 38.53% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 61.47% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 82 24.70% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 41 12.35% 37.05% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 62.95% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 111773 49.05% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 80677 35.41% 84.46% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 35412 15.54% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 103999 49.78% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 73864 35.35% 85.13% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31058 14.87% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 227862 # Type of FU issued -system.cpu3.iq.rate 1.405159 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 340 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001492 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 616290 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 245818 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 226322 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 208921 # Type of FU issued +system.cpu3.iq.rate 1.290512 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 332 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001589 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 578115 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 226182 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 207437 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 228202 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 209253 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 30727 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26373 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2667 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1480 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1361 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 7576 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 269910 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 166 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 76309 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 36069 # Number of dispatched store instructions +system.cpu3.iew.iewSquashCycles 1348 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8395 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 247262 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 68456 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 31644 # Number of dispatched store instructions system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 226838 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 75201 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1024 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 438 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1065 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 207928 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 67431 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 993 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 37293 # number of nop insts executed -system.cpu3.iew.exec_refs 110524 # number of memory reference insts executed -system.cpu3.iew.exec_branches 46686 # Number of branches executed -system.cpu3.iew.exec_stores 35323 # Number of stores executed -system.cpu3.iew.exec_rate 1.398844 # Inst execution rate -system.cpu3.iew.wb_sent 226605 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 226322 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 128132 # num instructions producing a value -system.cpu3.iew.wb_consumers 134738 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.395662 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.950972 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 13998 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5876 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1284 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 157615 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.623367 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.050526 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 33855 # number of nop insts executed +system.cpu3.iew.exec_refs 98404 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43312 # Number of branches executed +system.cpu3.iew.exec_stores 30973 # Number of stores executed +system.cpu3.iew.exec_rate 1.284378 # Inst execution rate +system.cpu3.iew.wb_sent 207701 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 207437 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 116002 # num instructions producing a value +system.cpu3.iew.wb_consumers 122598 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.281345 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.946198 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 13505 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6847 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1271 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157409 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.484744 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.997930 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 67043 42.54% 42.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 43238 27.43% 69.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5262 3.34% 73.31% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6673 4.23% 77.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1534 0.97% 78.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 30788 19.53% 98.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 827 0.52% 98.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 952 0.60% 99.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1298 0.82% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 73609 46.76% 46.76% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 39844 25.31% 72.08% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5242 3.33% 75.41% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7652 4.86% 80.27% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1542 0.98% 81.25% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 26417 16.78% 98.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 849 0.54% 98.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 951 0.60% 99.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 157615 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 255867 # Number of instructions committed -system.cpu3.commit.committedOps 255867 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157409 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 233712 # Number of instructions committed +system.cpu3.commit.committedOps 233712 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 108145 # Number of memory references committed -system.cpu3.commit.loads 73642 # Number of loads committed -system.cpu3.commit.membars 5159 # Number of memory barriers committed -system.cpu3.commit.branches 45627 # Number of branches committed +system.cpu3.commit.refs 96099 # Number of memory references committed +system.cpu3.commit.loads 65935 # Number of loads committed +system.cpu3.commit.membars 6131 # Number of memory barriers committed +system.cpu3.commit.branches 42256 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 175889 # Number of committed integer instructions. +system.cpu3.commit.int_insts 160475 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 36414 14.23% 14.23% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 106149 41.49% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 78801 30.80% 86.52% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 34503 13.48% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33044 14.14% 14.14% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 98438 42.12% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 72066 30.84% 87.09% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30164 12.91% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 255867 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1298 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 425596 # The number of ROB reads -system.cpu3.rob.rob_writes 542328 # The number of ROB writes -system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1948 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.commit.op_class_0::total 233712 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 402737 # The number of ROB reads +system.cpu3.rob.rob_writes 496962 # The number of ROB writes +system.cpu3.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1953 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 46007 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 214294 # Number of Instructions Simulated -system.cpu3.committedOps 214294 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.756722 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.756722 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.321489 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.321489 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 391365 # number of integer regfile reads -system.cpu3.int_regfile_writes 183208 # number of integer regfile writes +system.cpu3.committedInsts 194537 # Number of Instructions Simulated +system.cpu3.committedOps 194537 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.832181 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.832181 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.201662 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.201662 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 355006 # number of integer regfile reads +system.cpu3.int_regfile_writes 166699 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 112150 # number of misc regfile reads +system.cpu3.misc_regfile_reads 100037 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.277315 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 40522 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.251319 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 36167 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1447.214286 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1291.678571 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.277315 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047417 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047417 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.251319 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047366 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047366 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 316074 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 316074 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 43937 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 43937 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 34273 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 34273 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 78210 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 78210 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 78210 # number of overall hits -system.cpu3.dcache.overall_hits::total 78210 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 514 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 514 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 159 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 159 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 673 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 673 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 673 # number of overall misses -system.cpu3.dcache.overall_misses::total 673 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9349000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 9349000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3790500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3790500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 680500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 680500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 13139500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 13139500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 13139500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 13139500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 44451 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 44451 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 34432 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 34432 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 78883 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 78883 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 78883 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 78883 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011563 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.011563 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004618 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004618 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008532 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008532 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008532 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008532 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 18188.715953 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 18188.715953 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23839.622642 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 23839.622642 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11938.596491 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 11938.596491 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 19523.774146 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 19523.774146 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 285043 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 285043 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40546 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40546 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 29945 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 29945 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 17 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 17 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 70491 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 70491 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 70491 # number of overall hits +system.cpu3.dcache.overall_hits::total 70491 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 489 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 489 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 638 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 638 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 638 # number of overall misses +system.cpu3.dcache.overall_misses::total 638 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8138500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8138500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3781500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3781500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 606500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 606500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11920000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11920000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11920000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11920000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41035 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41035 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 30094 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 30094 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 71129 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 71129 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 71129 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 71129 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011917 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.011917 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004951 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004951 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.757143 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.757143 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008970 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.008970 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008970 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.008970 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16643.149284 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16643.149284 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25379.194631 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 25379.194631 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11443.396226 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 11443.396226 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18683.385580 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18683.385580 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2224,106 +2224,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 347 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 399 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 399 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 399 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 399 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 167 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 274 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 274 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1719000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1719000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2129500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2129500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 623500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 623500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3848500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3848500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3848500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3848500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003757 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003757 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003108 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003108 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003473 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003473 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10293.413174 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10293.413174 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19901.869159 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19901.869159 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 328 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 374 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 374 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1609000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1609000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2139500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2139500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 553500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 553500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3748500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3748500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3748500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3748500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003923 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003923 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003423 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003423 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.757143 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.757143 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003712 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003712 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9993.788820 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9993.788820 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 20771.844660 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 20771.844660 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10443.396226 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10443.396226 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 384 # number of replacements -system.cpu3.icache.tags.tagsinuse 81.046367 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 21310 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 80.879647 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 23443 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 42.791165 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 47.074297 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 81.046367 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.158294 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.158294 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.879647 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157968 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.157968 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 22380 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 22380 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 21310 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 21310 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 21310 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 21310 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 21310 # number of overall hits -system.cpu3.icache.overall_hits::total 21310 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 572 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 572 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 572 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 572 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 572 # number of overall misses -system.cpu3.icache.overall_misses::total 572 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 8104500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 8104500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 8104500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 8104500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 8104500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 8104500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 21882 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 21882 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 21882 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 21882 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 21882 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 21882 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026140 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.026140 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026140 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.026140 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026140 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.026140 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14168.706294 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14168.706294 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14168.706294 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14168.706294 # average overall miss latency +system.cpu3.icache.tags.tag_accesses 24515 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 24515 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 23443 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23443 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23443 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23443 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 23443 # number of overall hits +system.cpu3.icache.overall_hits::total 23443 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 574 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 574 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 574 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 574 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 574 # number of overall misses +system.cpu3.icache.overall_misses::total 574 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7717500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7717500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7717500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7717500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7717500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7717500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 24017 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 24017 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 24017 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 24017 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 24017 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 24017 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023900 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023900 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023900 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023900 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023900 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023900 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13445.121951 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13445.121951 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13445.121951 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13445.121951 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2334,66 +2334,66 @@ system.cpu3.icache.fast_writes 0 # nu system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks::writebacks 384 # number of writebacks system.cpu3.icache.writebacks::total 384 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 74 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 74 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 74 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 76 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 76 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 76 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 76 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6912000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6912000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6912000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6912000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6912000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6912000 # 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average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6640500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6640500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6640500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6640500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6640500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6640500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020735 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020735 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.020735 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13334.337349 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13334.337349 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13334.337349 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2.350458 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.677584 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.742702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.718294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.788194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 288.006073 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.075910 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 61.760427 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.322052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2.559109 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.677187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1.231634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.717957 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000923 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000039 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000019 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006397 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 25618 # Number of tag accesses system.l2c.tags.data_accesses 25618 # Number of data accesses @@ -2404,9 +2404,9 @@ system.l2c.WritebackClean_hits::total 676 # nu system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 412 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 489 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 489 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits @@ -2415,26 +2415,26 @@ system.l2c.ReadSharedReq_hits::cpu3.data 11 # nu system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 410 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 489 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 493 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits system.l2c.demand_hits::total 1670 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 246 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 412 # number of overall hits +system.l2c.overall_hits::cpu1.inst 410 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 491 # number of overall hits +system.l2c.overall_hits::cpu2.inst 489 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 489 # number of overall hits +system.l2c.overall_hits::cpu3.inst 493 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits system.l2c.overall_hits::total 1670 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 27 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses @@ -2442,9 +2442,9 @@ system.l2c.ReadExReq_misses::cpu2.data 12 # nu system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 84 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 9 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 9 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 86 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 11 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 5 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses @@ -2453,63 +2453,63 @@ system.l2c.ReadSharedReq_misses::cpu3.data 1 # system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 84 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 11 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses system.l2c.demand_misses::total 679 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 362 # number of overall misses system.l2c.overall_misses::cpu0.data 169 # number of overall misses -system.l2c.overall_misses::cpu1.inst 84 # number of overall misses +system.l2c.overall_misses::cpu1.inst 86 # number of overall misses system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 9 # number of overall misses +system.l2c.overall_misses::cpu2.inst 11 # number of overall misses system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 9 # number of overall misses +system.l2c.overall_misses::cpu3.inst 5 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 679 # number of overall misses -system.l2c.ReadExReq_miss_latency::cpu0.data 7611000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7622500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 1059000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1210500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 1399000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11279500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27676500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6293000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 614000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 660000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 35243500 # number of ReadCleanReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1210000 # 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number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 1495500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 53223500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 27676500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 13592500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 6293000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu2.inst 788500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1292500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 341500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1501000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 53244500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 27679500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 13604000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6438500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 1599000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 614000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1293000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 660000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 1495500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 53223500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 788500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1292500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 341500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1501000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 53244500 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackClean_accesses::writebacks 676 # number of WritebackClean accesses(hits+misses) system.l2c.WritebackClean_accesses::total 676 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) @@ -2555,9 +2555,9 @@ system.l2c.ReadExReq_miss_rate::cpu2.data 1 # m system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.169355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.018072 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173387 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.022000 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses @@ -2566,55 +2566,55 @@ system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.169355 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173387 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.022000 # 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mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses @@ -2736,129 +2736,128 @@ system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21740.740741 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21850 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21904.571429 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21785.714286 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21814.561798 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70968.085106 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18981.481481 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18921.052632 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19119.047619 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18909.090909 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18983.146067 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71090.425532 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90875 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 106583.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76103.053435 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90833.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 107041.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76229.007634 # average ReadExReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73000 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66272.727273 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72750 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72750 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66276.053215 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 534 # Transaction distribution -system.membus.trans_dist::UpgradeReq 290 # Transaction distribution -system.membus.trans_dist::UpgradeResp 89 # Transaction distribution -system.membus.trans_dist::ReadExReq 162 # Transaction distribution +system.membus.trans_dist::UpgradeReq 291 # Transaction distribution +system.membus.trans_dist::ReadExReq 159 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1741 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1741 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1650 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 232 # Total snoops (count) -system.membus.snoop_fanout::samples 987 # Request fanout histogram +system.membus.snoops 230 # Total snoops (count) +system.membus.snoop_fanout::samples 985 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 985 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 987 # Request fanout histogram -system.membus.reqLayer0.occupancy 936504 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 985 # Request fanout histogram +system.membus.reqLayer0.occupancy 928501 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4933 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2364 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.respLayer1.occupancy 3534750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.3 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 4931 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1335 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2778 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2779 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 676 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1468 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 293 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 391 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 391 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 294 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 294 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 387 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 387 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 677 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1151 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 376 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6581 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 53760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadSharedReq 678 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1530 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1386 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59008 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 56256 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 56704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 193600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1022 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3463 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.289633 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.182691 # Request fanout histogram +system.toL2Bus.pkt_size::total 244288 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1020 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3461 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.293268 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.185819 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1230 35.52% 35.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 835 24.11% 59.63% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 563 16.26% 75.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 835 24.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1230 35.54% 35.54% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 830 23.98% 59.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 557 16.09% 75.61% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 844 24.39% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2867,24 +2866,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3463 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3953462 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3461 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3950967 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 911498 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 505495 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 746495 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 746494 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 439455 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 429965 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 752991 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 752493 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 419474 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 440466 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 434475 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 422962 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 903a3bff1..1d3cbd064 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140858 # Simulator instruction rate (inst/s) -host_op_rate 140857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18239325 # Simulator tick rate (ticks/s) -host_mem_usage 243264 # Number of bytes of host memory used -host_seconds 4.81 # Real time elapsed on the host +host_inst_rate 1830828 # Simulator instruction rate (inst/s) +host_op_rate 1830758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 237054275 # Simulator tick rate (ticks/s) +host_mem_usage 306784 # Number of bytes of host memory used +host_seconds 0.37 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -750,14 +750,14 @@ system.cpu3.icache.writebacks::writebacks 279 # n system.cpu3.icache.writebacks::total 279 # number of writebacks system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use +system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.076010 # Average number of references to valid blocks. +system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor @@ -766,18 +766,18 @@ system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Av system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 19424 # Number of tag accesses system.l2c.tags.data_accesses 19424 # Number of data accesses system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits @@ -944,24 +944,24 @@ system.l2c.no_allocate_misses 0 # Nu system.membus.trans_dist::ReadResp 423 # Transaction distribution system.membus.trans_dist::UpgradeReq 273 # Transaction distribution system.membus.trans_dist::UpgradeResp 80 # Transaction distribution -system.membus.trans_dist::ReadExReq 412 # Transaction distribution +system.membus.trans_dist::ReadExReq 183 # Transaction distribution system.membus.trans_dist::ReadExResp 136 # Transaction distribution system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1108 # Request fanout histogram +system.membus.snoop_fanout::samples 879 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1108 # Request fanout histogram +system.membus.snoop_fanout::total 879 # Request fanout histogram system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -970,7 +970,7 @@ system.toL2Bus.snoop_filter.hit_single_snoops 0 system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution @@ -978,24 +978,24 @@ system.toL2Bus.trans_dist::ReadExReq 412 # Tr system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 838 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 830 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 30400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 197568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 813d17b05..eb0bc0573 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000265 # Number of seconds simulated -sim_ticks 264840500 # Number of ticks simulated -final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000264 # Number of seconds simulated +sim_ticks 263565500 # Number of ticks simulated +final_tick 263565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127010 # Simulator instruction rate (inst/s) -host_op_rate 127009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50783237 # Simulator tick rate (ticks/s) -host_mem_usage 243272 # Number of bytes of host memory used -host_seconds 5.22 # Real time elapsed on the host -sim_insts 662366 # Number of instructions simulated -sim_ops 662366 # Number of ops (including micro ops) simulated +host_inst_rate 798172 # Simulator instruction rate (inst/s) +host_op_rate 798158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 317271660 # Simulator tick rate (ticks/s) +host_mem_usage 306776 # Number of bytes of host memory used +host_seconds 0.83 # Real time elapsed on the host +sim_insts 663039 # Number of instructions simulated +sim_ops 663039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 68871642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39873056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 1691584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3624823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 14015983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5558062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 966620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3624823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138226593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 68871642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 1691584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 14015983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 966620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85545829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 68871642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39873056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1691584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3624823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 14015983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5558062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 966620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3624823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138226593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69204809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40065942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 2428239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3642358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 13112490 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5342126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1214119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3885182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138895265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69204809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 2428239 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 13112490 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1214119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85959657 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69204809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40065942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 2428239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3642358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 13112490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5342126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1214119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3885182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138895265 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 529681 # number of cpu cycles simulated +system.cpu0.numCycles 527131 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158238 # Number of instructions committed -system.cpu0.committedOps 158238 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108984 # Number of integer alu accesses +system.cpu0.committedInsts 158196 # Number of instructions committed +system.cpu0.committedOps 158196 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108956 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25976 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108984 # number of integer instructions +system.cpu0.num_conditional_control_insts 25969 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108956 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315110 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110590 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315026 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110562 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73853 # number of memory refs -system.cpu0.num_load_insts 48895 # Number of load instructions -system.cpu0.num_store_insts 24958 # Number of store instructions +system.cpu0.num_mem_refs 73832 # number of memory refs +system.cpu0.num_load_insts 48881 # Number of load instructions +system.cpu0.num_store_insts 24951 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 529680.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 527130.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26841 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23568 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60795 38.40% 53.29% # Class of executed instruction +system.cpu0.Branches 26834 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23561 14.89% 14.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 60781 38.41% 53.29% # Class of executed instruction system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction @@ -114,36 +114,36 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 48979 30.94% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 24958 15.77% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 48965 30.94% 84.23% # Class of executed instruction +system.cpu0.op_class::MemWrite 24951 15.77% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158300 # Class of executed instruction +system.cpu0.op_class::total 158258 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.090849 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73323 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.050771 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73302 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 439.059880 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 438.934132 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.090849 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283381 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.283381 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.050771 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283302 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.283302 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 295643 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 295643 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24724 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24724 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 295559 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 295559 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48703 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48703 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24717 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24717 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73441 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73441 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73441 # number of overall hits -system.cpu0.dcache.overall_hits::total 73441 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73420 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73420 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73420 # number of overall hits +system.cpu0.dcache.overall_hits::total 73420 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -154,46 +154,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 351 # system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses system.cpu0.dcache.overall_misses::total 351 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5149000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7867000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7867000 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4817500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4817500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6985500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6985500 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 13016000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 13016000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 13016000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 13016000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48885 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48885 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24907 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24907 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 11803000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11803000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11803000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11803000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48871 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48871 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24900 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24900 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73792 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73792 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73792 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73792 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003437 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73771 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73771 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73771 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003438 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003438 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007349 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007349 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004757 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004757 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004757 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004757 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004758 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004758 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004758 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004758 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28675.595238 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28675.595238 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38172.131148 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38172.131148 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33626.780627 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33626.780627 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,88 +214,88 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4981000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4981000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6802500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6802500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12665000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12665000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12665000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12665000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003437 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003437 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11452000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11452000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11452000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11452000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003438 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003438 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007349 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004757 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004757 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004758 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004758 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27675.595238 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27675.595238 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37172.131148 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37172.131148 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 211.456411 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157834 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 211.380247 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157792 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 337.974304 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 337.884368 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.456411 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.413001 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.413001 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.380247 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412852 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.412852 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158768 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158768 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 157834 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157834 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157834 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157834 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157834 # number of overall hits -system.cpu0.icache.overall_hits::total 157834 # number of overall hits +system.cpu0.icache.tags.tag_accesses 158726 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 158726 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157792 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157792 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157792 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157792 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157792 # number of overall hits +system.cpu0.icache.overall_hits::total 157792 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20139500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20139500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20139500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20139500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20139500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20139500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158301 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158301 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158301 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158301 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 43125.267666 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 43125.267666 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20140500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20140500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20140500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20140500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20140500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20140500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158259 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158259 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158259 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158259 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158259 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158259 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002951 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002951 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002951 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002951 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002951 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43127.408994 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 43127.408994 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 43127.408994 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 43127.408994 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -312,158 +312,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19672500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19672500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19672500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19672500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19672500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19672500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19673500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19673500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19673500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19673500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002951 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002951 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002951 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42127.408994 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 529680 # number of cpu cycles simulated +system.cpu1.numCycles 527130 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 168829 # Number of instructions committed -system.cpu1.committedOps 168829 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111193 # Number of integer alu accesses +system.cpu1.committedInsts 170790 # Number of instructions committed +system.cpu1.committedOps 170790 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110708 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32827 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111193 # number of integer instructions +system.cpu1.num_conditional_control_insts 34050 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110708 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 275699 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104505 # number of times the integer registers were written +system.cpu1.num_int_register_reads 268858 # number of times the integer registers were read +system.cpu1.num_int_register_writes 101318 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54535 # number of memory refs -system.cpu1.num_load_insts 41264 # Number of load instructions -system.cpu1.num_store_insts 13271 # Number of store instructions -system.cpu1.num_idle_cycles 73879.862241 # Number of idle cycles -system.cpu1.num_busy_cycles 455800.137759 # Number of busy cycles -system.cpu1.not_idle_fraction 0.860520 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.139480 # Percentage of idle cycles -system.cpu1.Branches 34479 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25261 14.96% 14.96% # Class of executed instruction -system.cpu1.op_class::IntAlu 74858 44.33% 59.29% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::MemRead 55471 32.85% 92.14% # Class of executed instruction -system.cpu1.op_class::MemWrite 13271 7.86% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 52827 # number of memory refs +system.cpu1.num_load_insts 41019 # Number of load instructions +system.cpu1.num_store_insts 11808 # Number of store instructions +system.cpu1.num_idle_cycles 73818.861681 # Number of idle cycles +system.cpu1.num_busy_cycles 453311.138319 # Number of busy cycles +system.cpu1.not_idle_fraction 0.859961 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.140039 # Percentage of idle cycles +system.cpu1.Branches 35703 # Number of branches fetched +system.cpu1.op_class::No_OpClass 26483 15.50% 15.50% # Class of executed instruction +system.cpu1.op_class::IntAlu 74610 43.68% 59.18% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::MemRead 57921 33.91% 93.09% # Class of executed instruction +system.cpu1.op_class::MemWrite 11808 6.91% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 168861 # Class of executed instruction +system.cpu1.op_class::total 170822 # Class of executed instruction system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.495164 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 28944 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 964.800000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.474097 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 25884 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 892.551724 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.495164 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051748 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051748 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.474097 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051707 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051707 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 218364 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 218364 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41094 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41094 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13094 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13094 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 54188 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 54188 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 54188 # number of overall hits -system.cpu1.dcache.overall_hits::total 54188 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 107 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 107 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses -system.cpu1.dcache.overall_misses::total 270 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2920000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2920000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2149500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2149500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 245500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 245500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5069500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5069500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5069500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5069500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41257 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41257 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 13201 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 13201 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 54458 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 54458 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 54458 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 54458 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003951 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003951 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008105 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.808824 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.808824 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004958 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004958 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004958 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004958 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4463.636364 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4463.636364 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926 # average overall miss latency +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 211529 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 211529 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 40844 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40844 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 11631 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 11631 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 52475 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 52475 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 52475 # number of overall hits +system.cpu1.dcache.overall_hits::total 52475 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 167 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 272 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 272 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 272 # number of overall misses +system.cpu1.dcache.overall_misses::total 272 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1891500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1891500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1642500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1642500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3534000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3534000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3534000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3534000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41011 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41011 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 11736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 11736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 52747 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 52747 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 52747 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 52747 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004072 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004072 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008947 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008947 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005157 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005157 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005157 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005157 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11326.347305 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11326.347305 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15642.857143 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 15642.857143 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 12992.647059 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12992.647059 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,99 +472,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2757000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2757000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2042500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2042500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 190500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 190500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4799500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4799500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4799500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4799500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008105 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008105 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.808824 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.808824 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004958 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004958 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3463.636364 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3463.636364 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1537500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1537500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3262000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3262000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3262000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3262000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004072 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004072 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008947 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008947 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005157 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005157 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10326.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10326.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14642.857143 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14642.857143 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 67.000483 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 168496 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 66.953040 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 170457 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 460.371585 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 465.729508 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.000483 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130860 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.130860 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.953040 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130768 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.130768 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 169228 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 169228 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 168496 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 168496 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 168496 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 168496 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 168496 # number of overall hits -system.cpu1.icache.overall_hits::total 168496 # number of overall hits +system.cpu1.icache.tags.tag_accesses 171189 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 171189 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 170457 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 170457 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 170457 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 170457 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 170457 # number of overall hits +system.cpu1.icache.overall_hits::total 170457 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5681500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5681500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5681500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5681500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5681500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5681500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 168862 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 168862 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 168862 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 168862 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 168862 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 168862 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002167 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002167 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002167 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002167 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002167 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002167 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15523.224044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15523.224044 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5688500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5688500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5688500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5688500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5688500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5688500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 170823 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 170823 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 170823 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 170823 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 170823 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 170823 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002143 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002143 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002143 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002143 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002143 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002143 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15542.349727 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15542.349727 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15542.349727 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15542.349727 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,158 +581,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5315500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5315500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002167 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002167 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002167 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5322500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5322500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5322500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5322500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5322500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5322500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002143 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002143 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14542.349727 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 529681 # number of cpu cycles simulated +system.cpu2.numCycles 527130 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165415 # Number of instructions committed -system.cpu2.committedOps 165415 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110386 # Number of integer alu accesses +system.cpu2.committedInsts 168244 # Number of instructions committed +system.cpu2.committedOps 168244 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 109603 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31522 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110386 # number of integer instructions +system.cpu2.num_conditional_control_insts 33329 # number of instructions that are conditional controls +system.cpu2.num_int_insts 109603 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 277687 # number of times the integer registers were read -system.cpu2.num_int_register_writes 105904 # number of times the integer registers were written +system.cpu2.num_int_register_reads 267321 # number of times the integer registers were read +system.cpu2.num_int_register_writes 101101 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 55033 # number of memory refs -system.cpu2.num_load_insts 40858 # Number of load instructions -system.cpu2.num_store_insts 14175 # Number of store instructions -system.cpu2.num_idle_cycles 74150.001720 # Number of idle cycles -system.cpu2.num_busy_cycles 455530.998280 # Number of busy cycles -system.cpu2.not_idle_fraction 0.860010 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.139990 # Percentage of idle cycles -system.cpu2.Branches 33177 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23956 14.48% 14.48% # Class of executed instruction -system.cpu2.op_class::IntAlu 74457 45.00% 59.48% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::MemRead 52859 31.95% 91.43% # Class of executed instruction -system.cpu2.op_class::MemWrite 14175 8.57% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 52443 # number of memory refs +system.cpu2.num_load_insts 40463 # Number of load instructions +system.cpu2.num_store_insts 11980 # Number of store instructions +system.cpu2.num_idle_cycles 74087.861169 # Number of idle cycles +system.cpu2.num_busy_cycles 453042.138831 # Number of busy cycles +system.cpu2.not_idle_fraction 0.859450 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.140550 # Percentage of idle cycles +system.cpu2.Branches 34984 # Number of branches fetched +system.cpu2.op_class::No_OpClass 25761 15.31% 15.31% # Class of executed instruction +system.cpu2.op_class::IntAlu 74059 44.01% 59.32% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::MemRead 56476 33.56% 92.88% # Class of executed instruction +system.cpu2.op_class::MemWrite 11980 7.12% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 165447 # Class of executed instruction +system.cpu2.op_class::total 168276 # Class of executed instruction system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.486829 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30625 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1056.034483 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.444081 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 26343 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 878.100000 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.486829 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053685 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.053685 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.444081 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053602 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.053602 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 220352 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 220352 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 40687 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40687 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 13994 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 13994 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54681 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54681 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54681 # number of overall hits -system.cpu2.dcache.overall_hits::total 54681 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 163 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 209996 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 209996 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40285 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40285 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 11801 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 11801 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 52086 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 52086 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 52086 # number of overall hits +system.cpu2.dcache.overall_hits::total 52086 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 170 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 104 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 104 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses -system.cpu2.dcache.overall_misses::total 271 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3093500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3093500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2328000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2328000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 5421500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 5421500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 5421500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 5421500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40850 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40850 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14102 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14102 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 54952 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 54952 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 54952 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 54952 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003990 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003990 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007658 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007658 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004932 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004932 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004932 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004932 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4491.379310 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055 # average overall miss latency +system.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses +system.cpu2.dcache.overall_misses::total 274 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2220000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2220000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1703000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1703000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 260000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 3923000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 3923000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 3923000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 3923000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40455 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40455 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 11905 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 11905 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 52360 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 52360 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 52360 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 52360 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004202 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008736 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.008736 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005233 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005233 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005233 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005233 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13058.823529 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13058.823529 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 16375 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 16375 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.758621 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.758621 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14317.518248 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14317.518248 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,99 +741,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 163 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2930500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2930500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2220000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2220000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5150500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 5150500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5150500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 5150500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003990 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003990 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007658 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007658 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004932 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004932 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3491.379310 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency +system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2050000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2050000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1599000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1599000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3649000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3649000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3649000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3649000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004202 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004202 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008736 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008736 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.005233 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.005233 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12058.823529 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12058.823529 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15375 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15375 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.758621 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.758621 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 69.407713 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 165082 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 69.363893 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167911 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 451.043716 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 458.773224 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.407713 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135562 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.135562 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.363893 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135476 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.135476 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165814 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165814 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 165082 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165082 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165082 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165082 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165082 # number of overall hits -system.cpu2.icache.overall_hits::total 165082 # number of overall hits +system.cpu2.icache.tags.tag_accesses 168643 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 168643 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 167911 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 167911 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 167911 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 167911 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 167911 # number of overall hits +system.cpu2.icache.overall_hits::total 167911 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8101000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8101000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8101000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8101000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8101000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8101000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165448 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165448 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165448 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165448 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165448 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165448 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002212 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002212 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002212 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002212 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002212 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002212 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22133.879781 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22133.879781 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8088500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8088500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8088500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8088500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8088500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8088500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 168277 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 168277 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 168277 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 168277 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 168277 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 168277 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002175 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002175 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002175 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22099.726776 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 22099.726776 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 22099.726776 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 22099.726776 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,158 +850,158 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7735000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7735000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7735000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7735000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7735000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7735000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002212 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002212 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002212 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7722500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7722500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7722500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7722500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21099.726776 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 529680 # number of cpu cycles simulated +system.cpu3.numCycles 527131 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 169884 # Number of instructions committed -system.cpu3.committedOps 169884 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 110793 # Number of integer alu accesses +system.cpu3.committedInsts 165809 # Number of instructions committed +system.cpu3.committedOps 165809 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 112442 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33553 # number of instructions that are conditional controls -system.cpu3.num_int_insts 110793 # number of integer instructions +system.cpu3.num_conditional_control_insts 30690 # number of instructions that are conditional controls +system.cpu3.num_int_insts 112442 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 271193 # number of times the integer registers were read -system.cpu3.num_int_register_writes 102450 # number of times the integer registers were written +system.cpu3.num_int_register_reads 289238 # number of times the integer registers were read +system.cpu3.num_int_register_writes 110642 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 53409 # number of memory refs -system.cpu3.num_load_insts 41060 # Number of load instructions -system.cpu3.num_store_insts 12349 # Number of store instructions -system.cpu3.num_idle_cycles 74420.861217 # Number of idle cycles -system.cpu3.num_busy_cycles 455259.138783 # Number of busy cycles -system.cpu3.not_idle_fraction 0.859498 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.140502 # Percentage of idle cycles -system.cpu3.Branches 35208 # Number of branches fetched -system.cpu3.op_class::No_OpClass 25987 15.29% 15.29% # Class of executed instruction -system.cpu3.op_class::IntAlu 74660 43.94% 59.23% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::MemRead 56920 33.50% 92.73% # Class of executed instruction -system.cpu3.op_class::MemWrite 12349 7.27% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 57921 # number of memory refs +system.cpu3.num_load_insts 41890 # Number of load instructions +system.cpu3.num_store_insts 16031 # Number of store instructions +system.cpu3.num_idle_cycles 74358.001718 # Number of idle cycles +system.cpu3.num_busy_cycles 452772.998282 # Number of busy cycles +system.cpu3.not_idle_fraction 0.858938 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.141062 # Percentage of idle cycles +system.cpu3.Branches 32344 # Number of branches fetched +system.cpu3.op_class::No_OpClass 23127 13.95% 13.95% # Class of executed instruction +system.cpu3.op_class::IntAlu 75479 45.51% 59.46% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::MemRead 51204 30.88% 90.33% # Class of executed instruction +system.cpu3.op_class::MemWrite 16031 9.67% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 169916 # Class of executed instruction +system.cpu3.op_class::total 165841 # Class of executed instruction system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.679518 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 26969 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.704074 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 34341 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 929.965517 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1184.172414 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.679518 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050155 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050155 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.704074 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050203 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050203 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 213856 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 213856 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 40892 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 40892 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 12169 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 12169 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 53061 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 53061 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 53061 # number of overall hits -system.cpu3.dcache.overall_hits::total 53061 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 161 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 161 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2856500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2856500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2210000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2210000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 258500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 258500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5066500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5066500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5066500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5066500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41053 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41053 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 12276 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 12276 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 53329 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 53329 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 53329 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 53329 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003922 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003922 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008716 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008716 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005025 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005025 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005025 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005025 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4535.087719 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4535.087719 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 231895 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 231895 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41733 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41733 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 15853 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 15853 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 57586 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 57586 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 57586 # number of overall hits +system.cpu3.dcache.overall_hits::total 57586 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 150 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 150 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses +system.cpu3.dcache.overall_misses::total 259 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1542500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 1542500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1810500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1810500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 250500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 250500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 3353000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 3353000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 3353000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 3353000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41883 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41883 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 15962 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 15962 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 57845 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 57845 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 57845 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 57845 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003581 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003581 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006829 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.006829 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004477 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004477 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004477 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004477 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 10283.333333 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 10283.333333 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16610.091743 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16610.091743 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4473.214286 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4473.214286 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 12945.945946 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 12945.945946 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1010,69 +1010,69 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2695500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2695500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2103000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2103000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4798500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4798500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4798500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4798500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003922 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003922 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008716 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008716 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005025 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005025 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3535.087719 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3535.087719 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 150 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 259 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 259 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1392500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1392500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1701500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1701500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 194500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 194500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3094000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3094000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3094000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3094000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003581 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006829 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006829 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004477 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004477 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004477 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004477 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9283.333333 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9283.333333 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15610.091743 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15610.091743 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3473.214286 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3473.214286 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 64.991831 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 169550 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 64.942208 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 165475 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 461.989101 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 450.885559 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.991831 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126937 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.126937 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.942208 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126840 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.126840 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 170284 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 170284 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 169550 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 169550 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 169550 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 169550 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 169550 # number of overall hits -system.cpu3.icache.overall_hits::total 169550 # number of overall hits +system.cpu3.icache.tags.tag_accesses 166209 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 166209 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 165475 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 165475 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 165475 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 165475 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 165475 # number of overall hits +system.cpu3.icache.overall_hits::total 165475 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses @@ -1085,18 +1085,18 @@ system.cpu3.icache.demand_miss_latency::cpu3.inst 5473500 system.cpu3.icache.demand_miss_latency::total 5473500 # number of demand (read+write) miss cycles system.cpu3.icache.overall_miss_latency::cpu3.inst 5473500 # number of overall miss cycles system.cpu3.icache.overall_miss_latency::total 5473500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 169917 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 169917 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 169917 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 169917 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 169917 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 169917 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002160 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002160 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002160 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002160 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002160 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002160 # miss rate for overall accesses +system.cpu3.icache.ReadReq_accesses::cpu3.inst 165842 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 165842 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 165842 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 165842 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 165842 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 165842 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002213 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002213 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002213 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002213 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002213 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002213 # miss rate for overall accesses system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937 # average ReadReq miss latency system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937 # average ReadReq miss latency system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency @@ -1125,12 +1125,12 @@ system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5106500 system.cpu3.icache.demand_mshr_miss_latency::total 5106500 # number of demand (read+write) MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5106500 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::total 5106500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002160 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002160 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002160 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002213 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002213 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002213 # mshr miss rate for overall accesses system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency @@ -1139,30 +1139,30 @@ system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 347.318197 # Cycle average of tags in use +system.l2c.tags.tagsinuse 347.185045 # Cycle average of tags in use system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.882018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 230.794628 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.021394 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.166785 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.835671 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 46.779239 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.090035 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.944334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.804093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.881447 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 230.714883 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.006864 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.227742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.835119 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 46.668024 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.066881 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.961095 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.822991 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003522 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003520 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000714 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005300 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005298 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id @@ -1204,9 +1204,9 @@ system.l2c.overall_hits::cpu3.inst 357 # nu system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1218 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses @@ -1242,46 +1242,46 @@ system.l2c.overall_misses::cpu3.inst 10 # nu system.l2c.overall_misses::cpu3.data 16 # number of overall misses system.l2c.overall_misses::total 594 # number of overall misses system.l2c.ReadExReq_miss_latency::cpu0.data 5892000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 842000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 896000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 840000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8470000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 16964000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 821500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3820000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 553500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 22159000 # number of ReadCleanReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 837500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 905000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 836000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8470500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 16965000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 831500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3806500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 555500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 22158500 # number of ReadCleanReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.data 3927500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 118500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 476000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3.data 118000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 118000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 475500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 119000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 4640000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 16964000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 16965000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 9819500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 821500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 960500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 3820000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1372000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 553500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 958000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 831500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 955500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 3806500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1380500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 555500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 955000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 35269000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 16964000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 16965000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 9819500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 821500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 960500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 3820000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1372000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 553500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 958000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 831500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 955500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 3806500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1380500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 555500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 955000 # number of overall miss cycles system.l2c.overall_miss_latency::total 35269000 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 14 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) @@ -1355,37 +1355,37 @@ system.l2c.overall_miss_rate::cpu3.inst 0.027248 # mi system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses system.l2c.ReadExReq_avg_miss_latency::cpu0.data 59515.151515 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 60142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 59733.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 60000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 59647.887324 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59522.807018 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 58678.571429 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58769.230769 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 55350 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 59248.663102 # average ReadCleanReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 59821.428571 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 60333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 59714.285714 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 59651.408451 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59526.315789 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 59392.857143 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58561.538462 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 55550 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 59247.326203 # average ReadCleanReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 59507.575758 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 59250 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59500 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 59000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 59000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59437.500000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 59500 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::total 59487.179487 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 59522.807018 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 59526.315789 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 59512.121212 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 58678.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 60031.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 58769.230769 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 59652.173913 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 55350 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 59875 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 59392.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 59718.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 58561.538462 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 60021.739130 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 55550 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 59687.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::total 59375.420875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 59522.807018 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 59526.315789 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 59512.121212 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 58678.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 60031.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 58769.230769 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 59652.173913 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 55350 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 59875 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 59392.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 59718.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 58561.538462 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 60021.739130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 55550 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 59687.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::total 59375.420875 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1395,29 +1395,29 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 7 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 6 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 11 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2.data 1 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 11 # 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average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50050 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49500 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49539.548023 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 271 # Transaction distribution -system.membus.trans_dist::UpgradeResp 76 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1481 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1481 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 261 # Total snoops (count) @@ -1588,53 +1587,53 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 915 # Request fanout histogram -system.membus.reqLayer0.occupancy 677632 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 685132 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2936000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 3980 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1113 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 3976 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1120 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1854 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 428 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 428 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 424 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 424 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 852 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5309 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5866 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 147712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1032 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2922 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.269678 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.154527 # Request fanout histogram +system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1028 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2918 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.265250 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.153418 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1002 34.29% 34.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 787 26.93% 61.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 476 16.29% 77.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 657 22.48% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1002 34.34% 34.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 794 27.21% 61.55% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 468 16.04% 77.59% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 654 22.41% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -1643,24 +1642,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2922 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3050992 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2918 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3048992 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 495500 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 500989 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 432972 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 435970 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 554485 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 434474 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 441968 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 552992 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 427974 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 411482 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |