diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/quick/se/40.m5threads-test-atomic/ref | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 3695 |
1 files changed, 1859 insertions, 1836 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index db4434e5e..7012b3f19 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 111025500 # Number of ticks simulated -final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 110955500 # Number of ticks simulated +final_tick 110955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93081 # Simulator instruction rate (inst/s) -host_op_rate 93081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9906240 # Simulator tick rate (ticks/s) -host_mem_usage 253180 # Number of bytes of host memory used -host_seconds 11.21 # Real time elapsed on the host -sim_insts 1043212 # Number of instructions simulated -sim_ops 1043212 # Number of ops (including micro ops) simulated +host_inst_rate 120250 # Simulator instruction rate (inst/s) +host_op_rate 120250 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12800201 # Simulator tick rate (ticks/s) +host_mem_usage 288992 # Number of bytes of host memory used +host_seconds 8.67 # Real time elapsed on the host +sim_insts 1042358 # Number of instructions simulated +sim_ops 1042358 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 4608 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42176 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 4672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 4608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 73 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 72 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205214117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 96842617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 5764442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7493774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 42080423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11528883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3458665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7493774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 379876695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205214117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 5764442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 42080423 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3458665 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 256517647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205214117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 96842617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5764442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7493774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 42080423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11528883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3458665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7493774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 379876695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 205343584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 96903714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 5768078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7498502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 41530163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11536156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 4037655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7498502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380116353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205343584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 5768078 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 41530163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 4037655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 256679480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205343584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 96903714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5768078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7498502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 41530163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11536156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 4037655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7498502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380116353 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 660 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue @@ -70,7 +70,7 @@ system.physmem.bytesReadSys 42240 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 77 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 115 # Per bank write bursts system.physmem.perBankRdBursts::1 39 # Per bank write bursts system.physmem.perBankRdBursts::2 29 # Per bank write bursts @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 110997500 # Total gap between requests +system.physmem.totGap 110927500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -120,9 +120,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -184,148 +184,172 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 260.662252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.685653 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.368727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 56 37.09% 37.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 15 9.93% 47.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 26 17.22% 64.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 9 5.96% 70.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 10 6.62% 76.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 7 4.64% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 4 2.65% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 6 3.97% 88.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 3 1.99% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 3 1.99% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 1.32% 93.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 1.32% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 3 1.99% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 2 1.32% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation -system.physmem.totQLat 4008250 # Total ticks spent queuing -system.physmem.totMemAccLat 18157000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 285.483146 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.878201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 280.642368 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 31.46% 31.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 26 29.21% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 14.61% 75.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 5.62% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 5.62% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.37% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.25% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.12% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 6.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation +system.physmem.totQLat 3793500 # Total ticks spent queuing +system.physmem.totMemAccLat 17983500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers -system.physmem.totBankLat 10848750 # Total ticks spent accessing banks -system.physmem.avgQLat 6073.11 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst +system.physmem.totBankLat 10890000 # Total ticks spent accessing banks +system.physmem.avgQLat 5747.73 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16500.00 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27510.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27247.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.69 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.97 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.16 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 509 # Number of row buffer hits during reads +system.physmem.readRowHits 505 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 168178.03 # Average gap between requests -system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.34 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 379876695 # Throughput (bytes/s) +system.physmem.avgGap 168071.97 # Average gap between requests +system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 9.12 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 380116353 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 529 # Transaction distribution system.membus.trans_dist::ReadResp 528 # Transaction distribution -system.membus.trans_dist::UpgradeReq 289 # Transaction distribution -system.membus.trans_dist::UpgradeResp 76 # Transaction distribution -system.membus.trans_dist::ReadExReq 164 # Transaction distribution +system.membus.trans_dist::UpgradeReq 287 # Transaction distribution +system.membus.trans_dist::UpgradeResp 77 # Transaction distribution +system.membus.trans_dist::ReadExReq 163 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1717 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1717 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1715 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1715 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 932000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 925000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6290425 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 6291924 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 417.163639 # Cycle average of tags in use -system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 417.123879 # Cycle average of tags in use +system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 285.086488 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.417431 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.409300 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 3.063366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.732215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.799384 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 285.051208 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.412458 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 7.037952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.694517 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 55.368542 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.407900 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3.619836 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.732082 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000107 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000846 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000845 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000047 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000055 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 182 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.311909 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.311909 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67650 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71100 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 58235.349716 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57743.856333 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10875.950000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59063.829787 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59750 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67270.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60984.732824 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 69062.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61641.221374 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61416.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71100 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 68557.692308 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58517.424242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55954.481793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61416.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71100 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58239.583333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 68557.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58517.424242 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 1689557804 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2541 # Transaction distribution +system.toL2Bus.throughput 1688893295 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 292 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 292 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 392 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 392 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 591 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 587 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 858 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 348 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5418 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 356 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 135424 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 52160 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1628974 # Layer occupancy (ticks) +system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 135488 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 51904 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1624976 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 2704748 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1475514 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1464514 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1928994 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1928496 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1199245 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1926995 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1148249 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1927493 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1183748 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1209236 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1932245 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 1936745 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1115744 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 1133252 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 83087 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80860 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1219 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80377 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78332 # Number of BTB hits +system.cpu0.branchPred.lookups 83023 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80825 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 80352 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78307 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.455740 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.454948 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 222052 # number of cpu cycles simulated +system.cpu0.numCycles 221912 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17259 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161829 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3807 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13993 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17233 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 492726 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 83023 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78819 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161746 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3811 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13929 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 488 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 197038 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503030 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.216871 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 196870 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.502799 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215097 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35209 17.87% 17.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 452 0.23% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76210 38.68% 98.25% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 578 0.29% 98.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 364 0.18% 98.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35124 17.84% 17.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 80120 40.70% 58.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.49% 59.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 477 0.24% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76224 38.72% 98.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 570 0.29% 98.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2455 1.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 197038 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17851 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18507 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 561 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 487444 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 187 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 333388 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 972038 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 734246 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 320411 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 872 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 895 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3641 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155927 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78789 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 76026 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 405044 # Number of instructions issued +system.cpu0.fetch.rateDist::total 196870 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.374126 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.220367 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17821 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15547 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160777 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 280 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2445 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 489900 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2445 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18476 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 865 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14063 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160426 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 595 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 487057 # Number of instructions processed by rename +system.cpu0.rename.LSQFullEvents 216 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 333048 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 971305 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 733660 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 320079 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12969 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 866 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 886 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3628 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155827 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78749 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 76001 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75817 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 407304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 910 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 404579 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9396 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 197038 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055664 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097184 # Number of insts issued each cycle +system.cpu0.iq.iqSquashedInstsExamined 10771 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9747 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 351 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 196870 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055057 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097769 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34076 17.29% 17.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77371 39.27% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1552 0.79% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34107 17.32% 17.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4943 2.51% 19.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77928 39.58% 59.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77295 39.26% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1579 0.80% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 650 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 197038 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 196870 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 27.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 42 19.91% 46.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 53.08% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 171308 42.29% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155505 38.39% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 171055 42.28% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155363 38.40% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 78161 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 405044 # Type of FU issued -system.cpu0.iq.rate 1.824095 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1007470 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 403231 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 404579 # Type of FU issued +system.cpu0.iq.rate 1.823151 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000549 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1006383 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 419039 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 402754 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 405255 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 404801 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75529 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2132 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1428 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2440 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 371 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 485139 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155927 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78789 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2445 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 405 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 484766 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 308 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 155827 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78749 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 328 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1114 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1066 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 403510 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 155033 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76577 # number of nop insts executed -system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed -system.cpu0.iew.exec_branches 80250 # Number of branches executed -system.cpu0.iew.exec_stores 78134 # Number of stores executed -system.cpu0.iew.exec_rate 1.819295 # Inst execution rate -system.cpu0.iew.wb_sent 403557 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 403231 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238890 # num instructions producing a value -system.cpu0.iew.wb_consumers 241357 # num instructions consuming a value +system.cpu0.iew.exec_nop 76552 # number of nop insts executed +system.cpu0.iew.exec_refs 233092 # number of memory reference insts executed +system.cpu0.iew.exec_branches 80162 # Number of branches executed +system.cpu0.iew.exec_stores 78059 # Number of stores executed +system.cpu0.iew.exec_rate 1.818333 # Inst execution rate +system.cpu0.iew.wb_sent 403084 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 402754 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238663 # num instructions producing a value +system.cpu0.iew.wb_consumers 241120 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.815931 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.814927 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989810 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12269 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 194598 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430487 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136021 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 194425 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430089 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136483 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34535 17.75% 17.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34537 17.76% 17.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79950 41.12% 58.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2378 1.22% 60.11% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75417 38.76% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75328 38.74% 99.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 457 0.24% 99.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 194598 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 472968 # Number of instructions committed -system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 194425 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 472470 # Number of instructions committed +system.cpu0.commit.committedOps 472470 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 231199 # Number of memory references committed -system.cpu0.commit.loads 153795 # Number of loads committed +system.cpu0.commit.refs 230950 # Number of memory references committed +system.cpu0.commit.loads 153629 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79291 # Number of branches committed +system.cpu0.commit.branches 79208 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 318742 # Number of committed integer instructions. +system.cpu0.commit.int_insts 318410 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 678235 # The number of ROB reads -system.cpu0.rob.rob_writes 972657 # The number of ROB writes -system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25014 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 396861 # Number of Instructions Simulated -system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated -system.cpu0.cpi 0.559521 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559521 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 722661 # number of integer regfile reads -system.cpu0.int_regfile_writes 325753 # number of integer regfile writes +system.cpu0.rob.rob_reads 677696 # The number of ROB reads +system.cpu0.rob.rob_writes 971940 # The number of ROB writes +system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25042 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 396446 # Number of Instructions Simulated +system.cpu0.committedOps 396446 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 396446 # Number of Instructions Simulated +system.cpu0.cpi 0.559753 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559753 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.786501 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.786501 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 721878 # number of integer regfile reads +system.cpu0.int_regfile_writes 325337 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads +system.cpu0.misc_regfile_reads 234915 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.312438 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 241.280038 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.312438 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471313 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471313 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.280038 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471250 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471250 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 6456 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 6456 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5113 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5113 # number of overall hits -system.cpu0.icache.overall_hits::total 5113 # number of overall hits +system.cpu0.icache.tags.tag_accesses 6422 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 6422 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits +system.cpu0.icache.overall_hits::total 5079 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses system.cpu0.icache.overall_misses::total 756 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35939745 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 35939745 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 35939745 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 35939745 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 35939745 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 35939745 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5869 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5869 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5869 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.128812 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.128812 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47539.345238 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 47539.345238 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 47539.345238 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 47539.345238 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35676245 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35676245 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35676245 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35676245 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35676245 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35676245 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47190.800265 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47190.800265 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47190.800265 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47190.800265 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47190.800265 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47190.800265 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1043,254 +1066,254 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686752 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686752 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686752 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27686752 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686752 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27686752 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47086.312925 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27430752 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27430752 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27430752 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27430752 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27430752 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27430752 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46650.938776 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 46650.938776 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46650.938776 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 46650.938776 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.026071 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.009454 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155675 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 915.735294 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026071 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277395 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277395 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.009454 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277362 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277362 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 51 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 627950 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 627950 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76817 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 627368 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 627368 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79025 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79025 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76734 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76734 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155902 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155902 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155902 # number of overall hits -system.cpu0.dcache.overall_hits::total 155902 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 420 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 420 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 155759 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155759 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155759 # number of overall hits +system.cpu0.dcache.overall_hits::total 155759 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 418 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 418 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 965 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 965 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 965 # number of overall misses -system.cpu0.dcache.overall_misses::total 965 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13542707 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13542707 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32279504 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32279504 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 963 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 963 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 963 # number of overall misses +system.cpu0.dcache.overall_misses::total 963 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13454697 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13454697 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32621759 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32621759 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 45822211 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 45822211 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 45822211 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 45822211 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79505 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79505 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 46076456 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 46076456 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 46076456 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 46076456 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 79443 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 79443 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77279 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77279 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156867 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156867 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156867 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156867 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005283 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005283 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007045 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007045 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 156722 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156722 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156722 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156722 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005262 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005262 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007052 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007052 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006152 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006152 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006152 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006152 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32244.540476 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32244.540476 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59228.447706 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 59228.447706 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006145 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006145 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006145 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006145 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32188.270335 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32188.270335 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59856.438532 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 59856.438532 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 47484.156477 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 47484.156477 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47846.787124 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47846.787124 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47846.787124 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47846.787124 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 524 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.200000 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 227 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 230 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 230 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu0.data 600 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 600 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu0.data 600 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 600 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 365 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 365 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6251507 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6251507 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7188729 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7188729 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 363 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 363 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 363 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 363 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6237508 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6237508 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7264228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7264228 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13440236 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13440236 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13440236 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13440236 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002428 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002428 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002223 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002223 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13501736 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13501736 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13501736 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13501736 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002366 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002366 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002327 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002327 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32391.227979 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32391.227979 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41794.936047 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41794.936047 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002316 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002316 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002316 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002316 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33178.234043 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33178.234043 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41509.874286 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41509.874286 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37194.865014 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37194.865014 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37194.865014 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37194.865014 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 47485 # Number of BP lookups -system.cpu1.branchPred.condPredicted 44754 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1270 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 41396 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 40599 # Number of BTB hits +system.cpu1.branchPred.lookups 49230 # Number of BP lookups +system.cpu1.branchPred.condPredicted 46482 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1275 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 43125 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 42318 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.074693 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.128696 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 644 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 177933 # number of cpu cycles simulated +system.cpu1.numCycles 177729 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 31734 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 260080 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 47485 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 41253 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 95164 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3727 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 37889 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 30707 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 271510 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 49230 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 42962 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 98061 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3712 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 35852 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.NoActiveThreadStallCycles 7757 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 23379 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 175722 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.480065 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.059330 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 22354 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 175517 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.546916 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.089154 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 80558 45.84% 45.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 49339 28.08% 73.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7969 4.54% 78.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3191 1.82% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 687 0.39% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 28723 16.35% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1207 0.69% 97.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 759 0.43% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3289 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 77456 44.13% 44.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 50516 28.78% 72.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7423 4.23% 77.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3189 1.82% 78.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 704 0.40% 79.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 30974 17.65% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1193 0.68% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 759 0.43% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3303 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 175722 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.266870 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.461674 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 38713 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 32553 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 87468 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 6833 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2380 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 256418 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2380 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 39395 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 20083 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11723 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 80903 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 13463 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 254199 # Number of instructions processed by rename +system.cpu1.fetch.rateDist::total 175517 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.276995 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.527663 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 37188 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 31008 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 90874 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6330 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2360 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 267842 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2360 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 37871 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18552 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11702 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 84813 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12462 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 265527 # Number of instructions processed by rename system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 175957 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 477753 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 373133 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 162997 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12960 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1085 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 16072 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 69810 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 31966 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 34021 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 211912 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10947 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.205950 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.291467 # Number of insts issued each cycle +system.cpu1.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 184379 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 502490 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 391665 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 171551 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12828 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 15186 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 73774 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 34232 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 35732 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 29187 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 218298 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7639 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 221677 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10737 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10712 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 175517 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.262994 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.299330 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 32813 18.67% 97.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3279 1.87% 99.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74868 42.66% 42.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26303 14.99% 57.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 34475 19.64% 77.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 35103 20.00% 97.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3248 1.85% 99.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1161 0.66% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 252 0.14% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 175722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 175517 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available @@ -1326,193 +1349,193 @@ system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # at system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 104746 49.43% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 75888 35.81% 85.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 108767 49.07% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.07% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 79372 35.81% 84.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 33538 15.13% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 211912 # Type of FU issued -system.cpu1.iq.rate 1.190965 # Inst issue rate +system.cpu1.iq.FU_type_0::total 221677 # Type of FU issued +system.cpu1.iq.rate 1.247275 # Inst issue rate system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 599896 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 210068 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fu_busy_rate 0.001200 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 619236 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 236717 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 219849 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 212178 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 221943 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 28929 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2449 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1444 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2380 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 699 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 251202 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 69810 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 31966 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1044 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2360 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 686 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 262595 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 73774 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 34232 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1056 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1183 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 918 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 220501 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 72766 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 34927 # number of nop insts executed -system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed -system.cpu1.iew.exec_branches 44131 # Number of branches executed -system.cpu1.iew.exec_stores 31196 # Number of stores executed -system.cpu1.iew.exec_rate 1.184317 # Inst execution rate -system.cpu1.iew.wb_sent 210356 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 210068 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 116711 # num instructions producing a value -system.cpu1.iew.wb_consumers 121376 # num instructions consuming a value +system.cpu1.iew.exec_nop 36658 # number of nop insts executed +system.cpu1.iew.exec_refs 106223 # number of memory reference insts executed +system.cpu1.iew.exec_branches 45902 # Number of branches executed +system.cpu1.iew.exec_stores 33457 # Number of stores executed +system.cpu1.iew.exec_rate 1.240659 # Inst execution rate +system.cpu1.iew.wb_sent 220134 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 219849 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 122957 # num instructions producing a value +system.cpu1.iew.wb_consumers 127616 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.180602 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.961566 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.236990 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.963492 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1270 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 165567 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.441743 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.939965 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12326 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7048 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1275 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 165400 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.513005 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.970213 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 77636 46.89% 46.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 42274 25.53% 72.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6096 3.68% 76.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 8474 5.12% 81.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1557 0.94% 82.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 27207 16.43% 98.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1010 0.61% 99.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 803 0.49% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 73929 44.70% 44.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 44053 26.63% 71.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 7962 4.81% 79.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 29500 17.84% 98.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 477 0.29% 98.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1008 0.61% 99.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 804 0.49% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 165567 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 238705 # Number of instructions committed -system.cpu1.commit.committedOps 238705 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 165400 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 250251 # Number of instructions committed +system.cpu1.commit.committedOps 250251 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 97880 # Number of memory references committed -system.cpu1.commit.loads 67361 # Number of loads committed -system.cpu1.commit.membars 6845 # Number of memory barriers committed -system.cpu1.commit.branches 43327 # Number of branches committed +system.cpu1.commit.refs 104168 # Number of memory references committed +system.cpu1.commit.loads 71380 # Number of loads committed +system.cpu1.commit.membars 6331 # Number of memory barriers committed +system.cpu1.commit.branches 45080 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 163326 # Number of committed integer instructions. +system.cpu1.commit.int_insts 171367 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 803 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 804 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 415361 # The number of ROB reads -system.cpu1.rob.rob_writes 504754 # The number of ROB writes -system.cpu1.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2211 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 44117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 197745 # Number of Instructions Simulated -system.cpu1.committedOps 197745 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 197745 # Number of Instructions Simulated -system.cpu1.cpi 0.899810 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.899810 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 358439 # number of integer regfile reads -system.cpu1.int_regfile_writes 167768 # number of integer regfile writes +system.cpu1.rob.rob_reads 426586 # The number of ROB reads +system.cpu1.rob.rob_writes 527520 # The number of ROB writes +system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2212 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 44181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 208053 # Number of Instructions Simulated +system.cpu1.committedOps 208053 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 208053 # Number of Instructions Simulated +system.cpu1.cpi 0.854249 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.854249 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.170619 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.170619 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 377223 # number of integer regfile reads +system.cpu1.int_regfile_writes 176309 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads +system.cpu1.misc_regfile_reads 107781 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.730517 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 76.722565 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 21879 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 51.119159 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730517 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.722565 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149849 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149849 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 23807 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 23807 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 22903 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 22903 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 22903 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 22903 # number of overall hits -system.cpu1.icache.overall_hits::total 22903 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses -system.cpu1.icache.overall_misses::total 476 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7186493 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7186493 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7186493 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7186493 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7186493 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7186493 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 23379 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 23379 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 23379 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.020360 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.020360 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15097.674370 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15097.674370 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15097.674370 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15097.674370 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 22782 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 22782 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 21879 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 21879 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 21879 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 21879 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 21879 # number of overall hits +system.cpu1.icache.overall_hits::total 21879 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 475 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 475 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 475 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 475 # number of overall misses +system.cpu1.icache.overall_misses::total 475 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7157495 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7157495 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7157495 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7157495 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7157495 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7157495 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 22354 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 22354 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 22354 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 22354 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 22354 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 22354 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021249 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.021249 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021249 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.021249 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021249 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.021249 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15068.410526 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15068.410526 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15068.410526 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15068.410526 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15068.410526 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15068.410526 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1521,112 +1544,111 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 47 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 47 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 47 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726506 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726506 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726506 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5726506 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726506 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5726506 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13379.686916 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5706004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5706004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5706004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5706004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5706004 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5706004 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019146 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019146 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019146 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019146 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13331.785047 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13331.785047 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13331.785047 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13331.785047 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 36646 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1263.655172 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 23.630187 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 38790 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1385.357143 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.664777 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046220 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.046220 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.630187 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046153 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.046153 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 290684 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 290684 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41736 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41736 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 30310 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 30310 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 72046 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 72046 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 72046 # number of overall hits -system.cpu1.dcache.overall_hits::total 72046 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 352 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 352 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 306681 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 306681 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 43485 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 43485 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 32585 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 32585 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 76070 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 76070 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 76070 # number of overall hits +system.cpu1.dcache.overall_hits::total 76070 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 336 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 336 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 491 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 491 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 491 # number of overall misses -system.cpu1.dcache.overall_misses::total 491 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4404095 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4404095 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2802760 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2802760 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 563508 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 563508 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7206855 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7206855 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7206855 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7206855 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 42088 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 42088 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 30449 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 30449 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 72537 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 72537 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 72537 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 72537 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008363 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008363 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004565 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004565 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006769 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006769 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006769 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006769 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12511.633523 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12511.633523 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20163.741007 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20163.741007 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9886.105263 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9886.105263 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14677.912424 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14677.912424 # average overall miss latency +system.cpu1.dcache.demand_misses::cpu1.data 468 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 468 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 468 # number of overall misses +system.cpu1.dcache.overall_misses::total 468 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4179135 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4179135 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2763761 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2763761 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 521507 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 521507 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6942896 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6942896 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6942896 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6942896 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 43821 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 43821 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 32717 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 32717 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 76538 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 76538 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 76538 # 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average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12437.901786 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9149.245614 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9149.245614 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14835.247863 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14835.247863 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14835.247863 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14835.247863 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1635,370 +1657,370 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 187 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 187 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 219 # 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number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1329240 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1329240 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 449492 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 449492 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2459763 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2459763 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2459763 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2459763 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003920 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003920 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003514 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003514 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003750 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003750 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6851.654545 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6851.654545 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12422.803738 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7885.824561 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7885.824561 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1078019 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1078019 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1313739 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1313739 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 407493 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 407493 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2391758 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2391758 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2391758 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2391758 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003606 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003606 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003118 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003118 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003397 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003397 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6822.905063 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6822.905063 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7149 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7149 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9199.069231 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9199.069231 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9199.069231 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9199.069231 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51289 # Number of BP lookups -system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 45091 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits +system.cpu2.branchPred.lookups 47736 # Number of BP lookups +system.cpu2.branchPred.condPredicted 45029 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1300 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 41576 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 40869 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.467543 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.299500 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 682 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 177568 # number of cpu cycles simulated +system.cpu2.numCycles 177364 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28811 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 286582 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51289 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 100994 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 31174 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 30843 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 263253 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 47736 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 41551 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 94921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3824 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 35042 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 19751 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.666126 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.139968 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 7755 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 807 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 21784 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 171818 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.532162 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.088026 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 71011 41.28% 41.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51378 29.87% 71.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3271 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 76897 44.75% 44.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 48842 28.43% 73.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7151 4.16% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3183 1.85% 79.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 686 0.40% 79.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 29853 17.37% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1160 0.68% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 777 0.45% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3269 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288841 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.613928 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 27886 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 95100 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 283075 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12252 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90315 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 280839 # Number of instructions processed by rename -system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 538430 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 418650 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1241 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12535 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 79329 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 37643 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 37867 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234900 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10850 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.365658 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.313804 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 171818 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.269141 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.484253 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 36742 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 30807 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 88098 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5970 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2446 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 259780 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2446 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 37466 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 17719 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12322 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 82368 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 11742 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 257506 # Number of instructions processed by rename +system.cpu2.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 179566 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 487666 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 380584 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 166435 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13131 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1114 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1238 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 14439 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 71199 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33061 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 34327 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 28016 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 212074 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7370 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 214906 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11214 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11199 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 171818 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.250777 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.303706 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38470 22.37% 97.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3247 1.89% 99.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 74494 43.36% 43.36% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 25338 14.75% 58.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33284 19.37% 77.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 33913 19.74% 97.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3241 1.89% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1161 0.68% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 274 0.16% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 172005 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 171818 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 17 6.01% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 56 19.79% 25.80% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 74.20% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17 6.18% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 48 17.45% 23.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 76.36% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 114350 48.68% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83592 35.59% 84.27% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 106166 49.40% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 76377 35.54% 84.94% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 32363 15.06% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234900 # Type of FU issued -system.cpu2.iq.rate 1.322873 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 642189 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 233099 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 214906 # Type of FU issued +system.cpu2.iq.rate 1.211666 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 275 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001280 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 602011 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 230706 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 213087 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 235183 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 215181 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 27728 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2477 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2543 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 48 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2417 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 878 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 278010 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 351 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 79329 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 37643 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1071 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 917 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 254656 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 71199 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33061 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1074 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 457 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 973 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1135 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 48 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 458 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 967 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1425 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 213756 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 70098 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1150 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 38771 # number of nop insts executed -system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed -system.cpu2.iew.exec_branches 48001 # Number of branches executed -system.cpu2.iew.exec_stores 36873 # Number of stores executed -system.cpu2.iew.exec_rate 1.316482 # Inst execution rate -system.cpu2.iew.wb_sent 233385 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 233099 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 131933 # num instructions producing a value -system.cpu2.iew.wb_consumers 136641 # num instructions consuming a value +system.cpu2.iew.exec_nop 35212 # number of nop insts executed +system.cpu2.iew.exec_refs 102378 # number of memory reference insts executed +system.cpu2.iew.exec_branches 44395 # Number of branches executed +system.cpu2.iew.exec_stores 32280 # Number of stores executed +system.cpu2.iew.exec_rate 1.205183 # Inst execution rate +system.cpu2.iew.wb_sent 213374 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 213087 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 119148 # num instructions producing a value +system.cpu2.iew.wb_consumers 123853 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.312731 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.965545 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.201411 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.962011 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1303 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 161811 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.639889 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.021157 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12898 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6722 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1300 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 161617 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.495857 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.966536 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 66196 40.91% 40.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46128 28.51% 69.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6098 3.77% 73.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6657 4.11% 77.30% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1558 0.96% 78.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 32865 20.31% 98.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 486 0.30% 98.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1000 0.62% 99.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 73208 45.30% 45.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 42532 26.32% 71.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6095 3.77% 75.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1558 0.96% 81.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28303 17.51% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 470 0.29% 98.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 161811 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 265352 # Number of instructions committed -system.cpu2.commit.committedOps 265352 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 161617 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 241756 # Number of instructions committed +system.cpu2.commit.committedOps 241756 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 113027 # Number of memory references committed -system.cpu2.commit.loads 76852 # Number of loads committed -system.cpu2.commit.membars 5022 # Number of memory barriers committed -system.cpu2.commit.branches 47160 # Number of branches committed +system.cpu2.commit.refs 100248 # Number of memory references committed +system.cpu2.commit.loads 68656 # Number of loads committed +system.cpu2.commit.membars 6003 # Number of memory barriers committed +system.cpu2.commit.branches 43556 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 182307 # Number of committed integer instructions. +system.cpu2.commit.int_insts 165922 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 823 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 438409 # The number of ROB reads -system.cpu2.rob.rob_writes 558438 # The number of ROB writes -system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5563 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44482 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 222382 # Number of Instructions Simulated -system.cpu2.committedOps 222382 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 222382 # Number of Instructions Simulated -system.cpu2.cpi 0.798482 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.798482 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 404230 # number of integer regfile reads -system.cpu2.int_regfile_writes 188772 # number of integer regfile writes +system.cpu2.rob.rob_reads 414862 # The number of ROB reads +system.cpu2.rob.rob_writes 511759 # The number of ROB writes +system.cpu2.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5546 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 201412 # Number of Instructions Simulated +system.cpu2.committedOps 201412 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 201412 # Number of Instructions Simulated +system.cpu2.cpi 0.880603 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.880603 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.135586 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.135586 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 365854 # number of integer regfile reads +system.cpu2.int_regfile_writes 171387 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads +system.cpu2.misc_regfile_reads 103940 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.236554 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19258 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 82.194037 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 21297 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.312941 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 50.110588 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236554 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.194037 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160535 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160535 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.210938 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 20176 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 20176 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 19258 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19258 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19258 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19258 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19258 # number of overall hits -system.cpu2.icache.overall_hits::total 19258 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses -system.cpu2.icache.overall_misses::total 493 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11621241 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11621241 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11621241 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11621241 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11621241 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11621241 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19751 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19751 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19751 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19751 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19751 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19751 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024961 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024961 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024961 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23572.496957 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23572.496957 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23572.496957 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23572.496957 # average overall miss latency +system.cpu2.icache.tags.tag_accesses 22209 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 22209 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 21297 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 21297 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 21297 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 21297 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 21297 # number of overall hits +system.cpu2.icache.overall_hits::total 21297 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 487 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 487 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 487 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 487 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 487 # number of overall misses +system.cpu2.icache.overall_misses::total 487 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11553239 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11553239 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11553239 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11553239 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11553239 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11553239 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 21784 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 21784 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 21784 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 21784 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 21784 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 21784 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.022356 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.022356 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.022356 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.022356 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.022356 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.022356 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23723.283368 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23723.283368 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23723.283368 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23723.283368 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23723.283368 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23723.283368 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -2007,111 +2029,112 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 62 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 62 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 62 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9301005 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 9301005 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9301005 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 9301005 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9301005 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 9301005 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021518 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021518 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021518 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21884.717647 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9258007 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 9258007 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9258007 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 9258007 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9258007 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 9258007 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019510 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.019510 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.019510 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21783.545882 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21783.545882 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21783.545882 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21783.545882 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.142591 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1507.392857 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 26.156826 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 37738 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1301.310345 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142591 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.156826 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051088 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.051088 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 328789 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 328789 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 45613 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 35966 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 35966 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 81579 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 81579 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 81579 # number of overall hits -system.cpu2.dcache.overall_hits::total 81579 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 346 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 346 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 485 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 485 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 485 # number of overall misses -system.cpu2.dcache.overall_misses::total 485 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5532140 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5532140 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3131011 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3131011 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 555006 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 555006 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8663151 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8663151 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8663151 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8663151 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 45959 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 45959 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 36105 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 36105 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 70 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 82064 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 82064 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 82064 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 82064 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007528 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.007528 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003850 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.814286 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005910 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005910 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005910 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005910 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15988.843931 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 15988.843931 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9736.947368 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9736.947368 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17862.167010 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17862.167010 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 296038 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 296038 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 31379 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 31379 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 73390 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 73390 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 73390 # number of overall hits +system.cpu2.dcache.overall_hits::total 73390 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 342 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 342 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 140 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 140 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 482 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 482 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 482 # number of overall misses +system.cpu2.dcache.overall_misses::total 482 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5441573 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5441573 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3139010 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3139010 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 574505 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 574505 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8580583 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8580583 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8580583 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8580583 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42353 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42353 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 31519 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 31519 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 73872 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 73872 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 73872 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 73872 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008075 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.008075 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004442 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004442 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.808219 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.808219 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006525 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006525 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15911.032164 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 15911.032164 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22421.500000 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22421.500000 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9737.372881 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9737.372881 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17802.039419 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17802.039419 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17802.039419 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17802.039419 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2120,371 +2143,371 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 184 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 217 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 217 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 177 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 177 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 211 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 211 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 211 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 211 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 165 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1488769 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1488769 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1526989 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1526989 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 440994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 440994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3015758 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3015758 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3015758 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3015758 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003525 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003525 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002936 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002936 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.814286 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003266 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003266 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9189.932099 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9189.932099 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14405.556604 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14405.556604 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7736.736842 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7736.736842 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1516779 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1516779 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1527990 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1527990 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456495 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456495 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3044769 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3044769 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3044769 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3044769 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003896 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003896 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003363 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003363 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.808219 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.808219 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003669 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003669 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.600000 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.600000 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14415 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14415 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7737.203390 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7737.203390 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11235.309963 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11235.309963 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11235.309963 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11235.309963 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 52302 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49590 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1266 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 46219 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 45467 # Number of BTB hits +system.cpu3.branchPred.lookups 53969 # Number of BP lookups +system.cpu3.branchPred.condPredicted 51237 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1265 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 47879 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 47122 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.372963 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.418931 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 177222 # number of cpu cycles simulated +system.cpu3.numCycles 177018 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 28851 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 32601 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 27849 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 302683 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 53969 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 47767 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 106238 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3643 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 30687 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.NoActiveThreadStallCycles 7755 # Number of stall cycles due to no active thread to fetch from system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 20565 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 250 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 175820 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.658463 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.129406 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.CacheLines 19589 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 175633 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.723383 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.153093 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 72377 41.17% 41.17% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 52818 30.04% 71.21% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6573 3.74% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3193 1.82% 76.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 659 0.37% 77.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 35007 19.91% 97.05% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1204 0.68% 97.73% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 759 0.43% 98.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3230 1.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 69395 39.51% 39.51% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 53961 30.72% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6037 3.44% 73.67% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3206 1.83% 75.50% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 696 0.40% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 37090 21.12% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1217 0.69% 97.70% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 754 0.43% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3277 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 34477 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 28631 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 35172 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11804 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename +system.cpu3.fetch.rateDist::total 175633 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.304879 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.709900 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 32991 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 27180 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 100358 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5049 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2300 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 299127 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2300 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 33666 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 14636 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11796 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 95593 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 9887 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 297010 # Number of instructions processed by rename system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 199357 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 546724 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 424837 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 186591 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12766 # Number of HB maps that are undone due to squashing +system.cpu3.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 207704 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 570857 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 442944 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 195081 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12623 # Number of HB maps that are undone due to squashing system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1226 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 13474 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 80900 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 38213 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 38893 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 238990 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10730 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.359288 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.308373 # Number of insts issued each cycle +system.cpu3.rename.tempSerializingInsts 1224 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 12502 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 84726 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 40382 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 40460 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 35337 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 246420 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6261 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 248749 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10413 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 9956 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 566 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 175633 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.416300 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.309117 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 39046 22.21% 97.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 66575 37.91% 37.91% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 22292 12.69% 50.60% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 40685 23.16% 73.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 41298 23.51% 97.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3252 1.85% 99.13% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1166 0.66% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 47 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 175820 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 175633 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 17 6.20% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 47 17.15% 23.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 76.64% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 6.46% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 36 13.69% 20.15% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 79.85% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 115815 48.46% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 85668 35.85% 84.31% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 119915 48.21% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.21% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 89111 35.82% 84.03% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 39723 15.97% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 238990 # Type of FU issued -system.cpu3.iq.rate 1.348535 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 654176 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 237197 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 248749 # Type of FU issued +system.cpu3.iq.rate 1.405219 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 263 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001057 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 673451 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 263132 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 246950 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 239264 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 249012 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 35153 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2413 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2247 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1461 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2346 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 674 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 283043 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 80900 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 38213 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2300 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 645 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 294144 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 84726 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 40382 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1060 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 47 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1378 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 247595 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 83855 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 39788 # number of nop insts executed -system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed -system.cpu3.iew.exec_branches 49028 # Number of branches executed -system.cpu3.iew.exec_stores 37424 # Number of stores executed -system.cpu3.iew.exec_rate 1.342091 # Inst execution rate -system.cpu3.iew.wb_sent 237481 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 237197 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 134032 # num instructions producing a value -system.cpu3.iew.wb_consumers 138708 # num instructions consuming a value +system.cpu3.iew.exec_nop 41463 # number of nop insts executed +system.cpu3.iew.exec_refs 123509 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50804 # Number of branches executed +system.cpu3.iew.exec_stores 39654 # Number of stores executed +system.cpu3.iew.exec_rate 1.398700 # Inst execution rate +system.cpu3.iew.wb_sent 247239 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 246950 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 140249 # num instructions producing a value +system.cpu3.iew.wb_consumers 144916 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.338417 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.966289 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.395056 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.967795 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1266 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165699 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.633836 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.016583 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 11951 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5695 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1265 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165578 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.704170 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.038930 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 68017 41.05% 41.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 47143 28.45% 69.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6068 3.66% 73.16% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7148 4.31% 77.48% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1577 0.95% 78.43% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 33420 20.17% 98.60% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 508 0.31% 98.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 998 0.60% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 820 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 64386 38.89% 38.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48906 29.54% 68.42% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6642 4.01% 76.11% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.06% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 35662 21.54% 98.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 504 0.30% 98.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 999 0.60% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 818 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165699 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 270725 # Number of instructions committed -system.cpu3.commit.committedOps 270725 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165578 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 282173 # Number of instructions committed +system.cpu3.commit.committedOps 282173 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 115239 # Number of memory references committed -system.cpu3.commit.loads 78487 # Number of loads committed -system.cpu3.commit.membars 5499 # Number of memory barriers committed -system.cpu3.commit.branches 48212 # Number of branches committed +system.cpu3.commit.refs 121476 # Number of memory references committed +system.cpu3.commit.loads 82479 # Number of loads committed +system.cpu3.commit.membars 4985 # Number of memory barriers committed +system.cpu3.commit.branches 49947 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 185574 # Number of committed integer instructions. +system.cpu3.commit.int_insts 193548 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 820 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 818 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 447315 # The number of ROB reads -system.cpu3.rob.rob_writes 568397 # The number of ROB writes -system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1402 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 226224 # Number of Instructions Simulated -system.cpu3.committedOps 226224 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 226224 # Number of Instructions Simulated -system.cpu3.cpi 0.783392 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.783392 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 410473 # number of integer regfile reads -system.cpu3.int_regfile_writes 191353 # number of integer regfile writes +system.cpu3.rob.rob_reads 458297 # The number of ROB reads +system.cpu3.rob.rob_writes 590554 # The number of ROB writes +system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1385 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44892 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 236447 # Number of Instructions Simulated +system.cpu3.committedOps 236447 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 236447 # Number of Instructions Simulated +system.cpu3.cpi 0.748658 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.748658 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.335723 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.335723 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 429146 # number of integer regfile reads +system.cpu3.int_regfile_writes 199911 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads +system.cpu3.misc_regfile_reads 125103 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 79.942822 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 80.480006 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 19114 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 44.451163 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942822 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.480006 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157188 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.157188 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 20994 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 20994 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 20090 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 20090 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 20090 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 20090 # number of overall hits -system.cpu3.icache.overall_hits::total 20090 # number of overall hits +system.cpu3.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 20019 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 20019 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 19114 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 19114 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 19114 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 19114 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 19114 # number of overall hits +system.cpu3.icache.overall_hits::total 19114 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449745 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6449745 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6449745 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6449745 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6449745 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6449745 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 20565 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 20565 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 20565 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023097 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.023097 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13578.410526 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13578.410526 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13578.410526 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13578.410526 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6525745 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6525745 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6525745 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6525745 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6525745 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6525745 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 19589 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 19589 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 19589 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 19589 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 19589 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 19589 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024248 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.024248 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024248 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.024248 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024248 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.024248 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13738.410526 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13738.410526 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2493,111 +2516,111 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223755 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223755 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223755 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5223755 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223755 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5223755 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12176.585082 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 45 # 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number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5298255 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5298255 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021951 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.021951 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021951 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.021951 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.692248 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.751493 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 44991 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1606.821429 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692248 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.751493 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048343 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.048343 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 335202 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 335202 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 46656 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 36553 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 36553 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 83209 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 83209 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 83209 # number of overall hits -system.cpu3.dcache.overall_hits::total 83209 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 333 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 333 # 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number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 83673 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 83673 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 83673 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 83673 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007087 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.007087 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003571 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003571 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12757.057057 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12757.057057 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25584.061069 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 25584.061069 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 16378.474138 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 16378.474138 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 350966 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 350966 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 48333 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 48333 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 38794 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 38794 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 87127 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 87127 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 87127 # 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number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3479012 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3479012 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 512008 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 512008 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 8118148 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 8118148 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 8118148 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 8118148 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 48684 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 48684 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 38933 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 38933 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 87617 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 87617 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 87617 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 87617 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007210 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.007210 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003570 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003570 # 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number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 181 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 212 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 212 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 212 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 212 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 100 # 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number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2410762 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2410762 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2410762 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2410762 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002726 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003012 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14082.380000 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14082.380000 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 197 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 230 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 230 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 230 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 230 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 154 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1051018 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1051018 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1439238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1439238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 407992 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 407992 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2490256 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2490256 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2490256 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2490256 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003163 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003163 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002723 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002723 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.812500 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.812500 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002967 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.002967 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002967 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.002967 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6824.792208 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6824.792208 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13577.716981 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13577.716981 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7846 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7846 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9577.907692 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9577.907692 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9577.907692 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9577.907692 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |