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authorAli Saidi <Ali.Saidi@ARM.com>2012-08-15 10:38:05 -0400
committerAli Saidi <Ali.Saidi@ARM.com>2012-08-15 10:38:05 -0400
commit73e9e923d00c6f5df9e79a6c40ecc159894d2bc5 (patch)
treef84188c6697fe79f0521b73d9d38855ce7e04d29 /tests/quick/se/40.m5threads-test-atomic/ref
parentdd1b346584e520ba970e62aa3bcc7d32828cdeba (diff)
downloadgem5-73e9e923d00c6f5df9e79a6c40ecc159894d2bc5.tar.xz
stats: Update stats for syscall emulation Linux kernel changes.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref')
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini2
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout48
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt3485
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini6
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout8
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt274
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini2
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout8
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt260
9 files changed, 2046 insertions, 2047 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index e18da5544..8f654c19e 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -1774,7 +1774,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.l2c.mem_side system.system_port
[system.physmem]
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 2447cd00c..63ee30b34 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:54:18
-gem5 started Jul 2 2012 11:31:33
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:31
gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
@@ -29,40 +29,40 @@ Iteration 2 completed
[Iteration 3, Thread 3] Got lock
[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
Iteration 3 completed
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 4, Thread 1] Got lock
[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
Iteration 4 completed
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 5, Thread 3] Got lock
[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
Iteration 5 completed
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
Iteration 6 completed
[Iteration 7, Thread 2] Got lock
[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
Iteration 8 completed
[Iteration 9, Thread 3] Got lock
[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
@@ -73,10 +73,10 @@ Iteration 8 completed
Iteration 9 completed
[Iteration 10, Thread 2] Got lock
[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
Iteration 10 completed
PASSED :-)
-Exiting @ tick 113941500 because target called exit()
+Exiting @ tick 113910500 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 08b3d0977..a13e56193 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,17 +1,17 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000114 # Number of seconds simulated
-sim_ticks 113941500 # Number of ticks simulated
-final_tick 113941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 113910500 # Number of ticks simulated
+final_tick 113910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 130117 # Simulator instruction rate (inst/s)
-host_op_rate 130117 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 13474596 # Simulator tick rate (ticks/s)
-host_mem_usage 234988 # Number of bytes of host memory used
-host_seconds 8.46 # Real time elapsed on the host
-sim_insts 1100269 # Number of instructions simulated
-sim_ops 1100269 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory
+host_inst_rate 141669 # Simulator instruction rate (inst/s)
+host_op_rate 141669 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 14682125 # Simulator tick rate (ticks/s)
+host_mem_usage 244464 # Number of bytes of host memory used
+host_seconds 7.76 # Real time elapsed on the host
+sim_insts 1099129 # Number of instructions simulated
+sim_ops 1099129 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
@@ -19,13 +19,13 @@ system.physmem.bytes_read::cpu2.inst 320 # Nu
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::total 43008 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total 42944 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::total 29248 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
@@ -33,340 +33,339 @@ system.physmem.num_reads::cpu2.inst 5 # Nu
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 672 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 203894104 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 94364213 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 47182107 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 11233835 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 2808459 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 7301993 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 3370150 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7301993 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 377456853 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 203894104 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 47182107 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 2808459 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 3370150 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 257254819 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 203894104 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 94364213 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 47182107 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 11233835 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 2808459 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 7301993 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 3370150 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7301993 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 377456853 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total 671 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 203387747 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 94389894 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 47194947 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 11236892 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 2809223 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 7303980 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 3371068 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7303980 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 376997731 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 203387747 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 47194947 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 2809223 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 3371068 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 256762985 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 203387747 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 94389894 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 47194947 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 11236892 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 2809223 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 7303980 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 3371068 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7303980 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 376997731 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 227884 # number of cpu cycles simulated
+system.cpu0.numCycles 227822 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 88195 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 85894 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 1314 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 85741 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 83416 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 88179 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 85929 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 1290 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 85894 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 83486 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 17885 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 523742 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 88195 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 83933 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 172058 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 4069 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 15014 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles 17727 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 523680 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 88179 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 84003 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 172095 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 4009 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 15408 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 1439 # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines 6122 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 517 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 209007 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.505859 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.211450 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.PendingTrapStallCycles 1281 # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines 6036 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 519 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 209087 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.504603 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.209881 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 36949 17.68% 17.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 85270 40.80% 58.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 593 0.28% 58.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1005 0.48% 59.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 500 0.24% 59.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 81190 38.85% 98.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 659 0.32% 98.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 361 0.17% 98.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2480 1.19% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 36992 17.69% 17.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 85294 40.79% 58.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 585 0.28% 58.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1000 0.48% 59.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 484 0.23% 59.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 81297 38.88% 98.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 665 0.32% 98.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 355 0.17% 98.84% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2415 1.16% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 209007 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.387017 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.298283 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 18552 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 16516 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 170985 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 348 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2606 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 520718 # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles 2606 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 19281 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 2206 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13583 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 170639 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 692 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 517471 # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 300 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 353567 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 1032190 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 1032190 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 339600 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 13967 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 909 # count of serializing insts renamed
+system.cpu0.fetch.rateDist::total 209087 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.387052 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.298637 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 18268 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 16880 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 171017 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 351 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 2571 # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts 520658 # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles 2571 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 18993 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 2288 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13870 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 170679 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 686 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 517484 # Number of instructions processed by rename
+system.cpu0.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 353459 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 1032335 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 1032335 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 339779 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 13680 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4082 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 165924 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 83735 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 81055 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 80764 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 432543 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 950 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 429278 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 11501 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 11387 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 391 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 209007 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.053893 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.097042 # Number of insts issued each cycle
+system.cpu0.rename.skidInsts 4009 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 165974 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 83785 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 81138 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 80830 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 432592 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 429324 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 270 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 11361 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 11323 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 209087 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.053327 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.097112 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 36203 17.32% 17.32% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5360 2.56% 19.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 82686 39.56% 59.45% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 82056 39.26% 98.71% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1635 0.78% 99.49% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 680 0.33% 99.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 282 0.13% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 36280 17.35% 17.35% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5325 2.55% 19.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 82668 39.54% 59.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 82134 39.28% 98.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1638 0.78% 99.50% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 661 0.32% 99.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 275 0.13% 99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 11 0.01% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 12 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 209007 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 209087 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 43 16.23% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 110 41.51% 57.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 112 42.26% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 52 18.77% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 113 40.79% 59.57% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 112 40.43% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 180966 42.16% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 165240 38.49% 80.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 83072 19.35% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 180924 42.14% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 165296 38.50% 80.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 83104 19.36% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 429278 # Type of FU issued
-system.cpu0.iq.rate 1.883757 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 265 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000617 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 1068049 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 445050 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 427325 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total 429324 # Type of FU issued
+system.cpu0.iq.rate 1.884471 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 277 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.000645 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 1068282 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 444960 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 427393 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 429543 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 429601 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 80408 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 80458 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2540 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1537 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedStores 1539 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2606 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 1701 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 86 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 515038 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 368 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 165924 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 83735 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles 2571 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 1789 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 515149 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 291 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 165974 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 83785 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 95 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 370 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 1149 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 428170 # Number of executed instructions
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+system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly
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system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
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-system.cpu0.iew.exec_refs 247840 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 85100 # Number of branches executed
-system.cpu0.iew.exec_stores 82919 # Number of stores executed
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-system.cpu0.iew.wb_count 427325 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 253224 # num instructions producing a value
-system.cpu0.iew.wb_consumers 255650 # num instructions consuming a value
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system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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-system.cpu0.iew.wb_fanout 0.990510 # average fanout of values written-back
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+system.cpu0.iew.wb_fanout 0.990608 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts 501745 # The number of committed instructions
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system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
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system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 36760 17.81% 17.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 84779 41.07% 58.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2446 1.18% 60.07% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 715 0.35% 60.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 578 0.28% 60.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 80055 38.78% 99.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 554 0.27% 99.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 230 0.11% 99.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 36757 17.80% 17.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 84830 41.07% 58.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2489 1.21% 60.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 701 0.34% 60.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 579 0.28% 60.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 80093 38.78% 99.48% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 561 0.27% 99.75% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 222 0.11% 99.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 206418 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 501745 # Number of instructions committed
-system.cpu0.commit.committedOps 501745 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 206533 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 502020 # Number of instructions committed
+system.cpu0.commit.committedOps 502020 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 245582 # Number of memory references committed
-system.cpu0.commit.loads 163384 # Number of loads committed
+system.cpu0.commit.refs 245725 # Number of memory references committed
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system.cpu0.commit.membars 84 # Number of memory barriers committed
-system.cpu0.commit.branches 84086 # Number of branches committed
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system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 337930 # Number of committed integer instructions.
+system.cpu0.commit.int_insts 338110 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 719961 # The number of ROB reads
-system.cpu0.rob.rob_writes 1032633 # The number of ROB writes
-system.cpu0.timesIdled 343 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 18877 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 420844 # Number of Instructions Simulated
-system.cpu0.committedOps 420844 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 420844 # Number of Instructions Simulated
-system.cpu0.cpi 0.541493 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.541493 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.846747 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.846747 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 766075 # number of integer regfile reads
-system.cpu0.int_regfile_writes 345063 # number of integer regfile writes
+system.cpu0.rob.rob_reads 720176 # The number of ROB reads
+system.cpu0.rob.rob_writes 1032801 # The number of ROB writes
+system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 18735 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 421071 # Number of Instructions Simulated
+system.cpu0.committedOps 421071 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 421071 # Number of Instructions Simulated
+system.cpu0.cpi 0.541054 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.541054 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.848246 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.848246 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 766308 # number of integer regfile reads
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system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
-system.cpu0.misc_regfile_reads 249668 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 249733 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
-system.cpu0.icache.replacements 308 # number of replacements
-system.cpu0.icache.tagsinuse 248.197747 # Cycle average of tags in use
-system.cpu0.icache.total_refs 5361 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 601 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 8.920133 # Average number of references to valid blocks.
+system.cpu0.icache.replacements 302 # number of replacements
+system.cpu0.icache.tagsinuse 247.706871 # Cycle average of tags in use
+system.cpu0.icache.total_refs 5276 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 594 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 8.882155 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 248.197747 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.484761 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.484761 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 5361 # number of ReadReq hits
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-system.cpu0.icache.ReadReq_misses::total 761 # number of ReadReq misses
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-system.cpu0.icache.overall_misses::total 761 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29540500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 29540500 # number of ReadReq miss cycles
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-system.cpu0.icache.demand_miss_latency::total 29540500 # number of demand (read+write) miss cycles
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-system.cpu0.icache.overall_miss_latency::total 29540500 # number of overall miss cycles
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 38818.002628 # average ReadReq miss latency
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system.cpu0.icache.blocked_cycles::no_mshrs 13500 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@@ -375,476 +374,476 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 13500
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu0.dcache.demand_avg_miss_latency::total 41670.770776 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 41670.770776 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 112000 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6638.888889 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6222.222222 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 345 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 345 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 392 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 392 # number of WriteReq MSHR hits
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-system.cpu0.dcache.overall_mshr_hits::cpu0.data 737 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 737 # number of overall MSHR hits
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-system.cpu0.dcache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses
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-system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses
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-system.cpu0.dcache.SwapReq_mshr_misses::total 24 # number of SwapReq MSHR misses
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-system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5693511 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.SwapReq_mshr_miss_latency::total 405000 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12424511 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 12424511 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12424511 # number of overall MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_rate::total 0.002107 # mshr miss rate for demand accesses
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31630.616667 # average ReadReq mshr miss latency
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39362.573099 # average WriteReq mshr miss latency
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-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16875 # average SwapReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35397.467236 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35397.467236 # average overall mshr miss latency
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32287.348066 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32287.348066 # average ReadReq mshr miss latency
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+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 191339 # number of cpu cycles simulated
+system.cpu1.numCycles 191317 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 49631 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 46572 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 1528 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 42950 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 41997 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 53059 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 50011 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 46382 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 45427 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 805 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.usedRAS 803 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 33375 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 271825 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 49631 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 42802 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 98758 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 4453 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 42292 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.icacheStallCycles 31318 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 294530 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 53059 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 46230 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 104588 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 4407 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 38684 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles 6725 # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.NoActiveThreadStallCycles 6733 # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines 23889 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 185079 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.468697 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.066601 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.CacheLines 21833 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 185209 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.590257 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.119058 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 86321 46.64% 46.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 51121 27.62% 74.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 7925 4.28% 78.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3336 1.80% 80.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 734 0.40% 80.74% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 30013 16.22% 96.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1151 0.62% 97.58% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 885 0.48% 98.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3593 1.94% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 80621 43.53% 43.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 53529 28.90% 72.43% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 6903 3.73% 76.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3276 1.77% 77.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 732 0.40% 78.32% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 34514 18.64% 96.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1160 0.63% 97.58% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 883 0.48% 98.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3591 1.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 185079 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.259388 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.420646 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 40472 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 37211 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 91012 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 6805 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2854 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 267804 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 2854 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 41302 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 21637 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 14674 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 84497 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 13390 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 265308 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full
+system.cpu1.fetch.rateDist::total 185209 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.277336 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.539487 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 37437 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 34588 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 97784 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 5856 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2811 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 290465 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 2811 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 38251 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 18737 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 14962 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 92242 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 11473 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 288015 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 184298 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 499771 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 499771 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 168579 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 15719 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1236 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 16177 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 72909 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 33507 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 35450 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 28267 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 217311 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 8226 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 220400 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 173 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 13138 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 12222 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 185079 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.190843 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.296813 # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands 201252 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 549512 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 549512 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 185544 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 15708 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1231 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 14237 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 80834 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 37999 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 38862 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 32764 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 237666 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 7151 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 239902 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 12973 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 11962 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 719 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 185209 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.295304 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.311031 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 84217 45.50% 45.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 27917 15.08% 60.59% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 33688 18.20% 78.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 34243 18.50% 97.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3324 1.80% 99.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1232 0.67% 99.75% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 345 0.19% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 78322 42.29% 42.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 24974 13.48% 55.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 38132 20.59% 76.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 38761 20.93% 97.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3339 1.80% 99.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1231 0.66% 99.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 185079 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 185209 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 21 6.60% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 87 27.36% 33.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 210 66.04% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 21 6.44% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 95 29.14% 35.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 210 64.42% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 108844 49.38% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 78735 35.72% 85.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 32821 14.89% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 116849 48.71% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 85748 35.74% 84.45% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 37305 15.55% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 220400 # Type of FU issued
-system.cpu1.iq.rate 1.151882 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 318 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001443 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 626370 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 238714 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 218326 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 239902 # Type of FU issued
+system.cpu1.iq.rate 1.253950 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 326 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001359 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 665467 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 257831 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 237819 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 220718 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 240228 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 28122 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 32613 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2824 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2758 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1558 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1567 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2854 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 2376 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 261974 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 434 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 72909 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 33507 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1131 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 2811 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 2340 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 107 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 284663 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 80834 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 37999 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 510 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 1187 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 219051 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 71704 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1349 # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 1185 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 1694 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 238552 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 79712 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 36437 # number of nop insts executed
-system.cpu1.iew.exec_refs 104435 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 45735 # Number of branches executed
-system.cpu1.iew.exec_stores 32731 # Number of stores executed
-system.cpu1.iew.exec_rate 1.144832 # Inst execution rate
-system.cpu1.iew.wb_sent 218612 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 218326 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 121254 # num instructions producing a value
-system.cpu1.iew.wb_consumers 126110 # num instructions consuming a value
+system.cpu1.iew.exec_nop 39846 # number of nop insts executed
+system.cpu1.iew.exec_refs 116931 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 49232 # Number of branches executed
+system.cpu1.iew.exec_stores 37219 # Number of stores executed
+system.cpu1.iew.exec_rate 1.246894 # Inst execution rate
+system.cpu1.iew.wb_sent 238105 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 237819 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 133762 # num instructions producing a value
+system.cpu1.iew.wb_consumers 138617 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.141043 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.961494 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.243063 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.964975 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts 246738 # The number of committed instructions
-system.cpu1.commit.commitCommittedOps 246738 # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts 15223 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 7427 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1528 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 175501 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.405907 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.932846 # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts 269706 # The number of committed instructions
+system.cpu1.commit.commitCommittedOps 269706 # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts 14936 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 6432 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1521 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 175666 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.535334 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.989786 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 84843 48.34% 48.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 43671 24.88% 73.23% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6232 3.55% 76.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 8331 4.75% 81.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1551 0.88% 82.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 28453 16.21% 98.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 613 0.35% 98.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 993 0.57% 99.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 78046 44.43% 44.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 47129 26.83% 71.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6230 3.55% 74.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 7351 4.18% 78.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1552 0.88% 79.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 32915 18.74% 98.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 634 0.36% 98.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 175501 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 246738 # Number of instructions committed
-system.cpu1.commit.committedOps 246738 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 175666 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 269706 # Number of instructions committed
+system.cpu1.commit.committedOps 269706 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 102034 # Number of memory references committed
-system.cpu1.commit.loads 70085 # Number of loads committed
-system.cpu1.commit.membars 6711 # Number of memory barriers committed
-system.cpu1.commit.branches 44619 # Number of branches committed
+system.cpu1.commit.refs 114508 # Number of memory references committed
+system.cpu1.commit.loads 78076 # Number of loads committed
+system.cpu1.commit.membars 5720 # Number of memory barriers committed
+system.cpu1.commit.branches 48115 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 168775 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 184747 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 436061 # The number of ROB reads
-system.cpu1.rob.rob_writes 526790 # The number of ROB writes
+system.cpu1.rob.rob_reads 458907 # The number of ROB reads
+system.cpu1.rob.rob_writes 572109 # The number of ROB writes
system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 6260 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 36543 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 204620 # Number of Instructions Simulated
-system.cpu1.committedOps 204620 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 204620 # Number of Instructions Simulated
-system.cpu1.cpi 0.935094 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.935094 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.069411 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.069411 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 373202 # number of integer regfile reads
-system.cpu1.int_regfile_writes 174771 # number of integer regfile writes
+system.cpu1.idleCycles 6108 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 36503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 225079 # Number of Instructions Simulated
+system.cpu1.committedOps 225079 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 225079 # Number of Instructions Simulated
+system.cpu1.cpi 0.849999 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.849999 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.176472 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.176472 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 410678 # number of integer regfile reads
+system.cpu1.int_regfile_writes 191757 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 106146 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 118640 # number of misc regfile reads
system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
system.cpu1.icache.replacements 322 # number of replacements
-system.cpu1.icache.tagsinuse 90.902674 # Cycle average of tags in use
-system.cpu1.icache.total_refs 23372 # Total number of references to valid blocks.
+system.cpu1.icache.tagsinuse 90.918932 # Cycle average of tags in use
+system.cpu1.icache.total_refs 21316 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 53.605505 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 48.889908 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 90.902674 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.177544 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.177544 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 23372 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 23372 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 23372 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 23372 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 23372 # number of overall hits
-system.cpu1.icache.overall_hits::total 23372 # number of overall hits
+system.cpu1.icache.occ_blocks::cpu1.inst 90.918932 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.177576 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.177576 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 21316 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 21316 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 21316 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 21316 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 21316 # number of overall hits
+system.cpu1.icache.overall_hits::total 21316 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses
system.cpu1.icache.overall_misses::total 517 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11874500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 11874500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 11874500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 11874500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 11874500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 11874500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 23889 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 23889 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 23889 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 23889 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 23889 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 23889 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021642 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.021642 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021642 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.021642 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021642 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.021642 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22968.085106 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 22968.085106 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22968.085106 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 22968.085106 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22968.085106 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 22968.085106 # average overall miss latency
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11871000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 11871000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 11871000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 11871000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 11871000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 11871000 # number of overall miss cycles
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@@ -865,94 +864,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 436
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@@ -961,366 +960,366 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003137 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003137 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003526 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.003526 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003526 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.003526 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19719.903614 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19719.903614 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16390 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16390 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20881.818182 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20881.818182 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18468.060150 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18468.060150 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18468.060150 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18468.060150 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3164503 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3164503 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1890000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1890000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1168500 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1168500 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5054503 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 5054503 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5054503 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 5054503 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003398 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003398 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002915 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002915 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.787879 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.787879 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.003188 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.003188 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19778.143750 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19778.143750 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17830.188679 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17830.188679 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 22471.153846 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 22471.153846 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.numCycles 191032 # number of cpu cycles simulated
+system.cpu2.numCycles 191010 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups 57390 # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted 54193 # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect 1550 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups 50681 # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits 49645 # Number of BTB hits
+system.cpu2.BPredUnit.lookups 57179 # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted 53988 # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect 1553 # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups 50487 # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits 49441 # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS 804 # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.usedRAS 815 # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu2.fetch.icacheStallCycles 29539 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 321276 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 57390 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 50449 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 112230 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 4473 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 35583 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles 29527 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 320031 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 57179 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 50256 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 111848 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 4474 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 35937 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles 6761 # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.NoActiveThreadStallCycles 6751 # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines 20533 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 334 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 188044 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.708515 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.158633 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.CacheLines 20539 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 187993 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.702356 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.156955 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 75814 40.32% 40.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 56962 30.29% 70.61% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 6138 3.26% 73.87% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3348 1.78% 75.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 769 0.41% 76.06% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 39287 20.89% 96.95% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1207 0.64% 97.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 911 0.48% 98.08% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3608 1.92% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 76145 40.50% 40.50% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 56782 30.20% 70.71% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 6165 3.28% 73.99% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3347 1.78% 75.77% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 731 0.39% 76.16% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 39077 20.79% 96.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1243 0.66% 97.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 913 0.49% 98.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3590 1.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 188044 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.300421 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.681792 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 35225 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 31967 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 106013 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5229 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 2849 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 316907 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 2849 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 36004 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 16323 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 14784 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 101094 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 10229 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 314547 # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 220052 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 605102 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 605102 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 204228 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 15824 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1236 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1356 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 12873 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 89800 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 42907 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 42940 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 37601 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 260749 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 6485 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 262481 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 146 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 13131 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 11780 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 188044 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.395849 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.314415 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 187993 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.299351 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.675467 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 35252 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 32290 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 105597 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5255 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 2848 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 315625 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 2848 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 36036 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 16472 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 14955 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 100655 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 10276 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 313299 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 219155 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 602465 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 602465 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 203359 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 15796 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1243 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1365 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 12944 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 89370 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 42679 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 42734 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 37374 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 259618 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 6531 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 261379 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 13068 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 11786 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 697 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 187993 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.390366 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.314588 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 73292 38.98% 38.98% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 23055 12.26% 51.24% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 43065 22.90% 74.14% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 43582 23.18% 97.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3340 1.78% 99.09% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1248 0.66% 99.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 346 0.18% 99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 73641 39.17% 39.17% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 23139 12.31% 51.48% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 42800 22.77% 74.25% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 43353 23.06% 97.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3352 1.78% 99.09% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1252 0.67% 99.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 188044 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 187993 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 21 6.71% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 82 26.20% 32.91% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 210 67.09% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 126143 48.06% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 94161 35.87% 83.93% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 42177 16.07% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 125670 48.08% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 93767 35.87% 83.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 41942 16.05% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 262481 # Type of FU issued
-system.cpu2.iq.rate 1.374016 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 316 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 713468 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 280402 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 260315 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 261379 # Type of FU issued
+system.cpu2.iq.rate 1.368405 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 313 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001197 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 711198 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 279252 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 259224 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 262797 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 261692 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 37443 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 37218 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 2690 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1644 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 1641 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 2849 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 1860 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 311245 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 407 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 89800 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 42907 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 74 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles 2848 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 1926 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 309970 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 89370 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 42679 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 72 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 516 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 1201 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1717 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 261072 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 88760 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1409 # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 514 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 1208 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1722 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 259980 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 88335 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1399 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 44011 # number of nop insts executed
-system.cpu2.iew.exec_refs 130847 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 53503 # Number of branches executed
-system.cpu2.iew.exec_stores 42087 # Number of stores executed
-system.cpu2.iew.exec_rate 1.366640 # Inst execution rate
-system.cpu2.iew.wb_sent 260613 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 260315 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 147697 # num instructions producing a value
-system.cpu2.iew.wb_consumers 152590 # num instructions consuming a value
+system.cpu2.iew.exec_nop 43821 # number of nop insts executed
+system.cpu2.iew.exec_refs 130189 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 53302 # Number of branches executed
+system.cpu2.iew.exec_stores 41854 # Number of stores executed
+system.cpu2.iew.exec_rate 1.361081 # Inst execution rate
+system.cpu2.iew.wb_sent 259524 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 259224 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 147020 # num instructions producing a value
+system.cpu2.iew.wb_consumers 151915 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.362677 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.967934 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.357123 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.967778 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitCommittedInsts 296145 # The number of committed instructions
-system.cpu2.commit.commitCommittedOps 296145 # The number of committed instructions
-system.cpu2.commit.commitSquashedInsts 15092 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 5798 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1550 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 178435 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.659680 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.032759 # Number of insts commited each cycle
+system.cpu2.commit.commitCommittedInsts 294930 # The number of committed instructions
+system.cpu2.commit.commitCommittedOps 294930 # The number of committed instructions
+system.cpu2.commit.commitSquashedInsts 15032 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 5834 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1553 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 178395 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.653241 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.030877 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 72400 40.57% 40.57% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 51371 28.79% 69.36% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 6245 3.50% 72.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 6660 3.73% 76.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1539 0.86% 77.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 37793 21.18% 98.64% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 621 0.35% 98.99% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 991 0.56% 99.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 72759 40.79% 40.79% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 51159 28.68% 69.46% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 6241 3.50% 72.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 6697 3.75% 76.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1549 0.87% 77.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 37557 21.05% 98.64% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 629 0.35% 98.99% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 989 0.55% 99.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 178435 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 296145 # Number of instructions committed
-system.cpu2.commit.committedOps 296145 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 178395 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 294930 # Number of instructions committed
+system.cpu2.commit.committedOps 294930 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 128361 # Number of memory references committed
-system.cpu2.commit.loads 87098 # Number of loads committed
-system.cpu2.commit.membars 5084 # Number of memory barriers committed
-system.cpu2.commit.branches 52312 # Number of branches committed
+system.cpu2.commit.refs 127718 # Number of memory references committed
+system.cpu2.commit.loads 86680 # Number of loads committed
+system.cpu2.commit.membars 5119 # Number of memory barriers committed
+system.cpu2.commit.branches 52122 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 202794 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 201960 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 488270 # The number of ROB reads
-system.cpu2.rob.rob_writes 625337 # The number of ROB writes
-system.cpu2.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 2988 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 36850 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 247959 # Number of Instructions Simulated
-system.cpu2.committedOps 247959 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 247959 # Number of Instructions Simulated
-system.cpu2.cpi 0.770418 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.770418 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.297997 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.297997 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 452595 # number of integer regfile reads
-system.cpu2.int_regfile_writes 210629 # number of integer regfile writes
+system.cpu2.rob.rob_reads 486955 # The number of ROB reads
+system.cpu2.rob.rob_writes 622786 # The number of ROB writes
+system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 3017 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 36810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 246900 # Number of Instructions Simulated
+system.cpu2.committedOps 246900 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 246900 # Number of Instructions Simulated
+system.cpu2.cpi 0.773633 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.773633 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.292602 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.292602 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 450556 # number of integer regfile reads
+system.cpu2.int_regfile_writes 209704 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 132559 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 131893 # number of misc regfile reads
system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
system.cpu2.icache.replacements 322 # number of replacements
-system.cpu2.icache.tagsinuse 84.182173 # Cycle average of tags in use
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+system.cpu2.dcache.overall_accesses::total 92067 # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007613 # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total 0.007613 # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003393 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total 0.003393 # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005735 # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total 0.005735 # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005735 # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total 0.005735 # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 26149.100257 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 26149.100257 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24392.086331 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 24392.086331 # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21657.894737 # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 21657.894737 # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25686.553030 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 25686.553030 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25686.553030 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 25686.553030 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1437,366 +1436,366 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 234 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total 234 # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data 276 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total 276 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data 276 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total 276 # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data 256 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data 256 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total 256 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2456507 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2456507 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1732500 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1732500 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1052000 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1052000 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4189007 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 4189007 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4189007 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 4189007 # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002944 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002549 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002549 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002768 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total 0.002768 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002768 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total 0.002768 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16268.258278 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16268.258278 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16500 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16500 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18785.714286 # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18785.714286 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16363.308594 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16363.308594 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16363.308594 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16363.308594 # average overall mshr miss latency
+system.cpu2.dcache.demand_mshr_hits::cpu2.data 269 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data 269 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total 269 # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data 259 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data 259 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2539505 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2539505 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1736500 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1736500 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1057000 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1057000 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4276005 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 4276005 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4276005 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 4276005 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003033 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003033 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002539 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002539 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total 0.002813 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total 0.002813 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16383.903226 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16383.903226 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16697.115385 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16697.115385 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18543.859649 # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18543.859649 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.numCycles 190752 # number of cpu cycles simulated
+system.cpu3.numCycles 190730 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.BPredUnit.lookups 53643 # Number of BP lookups
-system.cpu3.BPredUnit.condPredicted 50394 # Number of conditional branches predicted
-system.cpu3.BPredUnit.condIncorrect 1547 # Number of conditional branches incorrect
-system.cpu3.BPredUnit.BTBLookups 46912 # Number of BTB lookups
-system.cpu3.BPredUnit.BTBHits 45897 # Number of BTB hits
+system.cpu3.BPredUnit.lookups 50135 # Number of BP lookups
+system.cpu3.BPredUnit.condPredicted 46886 # Number of conditional branches predicted
+system.cpu3.BPredUnit.condIncorrect 1563 # Number of conditional branches incorrect
+system.cpu3.BPredUnit.BTBLookups 43380 # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits 42368 # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.BPredUnit.usedRAS 838 # Number of times the RAS was used to get a target.
+system.cpu3.BPredUnit.usedRAS 844 # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu3.fetch.icacheStallCycles 31381 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 296607 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 53643 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 46735 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 105748 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 4379 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles 39758 # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles 33373 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 273510 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 50135 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 43212 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 99693 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 4441 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles 43703 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles 6743 # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.NoActiveThreadStallCycles 6715 # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 22503 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 187456 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.582275 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.112091 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.CacheLines 24485 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 187356 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.459841 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.059659 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 81708 43.59% 43.59% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 54260 28.95% 72.53% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 7170 3.82% 76.36% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3258 1.74% 78.10% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 706 0.38% 78.47% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 34710 18.52% 96.99% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1204 0.64% 97.63% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 885 0.47% 98.10% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 3555 1.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 87663 46.79% 46.79% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 51707 27.60% 74.39% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 8154 4.35% 78.74% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3276 1.75% 80.49% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 745 0.40% 80.89% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 30183 16.11% 97.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1182 0.63% 97.63% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 888 0.47% 98.10% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 3558 1.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 187456 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.281219 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.554935 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 37941 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 35250 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 98653 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 6106 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2763 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 292333 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 2763 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 38724 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 18900 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 15518 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 92845 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 11963 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 289904 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands 201915 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 552179 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 552179 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 186764 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 15151 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1285 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1418 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 14719 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 81367 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 38245 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 39205 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 32957 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 238924 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 7473 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 241868 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 12521 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 10991 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 722 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 187456 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.290265 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.307286 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 187356 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.262858 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.434017 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 40875 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 38262 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 91696 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 6999 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 2809 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 269218 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 2809 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 41677 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 21676 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 15745 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 84975 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 13759 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 266737 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands 184789 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 501822 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 501822 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 169578 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 15211 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1292 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1426 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 16516 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 73298 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 33720 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 35666 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 28418 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 218299 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 222114 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 12726 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 11163 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 773 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 187356 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.185518 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.293170 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 79218 42.26% 42.26% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 25849 13.79% 56.05% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 38415 20.49% 76.54% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 38999 20.80% 97.35% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3297 1.76% 99.10% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1241 0.66% 99.77% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 322 0.17% 99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 85320 45.54% 45.54% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 28690 15.31% 60.85% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 33902 18.09% 78.95% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 34456 18.39% 97.34% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3309 1.77% 99.10% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1236 0.66% 99.76% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 327 0.17% 99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 187456 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 187356 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 22 7.19% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 74 24.18% 31.37% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 210 68.63% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 22 7.17% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 75 24.43% 31.60% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 210 68.40% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 117603 48.62% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 86736 35.86% 84.48% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 37529 15.52% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 109540 49.32% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 79567 35.82% 85.14% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 33007 14.86% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 241868 # Type of FU issued
-system.cpu3.iq.rate 1.267971 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 306 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001265 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 671615 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 258950 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 239863 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 222114 # Type of FU issued
+system.cpu3.iq.rate 1.164547 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 307 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 632004 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 239536 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 220090 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 242174 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 222421 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 32833 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 28294 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2526 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 2578 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1583 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1587 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2763 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 1788 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 286739 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 413 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 81367 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 38245 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1210 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles 2809 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 1854 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 263586 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 73298 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 33720 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1219 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 53 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 32 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 503 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 1210 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1713 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 240581 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 80413 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1287 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1726 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 220807 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 72290 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 1307 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 40342 # number of nop insts executed
-system.cpu3.iew.exec_refs 117868 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 49825 # Number of branches executed
-system.cpu3.iew.exec_stores 37455 # Number of stores executed
-system.cpu3.iew.exec_rate 1.261224 # Inst execution rate
-system.cpu3.iew.wb_sent 240146 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 239863 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 134653 # num instructions producing a value
-system.cpu3.iew.wb_consumers 139524 # num instructions consuming a value
+system.cpu3.iew.exec_nop 36810 # number of nop insts executed
+system.cpu3.iew.exec_refs 105220 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 46242 # Number of branches executed
+system.cpu3.iew.exec_stores 32930 # Number of stores executed
+system.cpu3.iew.exec_rate 1.157694 # Inst execution rate
+system.cpu3.iew.wb_sent 220376 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 220090 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 122048 # num instructions producing a value
+system.cpu3.iew.wb_consumers 126919 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.257460 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.965088 # average fanout of values written-back
+system.cpu3.iew.wb_rate 1.153935 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.961621 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitCommittedInsts 272332 # The number of committed instructions
-system.cpu3.commit.commitCommittedOps 272332 # The number of committed instructions
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-system.cpu3.commit.commitNonSpecStalls 6751 # The number of times commit has been forced to stall to communicate backwards
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system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 79207 44.51% 44.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 47739 26.83% 71.34% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 6222 3.50% 74.83% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 7617 4.28% 79.11% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1549 0.87% 79.98% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 33224 18.67% 98.66% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 582 0.33% 98.98% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 998 0.56% 99.54% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 86250 48.50% 48.50% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 44177 24.84% 73.34% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 6214 3.49% 76.84% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 8561 4.81% 81.65% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1535 0.86% 82.51% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 28697 16.14% 98.65% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 590 0.33% 98.98% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 996 0.56% 99.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 177951 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 272332 # Number of instructions committed
-system.cpu3.commit.committedOps 272332 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 177833 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 248929 # Number of instructions committed
+system.cpu3.commit.committedOps 248929 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 115503 # Number of memory references committed
-system.cpu3.commit.loads 78841 # Number of loads committed
-system.cpu3.commit.membars 6036 # Number of memory barriers committed
-system.cpu3.commit.branches 48661 # Number of branches committed
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+system.cpu3.commit.membars 6986 # Number of memory barriers committed
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system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 186284 # Number of committed integer instructions.
+system.cpu3.commit.int_insts 170050 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads 463264 # The number of ROB reads
-system.cpu3.rob.rob_writes 576197 # The number of ROB writes
-system.cpu3.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 3296 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 37130 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 226846 # Number of Instructions Simulated
-system.cpu3.committedOps 226846 # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total 226846 # Number of Instructions Simulated
-system.cpu3.cpi 0.840888 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.840888 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.189220 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.189220 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 413495 # number of integer regfile reads
-system.cpu3.int_regfile_writes 192863 # number of integer regfile writes
+system.cpu3.rob.rob_reads 439993 # The number of ROB reads
+system.cpu3.rob.rob_writes 529937 # The number of ROB writes
+system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 3374 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 37090 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 206079 # Number of Instructions Simulated
+system.cpu3.committedOps 206079 # Number of Ops (including micro ops) Simulated
+system.cpu3.committedInsts_total 206079 # Number of Instructions Simulated
+system.cpu3.cpi 0.925519 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 0.925519 # CPI: Total CPI of All Threads
+system.cpu3.ipc 1.080475 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 1.080475 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 375615 # number of integer regfile reads
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system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu3.misc_regfile_reads 119579 # number of misc regfile reads
+system.cpu3.misc_regfile_reads 106918 # number of misc regfile reads
system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
system.cpu3.icache.replacements 323 # number of replacements
-system.cpu3.icache.tagsinuse 88.254899 # Cycle average of tags in use
-system.cpu3.icache.total_refs 21999 # Total number of references to valid blocks.
+system.cpu3.icache.tagsinuse 88.249587 # Cycle average of tags in use
+system.cpu3.icache.total_refs 23982 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 439 # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs 50.111617 # Average number of references to valid blocks.
+system.cpu3.icache.avg_refs 54.628702 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst 88.254899 # Average occupied blocks per requestor
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-system.cpu3.icache.occ_percent::total 0.172373 # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst 21999 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 21999 # number of ReadReq hits
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-system.cpu3.icache.demand_hits::total 21999 # number of demand (read+write) hits
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-system.cpu3.icache.overall_hits::total 21999 # number of overall hits
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-system.cpu3.icache.ReadReq_misses::total 504 # number of ReadReq misses
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-system.cpu3.icache.demand_misses::total 504 # number of demand (read+write) misses
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-system.cpu3.icache.overall_misses::total 504 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7701000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total 7701000 # number of ReadReq miss cycles
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-system.cpu3.icache.demand_miss_latency::total 7701000 # number of demand (read+write) miss cycles
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-system.cpu3.icache.overall_miss_latency::total 7701000 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 22503 # number of ReadReq accesses(hits+misses)
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-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15279.761905 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 15279.761905 # average ReadReq miss latency
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-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15279.761905 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 15279.761905 # average overall miss latency
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system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1805,106 +1804,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
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-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12933.940774 # average overall mshr miss latency
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system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 0 # number of replacements
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system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
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system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1913,81 +1912,81 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.l2c.overall_avg_miss_latency::cpu2.inst 44900 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 55038.461538 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 48500 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 48250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 54692.230769 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53574.154185 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53554.410294 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -2215,7 +2214,7 @@ system.l2c.overall_mshr_hits::cpu1.inst 2 # nu
system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 362 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 84 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
@@ -2223,18 +2222,18 @@ system.l2c.ReadReq_mshr_misses::cpu2.inst 5 # n
system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 541 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 540 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 20 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 75 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 362 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 84 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
@@ -2242,8 +2241,8 @@ system.l2c.demand_mshr_misses::cpu2.inst 5 # nu
system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 672 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses
+system.l2c.demand_mshr_misses::total 671 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 362 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 84 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
@@ -2251,45 +2250,45 @@ system.l2c.overall_mshr_misses::cpu2.inst 5 # n
system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 672 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14840000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3282500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3420000 # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::total 671 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14801500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3274000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3420500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 291500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 200000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 240000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 22354000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 22307500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 800000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 840000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 844000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 765000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 3009000 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4019000 # number of ReadExReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 605000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 3089000 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4012500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 516500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5640500 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 14840000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 7301500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 3420000 # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5634000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 14801500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 7286500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 3420500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 885000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 200000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 556500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 240000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 551500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 27994500 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 14840000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 7301500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 3420000 # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 27941500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 14801500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 7286500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 3420500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 885000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 200000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 556500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 240000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 551500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 27994500 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.602990 # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_miss_latency::total 27941500 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
@@ -2297,18 +2296,18 @@ system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011416
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.266502 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.266930 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.869565 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.962500 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.602990 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
@@ -2316,8 +2315,8 @@ system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011416 #
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.310967 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.602990 # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::total 0.311513 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
@@ -2325,44 +2324,44 @@ system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011416
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.310967 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44358.108108 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_rate::total 0.311513 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44243.243243 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 41319.778189 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 41310.185185 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40263.157895 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40120 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42755.319149 # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40333.333333 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40116.883117 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42686.170213 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42625 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 43057.251908 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43461.309524 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 43007.633588 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43372.023810 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 41658.482143 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43461.309524 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43372.023810 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 41658.482143 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index f048ede7e..85ad1df6b 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -465,8 +465,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.l2c.mem_side system.system_port
[system.physmem]
@@ -487,7 +487,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 4b3a2eb90..77c22c008 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:54:10
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:36
gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
@@ -79,4 +79,4 @@ Iteration 9 completed
[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
Iteration 10 completed
PASSED :-)
-Exiting @ tick 87713500 because target called exit()
+Exiting @ tick 87707000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 382c1c71b..a86401b30 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000088 # Number of seconds simulated
-sim_ticks 87713500 # Number of ticks simulated
-final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 87707000 # Number of ticks simulated
+final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1588944 # Simulator instruction rate (inst/s)
-host_op_rate 1588869 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 205745598 # Simulator tick rate (ticks/s)
-host_mem_usage 1148436 # Number of bytes of host memory used
-host_seconds 0.43 # Real time elapsed on the host
-sim_insts 677340 # Number of instructions simulated
-sim_ops 677340 # Number of ops (including micro ops) simulated
+host_inst_rate 1518076 # Simulator instruction rate (inst/s)
+host_op_rate 1518015 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 196560583 # Simulator tick rate (ticks/s)
+host_mem_usage 1157868 # Number of bytes of host memory used
+host_seconds 0.45 # Real time elapsed on the host
+sim_insts 677327 # Number of instructions simulated
+sim_ops 677327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
@@ -34,85 +34,85 @@ system.physmem.num_reads::cpu2.data 13 # Nu
system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 205760801 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 120391958 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 45238190 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 14592965 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 1459296 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 9485427 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 1459296 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 9485427 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 407873360 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 205760801 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 45238190 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 1459296 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 1459296 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 253917584 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 205760801 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 120391958 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 45238190 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 14592965 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 1459296 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 9485427 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 1459296 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 9485427 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 407873360 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 175428 # number of cpu cycles simulated
+system.cpu0.numCycles 175415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 175339 # Number of instructions committed
-system.cpu0.committedOps 175339 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses
+system.cpu0.committedInsts 175326 # Number of instructions committed
+system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 28825 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 120388 # number of integer instructions
+system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 120376 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 349308 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 121996 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 82398 # number of memory refs
-system.cpu0.num_load_insts 54592 # Number of load instructions
+system.cpu0.num_mem_refs 82397 # number of memory refs
+system.cpu0.num_load_insts 54591 # Number of load instructions
system.cpu0.num_store_insts 27806 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 175428 # Number of busy cycles
+system.cpu0.num_busy_cycles 175415 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 215 # number of replacements
-system.cpu0.icache.tagsinuse 222.757301 # Cycle average of tags in use
-system.cpu0.icache.total_refs 174934 # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use
+system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 222.757301 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.435073 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.435073 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 174934 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 174934 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 174934 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 174934 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 174934 # number of overall hits
-system.cpu0.icache.overall_hits::total 174934 # number of overall hits
+system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
+system.cpu0.icache.overall_hits::total 174921 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
system.cpu0.icache.overall_misses::total 467 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 175401 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 175401 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 175401 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 175401 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.002662 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.002662 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.002662 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -123,24 +123,24 @@ system.cpu0.icache.fast_writes 0 # nu
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 2 # number of replacements
-system.cpu0.dcache.tagsinuse 150.735434 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 81884 # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 490.323353 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 150.735434 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.294405 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.294405 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 82009 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 82009 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 82009 # number of overall hits
-system.cpu0.dcache.overall_hits::total 82009 # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
+system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
@@ -151,18 +151,18 @@ system.cpu0.dcache.demand_misses::cpu0.data 328 #
system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
system.cpu0.dcache.overall_misses::total 328 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 54582 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 54582 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 82337 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 82337 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.002766 # miss rate for ReadReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
@@ -182,7 +182,7 @@ system.cpu0.dcache.cache_copies 0 # nu
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 173308 # number of cpu cycles simulated
+system.cpu1.numCycles 173295 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 167398 # Number of instructions committed
@@ -200,19 +200,19 @@ system.cpu1.num_fp_register_writes 0 # nu
system.cpu1.num_mem_refs 53394 # number of memory refs
system.cpu1.num_load_insts 40652 # Number of load instructions
system.cpu1.num_store_insts 12742 # Number of store instructions
-system.cpu1.num_idle_cycles 7886.574443 # Number of idle cycles
-system.cpu1.num_busy_cycles 165421.425557 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.954494 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.045506 # Percentage of idle cycles
+system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles
+system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
system.cpu1.icache.replacements 278 # number of replacements
-system.cpu1.icache.tagsinuse 76.746014 # Cycle average of tags in use
+system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use
system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 76.746014 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.149895 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.149895 # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
@@ -247,14 +247,14 @@ system.cpu1.icache.fast_writes 0 # nu
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 0 # number of replacements
-system.cpu1.dcache.tagsinuse 30.314752 # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use
system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 30.314752 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.059208 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.059208 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
@@ -304,7 +304,7 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets nan
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.numCycles 173308 # number of cpu cycles simulated
+system.cpu2.numCycles 173295 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 167334 # Number of instructions committed
@@ -322,19 +322,19 @@ system.cpu2.num_fp_register_writes 0 # nu
system.cpu2.num_mem_refs 58537 # number of memory refs
system.cpu2.num_load_insts 42362 # Number of load instructions
system.cpu2.num_store_insts 16175 # Number of store instructions
-system.cpu2.num_idle_cycles 7949.801380 # Number of idle cycles
-system.cpu2.num_busy_cycles 165358.198620 # Number of busy cycles
-system.cpu2.not_idle_fraction 0.954129 # Percentage of non-idle cycles
-system.cpu2.idle_fraction 0.045871 # Percentage of idle cycles
+system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles
+system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles
+system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
+system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
system.cpu2.icache.replacements 278 # number of replacements
-system.cpu2.icache.tagsinuse 74.775474 # Cycle average of tags in use
+system.cpu2.icache.tagsinuse 74.781015 # Cycle average of tags in use
system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst 74.775474 # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst 0.146046 # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total 0.146046 # Average percentage of cache occupancy
+system.cpu2.icache.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total 0.146057 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
@@ -369,14 +369,14 @@ system.cpu2.icache.fast_writes 0 # nu
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 0 # number of replacements
-system.cpu2.dcache.tagsinuse 29.603311 # Cycle average of tags in use
+system.cpu2.dcache.tagsinuse 29.605505 # Cycle average of tags in use
system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data 29.603311 # Average occupied blocks per requestor
-system.cpu2.dcache.occ_percent::cpu2.data 0.057819 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::total 0.057819 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total 0.057823 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits
@@ -426,7 +426,7 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets nan
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.numCycles 173307 # number of cpu cycles simulated
+system.cpu3.numCycles 173294 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.committedInsts 167269 # Number of instructions committed
@@ -444,19 +444,19 @@ system.cpu3.num_fp_register_writes 0 # nu
system.cpu3.num_mem_refs 55900 # number of memory refs
system.cpu3.num_load_insts 41466 # Number of load instructions
system.cpu3.num_store_insts 14434 # Number of store instructions
-system.cpu3.num_idle_cycles 8013.969997 # Number of idle cycles
-system.cpu3.num_busy_cycles 165293.030003 # Number of busy cycles
-system.cpu3.not_idle_fraction 0.953759 # Percentage of non-idle cycles
-system.cpu3.idle_fraction 0.046241 # Percentage of idle cycles
+system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles
+system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles
+system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles
+system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles
system.cpu3.icache.replacements 279 # number of replacements
-system.cpu3.icache.tagsinuse 72.869097 # Cycle average of tags in use
+system.cpu3.icache.tagsinuse 72.874497 # Cycle average of tags in use
system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst 72.869097 # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst 0.142322 # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total 0.142322 # Average percentage of cache occupancy
+system.cpu3.icache.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total 0.142333 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
@@ -491,14 +491,14 @@ system.cpu3.icache.fast_writes 0 # nu
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 0 # number of replacements
-system.cpu3.dcache.tagsinuse 28.793270 # Cycle average of tags in use
+system.cpu3.dcache.tagsinuse 28.795404 # Cycle average of tags in use
system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data 28.793270 # Average occupied blocks per requestor
-system.cpu3.dcache.occ_percent::cpu3.data 0.056237 # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::total 0.056237 # Average percentage of cache occupancy
+system.cpu3.dcache.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total 0.056241 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
@@ -549,20 +549,20 @@ system.cpu3.dcache.fast_writes 0 # nu
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
-system.l2c.tagsinuse 366.557230 # Cycle average of tags in use
+system.l2c.tagsinuse 366.582542 # Cycle average of tags in use
system.l2c.total_refs 1220 # Total number of references to valid blocks.
system.l2c.sampled_refs 421 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.897862 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 0.966368 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 6.720647 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst 1.930518 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
@@ -572,7 +572,7 @@ system.l2c.occ_percent::cpu2.inst 0.000029 # Av
system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.005593 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.005594 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 55888365a..636fc646c 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -450,7 +450,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.l2c.mem_side system.system_port
[system.physmem]
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index 900805018..d61ea072e 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:54:18
-gem5 started Jul 2 2012 11:32:06
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:39
gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
@@ -79,4 +79,4 @@ Iteration 9 completed
[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
Iteration 10 completed
PASSED :-)
-Exiting @ tick 268912000 because target called exit()
+Exiting @ tick 268898000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index ea05c2e9c..1523ab302 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000269 # Number of seconds simulated
-sim_ticks 268912000 # Number of ticks simulated
-final_tick 268912000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 268898000 # Number of ticks simulated
+final_tick 268898000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 548575 # Simulator instruction rate (inst/s)
-host_op_rate 548567 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 220132321 # Simulator tick rate (ticks/s)
-host_mem_usage 230896 # Number of bytes of host memory used
-host_seconds 1.22 # Real time elapsed on the host
-sim_insts 670117 # Number of instructions simulated
-sim_ops 670117 # Number of ops (including micro ops) simulated
+host_inst_rate 1131883 # Simulator instruction rate (inst/s)
+host_op_rate 1131850 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 454173870 # Simulator tick rate (ticks/s)
+host_mem_usage 240368 # Number of bytes of host memory used
+host_seconds 0.59 # Real time elapsed on the host
+sim_insts 670104 # Number of instructions simulated
+sim_ops 670104 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory
@@ -34,67 +34,67 @@ system.physmem.num_reads::cpu2.data 15 # Nu
system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory
system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 67828881 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39269352 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 14041768 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 5235914 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 475992 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 3569941 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 1903969 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 3807937 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 136133754 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 67828881 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 14041768 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 475992 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 1903969 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 84250610 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 67828881 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39269352 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 14041768 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 5235914 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 475992 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 3569941 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 1903969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 3807937 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 136133754 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 67832412 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 39271397 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 14042499 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 5236186 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 476017 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 3570127 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 1904068 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 3808135 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 136140842 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 67832412 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 14042499 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 476017 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 1904068 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 84254996 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 67832412 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 39271397 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 14042499 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 5236186 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 476017 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 3570127 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 1904068 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 3808135 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 136140842 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 537824 # number of cpu cycles simulated
+system.cpu0.numCycles 537796 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 160927 # Number of instructions committed
-system.cpu0.committedOps 160927 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 110780 # Number of integer alu accesses
+system.cpu0.committedInsts 160914 # Number of instructions committed
+system.cpu0.committedOps 160914 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 110768 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 26423 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 110780 # number of integer instructions
+system.cpu0.num_conditional_control_insts 26422 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 110768 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 320484 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 112387 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 320462 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 112374 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 75192 # number of memory refs
-system.cpu0.num_load_insts 49788 # Number of load instructions
+system.cpu0.num_mem_refs 75191 # number of memory refs
+system.cpu0.num_load_insts 49787 # Number of load instructions
system.cpu0.num_store_insts 25404 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 537824 # Number of busy cycles
+system.cpu0.num_busy_cycles 537796 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 215 # number of replacements
-system.cpu0.icache.tagsinuse 212.253377 # Cycle average of tags in use
-system.cpu0.icache.total_refs 160523 # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse 212.263647 # Cycle average of tags in use
+system.cpu0.icache.total_refs 160510 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 343.732334 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 343.704497 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 212.253377 # Average occupied blocks per requestor
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-system.cpu0.icache.occ_percent::total 0.414557 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 160523 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 160523 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 160523 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 160523 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 160523 # number of overall hits
-system.cpu0.icache.overall_hits::total 160523 # number of overall hits
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system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
@@ -107,12 +107,12 @@ system.cpu0.icache.demand_miss_latency::cpu0.inst 18554000
system.cpu0.icache.demand_miss_latency::total 18554000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 18554000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 18554000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 160990 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 160990 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 160990 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 160990 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 160990 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 160990 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 160977 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 160977 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 160977 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 160977 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 160977 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 160977 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002901 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.002901 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002901 # miss rate for demand accesses
@@ -159,24 +159,24 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719
system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 2 # number of replacements
-system.cpu0.dcache.tagsinuse 145.513886 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 74668 # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse 145.520681 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 74667 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 447.113772 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 447.107784 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 145.513886 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.284207 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.284207 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 49616 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 49616 # number of ReadReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data 145.520681 # Average occupied blocks per requestor
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system.cpu0.dcache.WriteReq_hits::cpu0.data 25170 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 25170 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 74786 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 74786 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 74786 # number of overall hits
-system.cpu0.dcache.overall_hits::total 74786 # number of overall hits
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+system.cpu0.dcache.demand_hits::total 74785 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 74785 # number of overall hits
+system.cpu0.dcache.overall_hits::total 74785 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
@@ -197,18 +197,18 @@ system.cpu0.dcache.demand_miss_latency::cpu0.data 12481000
system.cpu0.dcache.demand_miss_latency::total 12481000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 12481000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 12481000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 49778 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 49778 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 49777 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 49777 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 25353 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 25353 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 75131 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 75131 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 75131 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 75131 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003254 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.003254 # miss rate for ReadReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 75130 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 75130 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 75130 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 75130 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003255 # miss rate for ReadReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007218 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.007218 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
@@ -257,8 +257,8 @@ system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11445001
system.cpu0.dcache.demand_mshr_miss_latency::total 11445001 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11445001 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 11445001 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003254 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003254 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003255 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003255 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007218 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007218 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
@@ -278,7 +278,7 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 537824 # number of cpu cycles simulated
+system.cpu1.numCycles 537796 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 159902 # Number of instructions committed
@@ -296,19 +296,19 @@ system.cpu1.num_fp_register_writes 0 # nu
system.cpu1.num_mem_refs 64016 # number of memory refs
system.cpu1.num_load_insts 42937 # Number of load instructions
system.cpu1.num_store_insts 21079 # Number of store instructions
-system.cpu1.num_idle_cycles 71606.001734 # Number of idle cycles
+system.cpu1.num_idle_cycles 71578.001734 # Number of idle cycles
system.cpu1.num_busy_cycles 466217.998266 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.866860 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.133140 # Percentage of idle cycles
+system.cpu1.not_idle_fraction 0.866905 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.133095 # Percentage of idle cycles
system.cpu1.icache.replacements 280 # number of replacements
-system.cpu1.icache.tagsinuse 69.902178 # Cycle average of tags in use
+system.cpu1.icache.tagsinuse 69.905818 # Cycle average of tags in use
system.cpu1.icache.total_refs 159569 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 435.980874 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.icache.occ_percent::total 0.136528 # Average percentage of cache occupancy
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system.cpu1.icache.ReadReq_hits::cpu1.inst 159569 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 159569 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 159569 # number of demand (read+write) hits
@@ -379,14 +379,14 @@ system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18814.207650
system.cpu1.icache.overall_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 0 # number of replacements
-system.cpu1.dcache.tagsinuse 27.730072 # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse 27.731515 # Cycle average of tags in use
system.cpu1.dcache.total_refs 44449 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 1532.724138 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 27.730072 # Average occupied blocks per requestor
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-system.cpu1.dcache.occ_percent::total 0.054160 # Average percentage of cache occupancy
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system.cpu1.dcache.ReadReq_hits::cpu1.data 42776 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 42776 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 20903 # number of WriteReq hits
@@ -496,7 +496,7 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18000.003861
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.numCycles 537824 # number of cpu cycles simulated
+system.cpu2.numCycles 537796 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 177221 # Number of instructions committed
@@ -514,19 +514,19 @@ system.cpu2.num_fp_register_writes 0 # nu
system.cpu2.num_mem_refs 47896 # number of memory refs
system.cpu2.num_load_insts 40447 # Number of load instructions
system.cpu2.num_store_insts 7449 # Number of store instructions
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+system.cpu2.num_idle_cycles 71854.001733 # Number of idle cycles
system.cpu2.num_busy_cycles 465941.998267 # Number of busy cycles
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-system.cpu2.idle_fraction 0.133653 # Percentage of idle cycles
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system.cpu2.icache.replacements 281 # number of replacements
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+system.cpu2.icache.tagsinuse 67.534984 # Cycle average of tags in use
system.cpu2.icache.total_refs 176887 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 481.980926 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.icache.occ_percent::total 0.131897 # Average percentage of cache occupancy
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system.cpu2.icache.ReadReq_hits::cpu2.inst 176887 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 176887 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 176887 # number of demand (read+write) hits
@@ -597,14 +597,14 @@ system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 0 # number of replacements
-system.cpu2.dcache.tagsinuse 26.637011 # Cycle average of tags in use
+system.cpu2.dcache.tagsinuse 26.638398 # Cycle average of tags in use
system.cpu2.dcache.total_refs 17171 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 592.103448 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.dcache.occ_percent::total 0.052025 # Average percentage of cache occupancy
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system.cpu2.dcache.ReadReq_hits::cpu2.data 40266 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 40266 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 7273 # number of WriteReq hits
@@ -714,7 +714,7 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.numCycles 537824 # number of cpu cycles simulated
+system.cpu3.numCycles 537796 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.committedInsts 172067 # Number of instructions committed
@@ -732,19 +732,19 @@ system.cpu3.num_fp_register_writes 0 # nu
system.cpu3.num_mem_refs 52937 # number of memory refs
system.cpu3.num_load_insts 41268 # Number of load instructions
system.cpu3.num_store_insts 11669 # Number of store instructions
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+system.cpu3.num_idle_cycles 72130.001732 # Number of idle cycles
system.cpu3.num_busy_cycles 465665.998268 # Number of busy cycles
-system.cpu3.not_idle_fraction 0.865833 # Percentage of non-idle cycles
-system.cpu3.idle_fraction 0.134167 # Percentage of idle cycles
+system.cpu3.not_idle_fraction 0.865879 # Percentage of non-idle cycles
+system.cpu3.idle_fraction 0.134121 # Percentage of idle cycles
system.cpu3.icache.replacements 280 # number of replacements
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+system.cpu3.icache.tagsinuse 65.345482 # Cycle average of tags in use
system.cpu3.icache.total_refs 171734 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 469.218579 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.icache.occ_percent::total 0.127621 # Average percentage of cache occupancy
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system.cpu3.icache.ReadReq_hits::cpu3.inst 171734 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 171734 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 171734 # number of demand (read+write) hits
@@ -815,14 +815,14 @@ system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12423.497268
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 0 # number of replacements
-system.cpu3.dcache.tagsinuse 25.848817 # Cycle average of tags in use
+system.cpu3.dcache.tagsinuse 25.850163 # Cycle average of tags in use
system.cpu3.dcache.total_refs 25744 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 858.133333 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data 25.848817 # Average occupied blocks per requestor
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-system.cpu3.dcache.occ_percent::total 0.050486 # Average percentage of cache occupancy
+system.cpu3.dcache.occ_blocks::cpu3.data 25.850163 # Average occupied blocks per requestor
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+system.cpu3.dcache.occ_percent::total 0.050489 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 41084 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 41084 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 11491 # number of WriteReq hits
@@ -933,20 +933,20 @@ system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 19284.697509
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 19284.697509 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
-system.l2c.tagsinuse 348.808930 # Cycle average of tags in use
+system.l2c.tagsinuse 348.825789 # Cycle average of tags in use
system.l2c.total_refs 1221 # Total number of references to valid blocks.
system.l2c.sampled_refs 429 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.846154 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 0.888060 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 231.678051 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 54.187452 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 51.469392 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 6.113383 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst 1.770981 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data 0.842116 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst 1.030371 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data 0.829126 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 0.888106 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 231.689332 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 54.189752 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 51.472071 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 6.113701 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst 1.771073 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data 0.842159 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst 1.030424 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data 0.829169 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.003535 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy
@@ -956,7 +956,7 @@ system.l2c.occ_percent::cpu2.inst 0.000027 # Av
system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.005322 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.005323 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits