SE/FS: Make both SE and FS tests available all the time.

--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
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rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
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rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py

18 files changed, 7783 insertions, 0 deletions

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
new file mode 100644
index 000000000..eb497bb90
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -0,0 +1,1828 @@
+[root]
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+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
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+
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+
+[system.cpu3.itb]
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+
+[system.cpu3.tracer]
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+
+[system.l2c]
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+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[0]
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.mem_side system.physmem.port[0] system.system_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
new file mode 100755
index 000000000..0491d5141
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -0,0 +1,82 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:31
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Init done
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 1 completed
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 2 completed
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+Iteration 3 completed
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 4 completed
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 5 completed
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 6 completed
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 7 completed
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 8 completed
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
+Iteration 9 completed
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+Iteration 10 completed
+PASSED :-)
+Exiting @ tick 104317500 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
new file mode 100644
index 000000000..191a42060
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -0,0 +1,1813 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000104                       # Number of seconds simulated
+sim_ticks                                   104317500                       # Number of ticks simulated
+final_tick                                  104317500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 132902                       # Simulator instruction rate (inst/s)
+host_tick_rate                               13605540                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226920                       # Number of bytes of host memory used
+host_seconds                                     7.67                       # Real time elapsed on the host
+sim_insts                                     1018993                       # Number of instructions simulated
+system.physmem.bytes_read                       41984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  28224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          656                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      402463633                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 270558631                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     402463633                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu0.workload.num_syscalls                  89                       # Number of system calls
+system.cpu0.numCycles                          208636                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.BPredUnit.lookups                   80640                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted             78657                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect              1043                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups                79781                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                   77332                       # Number of BTB hits
+system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.BPredUnit.usedRAS                     408                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles             16565                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        478922                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      80640                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             77740                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       158137                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                   3216                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles                 12889                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles         1227                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines                     5515                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes                  447                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples            190846                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.509468                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.192643                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   32709     17.14%     17.14% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   78517     41.14%     58.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     548      0.29%     58.57% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                     994      0.52%     59.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     666      0.35%     59.44% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   74596     39.09%     98.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     801      0.42%     98.94% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     243      0.13%     99.07% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    1772      0.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total              190846                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.386510                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.295491                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   16943                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                14345                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   157232                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  303                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                  2023                       # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts                476750                       # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles                  2023                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                   17547                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                   1397                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         12300                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   156956                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                  623                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                474177                       # Number of instructions processed by rename
+system.cpu0.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents                  220                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands             323986                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups               945682                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups          945682                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               313636                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   10350                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts               803                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts           824                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                     3595                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              152097                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              76745                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            74317                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           74189                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    396725                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded                846                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                   395036                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued               98                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined           8285                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined         7136                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved           287                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples       190846                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.069920                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.087146                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              31787     16.66%     16.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               5152      2.70%     19.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              75953     39.80%     59.15% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              75299     39.46%     98.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1582      0.83%     99.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                772      0.40%     99.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                222      0.12%     99.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7                 71      0.04%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                  8      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         190846                       # Number of insts issued each cycle
+system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     35     14.96%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                    80     34.19%     49.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  119     50.85%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               166893     42.25%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              151805     38.43%     80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              76338     19.32%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::total                395036                       # Type of FU issued
+system.cpu0.iq.rate                          1.893422                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        234                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000592                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads            981250                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           405901                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       393576                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses                395270                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads           73924                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.squashedLoads         1695                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation           45                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores         1038                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu0.iew.iewSquashCycles                  2023                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                   1027                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   29                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             472373                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              357                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               152097                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               76745                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts               745                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                    27                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents            45                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect           467                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect          734                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts                1201                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts               394155                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               151500                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts              881                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu0.iew.exec_nop                        74802                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      227728                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   78432                       # Number of branches executed
+system.cpu0.iew.exec_stores                     76228                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.889199                       # Inst execution rate
+system.cpu0.iew.wb_sent                        393836                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       393576                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   233255                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   235364                       # num instructions consuming a value
+system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.wb_rate                      1.886424                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.991039                       # average fanout of values written-back
+system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.commit.commitCommittedInsts        462799                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts           9535                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts             1043                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples       188840                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.450747                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.135046                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        32333     17.12%     17.12% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        78258     41.44%     58.56% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         2188      1.16%     59.72% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          719      0.38%     60.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          659      0.35%     60.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        73614     38.98%     99.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          485      0.26%     99.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          280      0.15%     99.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          304      0.16%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total       188840                       # Number of insts commited each cycle
+system.cpu0.commit.count                       462799                       # Number of instructions committed
+system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu0.commit.refs                        226109                       # Number of memory references committed
+system.cpu0.commit.loads                       150402                       # Number of loads committed
+system.cpu0.commit.membars                         84                       # Number of memory barriers committed
+system.cpu0.commit.branches                     77595                       # Number of branches committed
+system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                   311966                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events                  304                       # number cycles where commit BW limit reached
+system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu0.rob.rob_reads                      659709                       # The number of ROB reads
+system.cpu0.rob.rob_writes                     946703                       # The number of ROB writes
+system.cpu0.timesIdled                            320                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                          17790                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     388389                       # Number of Instructions Simulated
+system.cpu0.committedInsts_total               388389                       # Number of Instructions Simulated
+system.cpu0.cpi                              0.537183                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.537183                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.861563                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.861563                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  705230                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 317935                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
+system.cpu0.misc_regfile_reads                 229503                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
+system.cpu0.icache.replacements                   294                       # number of replacements
+system.cpu0.icache.tagsinuse               244.353680                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                    4810                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                   581                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  8.278830                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0           244.353680                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.477253                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits                  4810                       # number of ReadReq hits
+system.cpu0.icache.demand_hits                   4810                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits                  4810                       # number of overall hits
+system.cpu0.icache.ReadReq_misses                 705                       # number of ReadReq misses
+system.cpu0.icache.demand_misses                  705                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses                 705                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency      27622000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency       27622000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency      27622000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses              5515                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses               5515                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses              5515                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate         0.127833                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate          0.127833                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate         0.127833                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency 39180.141844                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency 39180.141844                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency 39180.141844                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        15500                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs        15500                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks                       0                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits              123                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits               123                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits              123                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses            582                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses             582                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses            582                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency     21369000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency     21369000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency     21369000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate     0.105530                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate     0.105530                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate     0.105530                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36716.494845                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 36716.494845                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 36716.494845                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements                     9                       # number of replacements
+system.cpu0.dcache.tagsinuse               138.901719                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                   97328                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                   174                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                559.356322                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::0           140.432794                       # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1            -1.531076                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.274283                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::1           -0.002990                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits                 77005                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits                75125                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits                    23                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits                 152130                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits                152130                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses                 517                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses                540                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses                  19                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses                 1057                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses                1057                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency      14734500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency     24692984                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency        371000                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency       39427484                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency      39427484                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses             77522                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses            75665                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses             153187                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses            153187                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate         0.006669                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate        0.007137                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate         0.452381                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate          0.006900                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate         0.006900                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency        28500                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency 45727.748148                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency 19526.315789                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency 37301.309366                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency 37301.309366                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       180500                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8595.238095                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks                       6                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits              327                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits             368                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits               695                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits              695                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses            190                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses           172                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses             19                       # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses             362                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses            362                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency      5255000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency      6251500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency       314000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency     11506500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency     11506500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate     0.002451                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate     0.002273                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate     0.452381                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate     0.002363                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate     0.002363                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27657.894737                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36345.930233                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16526.315789                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 31785.911602                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 31785.911602                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.numCycles                          174305                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.BPredUnit.lookups                   52112                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted             49475                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect              1085                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups                48064                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                   46080                       # Number of BTB hits
+system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.BPredUnit.usedRAS                     697                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles             26834                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        291745                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      52112                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             46777                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                       102740                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   3160                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles                 32953                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.NoActiveThreadStallCycles         6397                       # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.PendingTrapStallCycles          670                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines                    18341                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                  181                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples            171598                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.700166                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.136223                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   68858     40.13%     40.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   52177     30.41%     70.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    5705      3.32%     73.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3354      1.95%     75.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     589      0.34%     76.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   36153     21.07%     97.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1352      0.79%     98.01% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                     417      0.24%     98.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    2993      1.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total              171598                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.298970                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.673762                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   31662                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                29517                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    97194                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 4829                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  1999                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                288983                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  1999                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   32299                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  14957                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         13738                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                    92834                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                 9374                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                287085                       # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents                    26                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents                   60                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands             200836                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               551958                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          551958                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               191192                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                    9644                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts              1080                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1209                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    11997                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               82183                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              38955                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            39306                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           34408                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    238857                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               6064                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   241490                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined           8361                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined         7490                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved           637                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       171598                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.407301                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.310079                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              65840     38.37%     38.37% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              21732     12.66%     51.03% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              38892     22.66%     73.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              40381     23.53%     97.23% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3339      1.95%     99.18% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1157      0.67%     99.85% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                163      0.09%     99.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                 40      0.02%     99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8                 54      0.03%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         171598                       # Number of insts issued each cycle
+system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                     12      4.55%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    62     23.48%     28.03% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  190     71.97%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               116592     48.28%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               86338     35.75%     84.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              38560     15.97%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::total                241490                       # Type of FU issued
+system.cpu1.iq.rate                          1.385445                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                        264                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.001093                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            654845                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           253312                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       240391                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses                241754                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           34276                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.squashedLoads         1784                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation           30                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores          861                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu1.iew.iewSquashCycles                  1999                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                   1765                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                   48                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             285210                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              302                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                82183                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               38955                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts              1043                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                    45                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents            30                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect           599                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect          655                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                1254                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               240751                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                81429                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts              739                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu1.iew.exec_nop                        40289                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      119949                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   49362                       # Number of branches executed
+system.cpu1.iew.exec_stores                     38520                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.381205                       # Inst execution rate
+system.cpu1.iew.wb_sent                        240558                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       240391                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   136702                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   141193                       # num instructions consuming a value
+system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.wb_rate                      1.379140                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.968192                       # average fanout of values written-back
+system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.commit.commitCommittedInsts        275667                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts           9533                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           5427                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             1085                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       163203                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.689105                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     2.043033                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        64641     39.61%     39.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        47587     29.16%     68.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         5957      3.65%     72.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         6309      3.87%     76.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1571      0.96%     77.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        34602     21.20%     98.45% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          646      0.40%     98.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7         1051      0.64%     99.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8          839      0.51%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::total       163203                       # Number of insts commited each cycle
+system.cpu1.commit.count                       275667                       # Number of instructions committed
+system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu1.commit.refs                        118493                       # Number of memory references committed
+system.cpu1.commit.loads                        80399                       # Number of loads committed
+system.cpu1.commit.membars                       4716                       # Number of memory barriers committed
+system.cpu1.commit.branches                     48773                       # Number of branches committed
+system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                   189391                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events                  839                       # number cycles where commit BW limit reached
+system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu1.rob.rob_reads                      446977                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     572400                       # The number of ROB writes
+system.cpu1.timesIdled                            225                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                           2707                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                       34329                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                     231385                       # Number of Instructions Simulated
+system.cpu1.committedInsts_total               231385                       # Number of Instructions Simulated
+system.cpu1.cpi                              0.753312                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.753312                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.327472                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.327472                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  418065                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 194844                       # number of integer regfile writes
+system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 121500                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
+system.cpu1.icache.replacements                   317                       # number of replacements
+system.cpu1.icache.tagsinuse                84.541118                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                   17870                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                   427                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 41.850117                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::0            84.541118                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.165119                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits                 17870                       # number of ReadReq hits
+system.cpu1.icache.demand_hits                  17870                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits                 17870                       # number of overall hits
+system.cpu1.icache.ReadReq_misses                 471                       # number of ReadReq misses
+system.cpu1.icache.demand_misses                  471                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses                 471                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency       7203000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency        7203000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency       7203000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses             18341                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses              18341                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses             18341                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate         0.025680                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate          0.025680                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate         0.025680                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency 15292.993631                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency 15292.993631                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency 15292.993631                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks                       0                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits               44                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits                44                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits               44                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses            427                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses             427                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses            427                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency      5374000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency      5374000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency      5374000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate     0.023281                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate     0.023281                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate     0.023281                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12585.480094                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 12585.480094                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 12585.480094                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.replacements                     2                       # number of replacements
+system.cpu1.dcache.tagsinuse                18.588243                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                   44082                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs               1469.400000                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0            24.401572                       # Average occupied blocks per context
+system.cpu1.dcache.occ_blocks::1            -5.813330                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.047659                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::1           -0.011354                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits                 46660                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits                37905                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits                    13                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits                  84565                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits                 84565                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses                 478                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses                124                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses                  52                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses                  602                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses                 602                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency      10261500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency      2943000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency       1149500                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency       13204500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency      13204500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses             47138                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses            38029                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses                65                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses              85167                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses             85167                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate         0.010140                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate        0.003261                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate         0.800000                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate          0.007068                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate         0.007068                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency 21467.573222                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency 23733.870968                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency 22105.769231                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency 21934.385382                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency 21934.385382                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks                       1                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits              323                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits               341                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits              341                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses            155                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses           106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses             52                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses             261                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses            261                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency      2079000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency      1617000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency       993500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency      3696000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency      3696000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate     0.003288                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate     0.002787                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate     0.800000                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate     0.003065                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate     0.003065                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13412.903226                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15254.716981                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19105.769231                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 14160.919540                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 14160.919540                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.numCycles                          174018                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.BPredUnit.lookups                   49365                       # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted             46733                       # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect              1149                       # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups                45641                       # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits                   43566                       # Number of BTB hits
+system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.BPredUnit.usedRAS                     657                       # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
+system.cpu2.fetch.icacheStallCycles             27807                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        273933                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      49365                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             44223                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                        97490                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   3286                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles                 34440                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.NoActiveThreadStallCycles         6393                       # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles          776                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines                    19059                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  204                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            168970                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.621193                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.105353                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   71480     42.30%     42.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   49528     29.31%     71.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                    6067      3.59%     75.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3620      2.14%     77.35% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                     727      0.43%     77.78% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   32913     19.48%     97.26% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1356      0.80%     98.06% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                     430      0.25%     98.31% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    2849      1.69%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total              168970                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.283678                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.574165                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   32851                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                30938                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                    91697                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 5032                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  2059                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                271122                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  2059                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   33552                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  15710                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         14412                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                    87163                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                 9681                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                268918                       # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents                    31                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents                   44                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands             188425                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               514118                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          514118                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               178130                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   10295                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1067                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1200                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    12339                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               75827                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              35627                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            36245                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           31070                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    223191                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded               6330                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   225872                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined           8710                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined         8050                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved           644                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples       168970                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.336758                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.306399                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              68735     40.68%     40.68% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              22585     13.37%     54.05% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              35942     21.27%     75.32% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              37104     21.96%     97.28% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3355      1.99%     99.26% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5                981      0.58%     99.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                168      0.10%     99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                 42      0.02%     99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8                 58      0.03%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         168970                       # Number of insts issued each cycle
+system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     19      7.04%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    61     22.59%     29.63% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  190     70.37%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               110495     48.92%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               80157     35.49%     84.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              35220     15.59%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::total                225872                       # Type of FU issued
+system.cpu2.iq.rate                          1.297981                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                        270                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001195                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            620987                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           238263                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       224632                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses                226142                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads           30940                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.squashedLoads         1843                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation           32                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores          852                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu2.iew.iewSquashCycles                  2059                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                   1941                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                   63                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts             266786                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              354                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                75827                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               35627                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1018                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    57                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents            32                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect           683                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect          611                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                1294                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               225039                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                74986                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts              833                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu2.iew.exec_nop                        37265                       # number of nop insts executed
+system.cpu2.iew.exec_refs                      110171                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   46373                       # Number of branches executed
+system.cpu2.iew.exec_stores                     35185                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.293194                       # Inst execution rate
+system.cpu2.iew.wb_sent                        224805                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       224632                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                   127007                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                   131418                       # num instructions consuming a value
+system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu2.iew.wb_rate                      1.290855                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.966435                       # average fanout of values written-back
+system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu2.commit.commitCommittedInsts        256708                       # The number of committed instructions
+system.cpu2.commit.commitSquashedInsts          10074                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           5686                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             1149                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       160519                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.599237                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.012927                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        67924     42.32%     42.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        44668     27.83%     70.14% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         6005      3.74%     73.88% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         6542      4.08%     77.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1606      1.00%     78.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        31385     19.55%     98.51% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          504      0.31%     98.83% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7         1049      0.65%     99.48% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8          836      0.52%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total       160519                       # Number of insts commited each cycle
+system.cpu2.commit.count                       256708                       # Number of instructions committed
+system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu2.commit.refs                        108759                       # Number of memory references committed
+system.cpu2.commit.loads                        73984                       # Number of loads committed
+system.cpu2.commit.membars                       4966                       # Number of memory barriers committed
+system.cpu2.commit.branches                     45704                       # Number of branches committed
+system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                   176579                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
+system.cpu2.commit.bw_lim_events                  836                       # number cycles where commit BW limit reached
+system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu2.rob.rob_reads                      425878                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     535627                       # The number of ROB writes
+system.cpu2.timesIdled                            232                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           5048                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                       34616                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                     215254                       # Number of Instructions Simulated
+system.cpu2.committedInsts_total               215254                       # Number of Instructions Simulated
+system.cpu2.cpi                              0.808431                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.808431                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.236964                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.236964                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  389052                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 181919                       # number of integer regfile writes
+system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                 111746                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
+system.cpu2.icache.replacements                   321                       # number of replacements
+system.cpu2.icache.tagsinuse                85.227474                       # Cycle average of tags in use
+system.cpu2.icache.total_refs                   18578                       # Total number of references to valid blocks.
+system.cpu2.icache.sampled_refs                   427                       # Sample count of references to valid blocks.
+system.cpu2.icache.avg_refs                 43.508197                       # Average number of references to valid blocks.
+system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.occ_blocks::0            85.227474                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.166460                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits                 18578                       # number of ReadReq hits
+system.cpu2.icache.demand_hits                  18578                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits                 18578                       # number of overall hits
+system.cpu2.icache.ReadReq_misses                 481                       # number of ReadReq misses
+system.cpu2.icache.demand_misses                  481                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses                 481                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency      10446500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency       10446500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency      10446500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses             19059                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses              19059                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses             19059                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate         0.025237                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate          0.025237                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate         0.025237                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency 21718.295218                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency 21718.295218                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency 21718.295218                       # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs        33000                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs        33000                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.icache.writebacks                       0                       # number of writebacks
+system.cpu2.icache.ReadReq_mshr_hits               54                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits                54                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits               54                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses            427                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses             427                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses            427                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.icache.ReadReq_mshr_miss_latency      8026500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency      8026500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency      8026500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate     0.022404                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate     0.022404                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate     0.022404                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18797.423888                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency 18797.423888                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency 18797.423888                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.dcache.replacements                     2                       # number of replacements
+system.cpu2.dcache.tagsinuse                19.370911                       # Cycle average of tags in use
+system.cpu2.dcache.total_refs                   40686                       # Total number of references to valid blocks.
+system.cpu2.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
+system.cpu2.dcache.avg_refs               1356.200000                       # Average number of references to valid blocks.
+system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.occ_blocks::0            26.582846                       # Average occupied blocks per context
+system.cpu2.dcache.occ_blocks::1            -7.211935                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.051920                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::1           -0.014086                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits                 43569                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits                34581                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits                    13                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits                  78150                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits                 78150                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses                 459                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses                120                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses                  61                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses                  579                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses                 579                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency      10999500                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency      2980500                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency       1343500                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency       13980000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency      13980000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses             44028                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses            34701                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses                74                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses              78729                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses             78729                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate         0.010425                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate        0.003458                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate         0.824324                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate          0.007354                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate         0.007354                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency 23964.052288                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency 24837.500000                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency 22024.590164                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency 24145.077720                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency 24145.077720                       # average overall miss latency
+system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.dcache.writebacks                       1                       # number of writebacks
+system.cpu2.dcache.ReadReq_mshr_hits              297                       # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits               315                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits              315                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses            162                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses           102                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses             61                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses             264                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses            264                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency      2380000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency      1660000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency      1160500                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency      4040000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency      4040000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate     0.003679                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate     0.002939                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate     0.824324                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate     0.003353                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate     0.003353                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14691.358025                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16274.509804                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19024.590164                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency 15303.030303                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency 15303.030303                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.numCycles                          173752                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.BPredUnit.lookups                   43974                       # Number of BP lookups
+system.cpu3.BPredUnit.condPredicted             41362                       # Number of conditional branches predicted
+system.cpu3.BPredUnit.condIncorrect              1065                       # Number of conditional branches incorrect
+system.cpu3.BPredUnit.BTBLookups                40218                       # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits                   38243                       # Number of BTB hits
+system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu3.BPredUnit.usedRAS                     627                       # Number of times the RAS was used to get a target.
+system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
+system.cpu3.fetch.icacheStallCycles             31228                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        238342                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      43974                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             38870                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                        88902                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   3085                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles                 41810                       # Number of cycles fetch has spent blocked
+system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.NoActiveThreadStallCycles         6387                       # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.PendingTrapStallCycles          706                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines                    22959                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes                  173                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples            170982                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.393960                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.002021                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   82080     48.01%     48.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   46273     27.06%     75.07% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    8028      4.70%     79.76% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3581      2.09%     81.86% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                     661      0.39%     82.24% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   25734     15.05%     97.30% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1333      0.78%     98.07% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                     378      0.22%     98.30% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    2914      1.70%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::total              170982                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.253085                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       1.371737                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   38250                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                36210                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                    81249                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 6942                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  1944                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                235582                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  1944                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   38898                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  21197                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         14171                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    74841                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                13544                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                233650                       # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents                    34                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LSQFullEvents                   44                       # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands             161376                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               435940                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          435940                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               151925                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                    9451                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts              1060                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts          1201                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                    16222                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               63593                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              28573                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            31152                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           24018                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    191280                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               8270                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   196054                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined           8200                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined         7610                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved           629                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       170982                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.146635                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.276395                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              79237     46.34%     46.34% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              28336     16.57%     62.91% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              28717     16.80%     79.71% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              30135     17.62%     97.33% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3289      1.92%     99.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1034      0.60%     99.86% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                139      0.08%     99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7                 41      0.02%     99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8                 54      0.03%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         170982                       # Number of insts issued each cycle
+system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     11      4.49%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    44     17.96%     22.45% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  190     77.55%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu                97962     49.97%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               69919     35.66%     85.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              28173     14.37%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::total                196054                       # Type of FU issued
+system.cpu3.iq.rate                          1.128355                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        245                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001250                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            563338                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           207780                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       194934                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses                196299                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads           23899                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu3.iew.lsq.thread0.squashedLoads         1728                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           30                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores          841                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu3.iew.iewSquashCycles                  1944                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                   1688                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles                   45                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts             231715                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              366                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                63593                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               28573                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts               992                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents            30                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect           631                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect          549                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                1180                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               195273                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                62778                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts              781                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu3.iew.exec_nop                        32165                       # number of nop insts executed
+system.cpu3.iew.exec_refs                       90920                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   41191                       # Number of branches executed
+system.cpu3.iew.exec_stores                     28142                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.123860                       # Inst execution rate
+system.cpu3.iew.wb_sent                        195091                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       194934                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   107675                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   111992                       # num instructions consuming a value
+system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu3.iew.wb_rate                      1.121909                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.961453                       # average fanout of values written-back
+system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu3.commit.commitCommittedInsts        222296                       # The number of committed instructions
+system.cpu3.commit.commitSquashedInsts           9409                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           7641                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             1065                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       162652                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.366697                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.912123                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        80351     49.40%     49.40% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        39430     24.24%     73.64% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         6019      3.70%     77.34% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         8502      5.23%     82.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1632      1.00%     83.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        24257     14.91%     98.49% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          559      0.34%     98.83% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7         1061      0.65%     99.48% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8          841      0.52%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::total       162652                       # Number of insts commited each cycle
+system.cpu3.commit.count                       222296                       # Number of instructions committed
+system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu3.commit.refs                         89597                       # Number of memory references committed
+system.cpu3.commit.loads                        61865                       # Number of loads committed
+system.cpu3.commit.membars                       6925                       # Number of memory barriers committed
+system.cpu3.commit.branches                     40618                       # Number of branches committed
+system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
+system.cpu3.commit.int_insts                   152335                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
+system.cpu3.commit.bw_lim_events                  841                       # number cycles where commit BW limit reached
+system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu3.rob.rob_reads                      392929                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     465356                       # The number of ROB writes
+system.cpu3.timesIdled                            234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                           2770                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                       34882                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                     183965                       # Number of Instructions Simulated
+system.cpu3.committedInsts_total               183965                       # Number of Instructions Simulated
+system.cpu3.cpi                              0.944484                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.944484                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.058779                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.058779                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  330929                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 155348                       # number of integer regfile writes
+system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
+system.cpu3.misc_regfile_reads                  92475                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
+system.cpu3.icache.replacements                   318                       # number of replacements
+system.cpu3.icache.tagsinuse                80.006059                       # Cycle average of tags in use
+system.cpu3.icache.total_refs                   22493                       # Total number of references to valid blocks.
+system.cpu3.icache.sampled_refs                   426                       # Sample count of references to valid blocks.
+system.cpu3.icache.avg_refs                 52.800469                       # Average number of references to valid blocks.
+system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.occ_blocks::0            80.006059                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.156262                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits                 22493                       # number of ReadReq hits
+system.cpu3.icache.demand_hits                  22493                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits                 22493                       # number of overall hits
+system.cpu3.icache.ReadReq_misses                 466                       # number of ReadReq misses
+system.cpu3.icache.demand_misses                  466                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses                 466                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency       6527000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency        6527000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency       6527000                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses             22959                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses              22959                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses             22959                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate         0.020297                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate          0.020297                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate         0.020297                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency 14006.437768                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency 14006.437768                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency 14006.437768                       # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.icache.writebacks                       0                       # number of writebacks
+system.cpu3.icache.ReadReq_mshr_hits               40                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits                40                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits               40                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_misses            426                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses             426                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses            426                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.icache.ReadReq_mshr_miss_latency      4833500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency      4833500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency      4833500                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate     0.018555                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate     0.018555                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate     0.018555                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11346.244131                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency 11346.244131                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency 11346.244131                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.dcache.replacements                     2                       # number of replacements
+system.cpu3.dcache.tagsinuse                13.455705                       # Cycle average of tags in use
+system.cpu3.dcache.total_refs                   33584                       # Total number of references to valid blocks.
+system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
+system.cpu3.dcache.avg_refs               1158.068966                       # Average number of references to valid blocks.
+system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.occ_blocks::0            23.407477                       # Average occupied blocks per context
+system.cpu3.dcache.occ_blocks::1            -9.951772                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.045718                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::1           -0.019437                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits                 38412                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits                27537                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits                    14                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits                  65949                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits                 65949                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses                 448                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses                125                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses                  56                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses                  573                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses                 573                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency       9358000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency      2911000                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency       1350500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency       12269000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency      12269000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses             38860                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses            27662                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses                70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses              66522                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses             66522                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate         0.011529                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate        0.004519                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate         0.800000                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate          0.008614                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate         0.008614                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency 20888.392857                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency        23288                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency 24116.071429                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency 21411.867365                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency 21411.867365                       # average overall miss latency
+system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.dcache.writebacks                       1                       # number of writebacks
+system.cpu3.dcache.ReadReq_mshr_hits              279                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits              17                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits               296                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits              296                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses            169                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses           108                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses             56                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses             277                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses            277                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency      2218000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency      1624500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency      1182500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency      3842500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency      3842500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate     0.004349                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate     0.003904                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate     0.800000                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate     0.004164                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate     0.004164                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13124.260355                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15041.666667                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 21116.071429                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency 13871.841155                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency 13871.841155                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.l2c.replacements                             0                       # number of replacements
+system.l2c.tagsinuse                       428.231635                       # Cycle average of tags in use
+system.l2c.total_refs                            1446                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                           527                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          2.743833                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                   347.174574                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                    11.269547                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                    63.254631                       # Average occupied blocks per context
+system.l2c.occ_blocks::3                     1.567259                       # Average occupied blocks per context
+system.l2c.occ_blocks::4                     4.965624                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.005297                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.000172                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.000965                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.000024                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000076                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                        233                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                        424                       # number of ReadReq hits
+system.l2c.ReadReq_hits::2                        356                       # number of ReadReq hits
+system.l2c.ReadReq_hits::3                        436                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                   1449                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
+system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                       3                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
+system.l2c.demand_hits::0                         233                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                         424                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                         356                       # number of demand (read+write) hits
+system.l2c.demand_hits::3                         436                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                    1449                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                        233                       # number of overall hits
+system.l2c.overall_hits::1                        424                       # number of overall hits
+system.l2c.overall_hits::2                        356                       # number of overall hits
+system.l2c.overall_hits::3                        436                       # number of overall hits
+system.l2c.overall_hits::total                   1449                       # number of overall hits
+system.l2c.ReadReq_misses::0                      429                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                       16                       # number of ReadReq misses
+system.l2c.ReadReq_misses::2                       85                       # number of ReadReq misses
+system.l2c.ReadReq_misses::3                        3                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                  533                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                    21                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                    22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::2                    22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::3                    22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                87                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                     94                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                     12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::2                     13                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::3                     12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
+system.l2c.demand_misses::0                       523                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                        28                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                        98                       # number of demand (read+write) misses
+system.l2c.demand_misses::3                        15                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                   664                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                      523                       # number of overall misses
+system.l2c.overall_misses::1                       28                       # number of overall misses
+system.l2c.overall_misses::2                       98                       # number of overall misses
+system.l2c.overall_misses::3                       15                       # number of overall misses
+system.l2c.overall_misses::total                  664                       # number of overall misses
+system.l2c.ReadReq_miss_latency              27701000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency             157500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency             6878000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency               34579000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency              34579000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                    662                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                    440                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2                    441                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::3                    439                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               1982                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                  24                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                  22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::2                  22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::3                  22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              90                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0                   94                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                   12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::2                   13                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::3                   12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                     756                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                     452                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                     454                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::3                     451                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                2113                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                    756                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                    452                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                    454                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::3                    451                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               2113                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.648036                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.036364                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2              0.192744                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3              0.006834                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.883977                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.875000                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       3.875000                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.691799                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.061947                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               0.215859                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::3               0.033259                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           1.002864                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.691799                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.061947                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              0.215859                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::3              0.033259                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          1.002864                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   64571.095571                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   1731312.500000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2   325894.117647                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3   9233666.666667                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 11355444.379885                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0         7500                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1  7159.090909                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2  7159.090909                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::3  7159.090909                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 28977.272727                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 73170.212766                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 573166.666667                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 529076.923077                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::3 573166.666667                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 1748580.469176                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0    66116.634799                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    1234964.285714                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2    352846.938776                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::3    2305266.666667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 3959194.525956                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   66116.634799                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   1234964.285714                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2   352846.938776                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::3   2305266.666667                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 3959194.525956                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                               0                       # number of writebacks
+system.l2c.ReadReq_mshr_hits                        8                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits                         8                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                        8                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                    525                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                  87                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses                  131                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                     656                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                    656                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency         20993500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency       3480000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency        5279000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency          26272500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency         26272500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.793051                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         1.193182                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2         1.190476                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::3         1.195900                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     4.372609                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      3.625000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      3.954545                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2      3.954545                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::3      3.954545                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total    15.488636                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       1.393617                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1      10.916667                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2      10.076923                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::3      10.916667                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total    33.303873                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0          0.867725                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.451327                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2          1.444934                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::3          1.454545                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      5.218532                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0         0.867725                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.451327                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2         1.444934                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::3         1.454545                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     5.218532                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 39987.619048                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40049.542683                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40049.542683                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
new file mode 100644
index 000000000..65fcae2f7
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -0,0 +1,520 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[2]
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dtb icache itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=system.cpu0.workload
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu0.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.itb]
+type=SparcTLB
+size=64
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu0.workload]
+type=LiveProcess
+cmd=test_atomic 4
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dcache dtb icache itb tracer
+checker=Null
+clock=500
+cpu_id=1
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu1.tracer
+width=1
+workload=system.cpu0.workload
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.dcache_port
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu1.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu1.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu1.itb]
+type=SparcTLB
+size=64
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu2]
+type=AtomicSimpleCPU
+children=dcache dtb icache itb tracer
+checker=Null
+clock=500
+cpu_id=2
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu2.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu2.tracer
+width=1
+workload=system.cpu0.workload
+dcache_port=system.cpu2.dcache.cpu_side
+icache_port=system.cpu2.icache.cpu_side
+
+[system.cpu2.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.dcache_port
+mem_side=system.toL2Bus.port[6]
+
+[system.cpu2.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu2.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.icache_port
+mem_side=system.toL2Bus.port[5]
+
+[system.cpu2.itb]
+type=SparcTLB
+size=64
+
+[system.cpu2.tracer]
+type=ExeTracer
+
+[system.cpu3]
+type=AtomicSimpleCPU
+children=dcache dtb icache itb tracer
+checker=Null
+clock=500
+cpu_id=3
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu3.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu3.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu3.tracer
+width=1
+workload=system.cpu0.workload
+dcache_port=system.cpu3.dcache.cpu_side
+icache_port=system.cpu3.icache.cpu_side
+
+[system.cpu3.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.dcache_port
+mem_side=system.toL2Bus.port[8]
+
+[system.cpu3.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu3.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.icache_port
+mem_side=system.toL2Bus.port[7]
+
+[system.cpu3.itb]
+type=SparcTLB
+size=64
+
+[system.cpu3.tracer]
+type=ExeTracer
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=4
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[0]
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.mem_side system.physmem.port[0] system.system_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:1073741823
+zero=false
+port=system.membus.port[1]
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
new file mode 100755
index 000000000..8daa6c894
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -0,0 +1,82 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:32
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Init done
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 1 completed
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 2 completed
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 3 completed
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
+Iteration 4 completed
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 5 completed
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 6 completed
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 7 completed
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 8 completed
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 9 completed
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 10 completed
+PASSED :-)
+Exiting @ tick 87713500 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
new file mode 100644
index 000000000..0cc0a830c
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -0,0 +1,688 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000088                       # Number of seconds simulated
+sim_ticks                                    87713500                       # Number of ticks simulated
+final_tick                                   87713500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1650324                       # Simulator instruction rate (inst/s)
+host_tick_rate                              213702670                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1140448                       # Number of bytes of host memory used
+host_seconds                                     0.41                       # Real time elapsed on the host
+sim_insts                                      677340                       # Number of instructions simulated
+system.physmem.bytes_read                       35776                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  22272                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          559                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      407873360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 253917584                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     407873360                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu0.workload.num_syscalls                  89                       # Number of system calls
+system.cpu0.numCycles                          175428                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.num_insts                          175339                       # Number of instructions executed
+system.cpu0.num_int_alu_accesses               120388                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts        28825                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      120388                       # number of integer instructions
+system.cpu0.num_fp_insts                            0                       # number of float instructions
+system.cpu0.num_int_register_reads             349308                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            121996                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                        82398                       # number of memory refs
+system.cpu0.num_load_insts                      54592                       # Number of load instructions
+system.cpu0.num_store_insts                     27806                       # Number of store instructions
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu0.num_busy_cycles                    175428                       # Number of busy cycles
+system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.icache.replacements                   215                       # number of replacements
+system.cpu0.icache.tagsinuse               222.757301                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                  174934                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                   467                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                374.591006                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0           222.757301                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.435073                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits                174934                       # number of ReadReq hits
+system.cpu0.icache.demand_hits                 174934                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits                174934                       # number of overall hits
+system.cpu0.icache.ReadReq_misses                 467                       # number of ReadReq misses
+system.cpu0.icache.demand_misses                  467                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses                 467                       # number of overall misses
+system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses            175401                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses             175401                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses            175401                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate         0.002662                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate          0.002662                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate         0.002662                       # miss rate for overall accesses
+system.cpu0.icache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks                       0                       # number of writebacks
+system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu0.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements                     9                       # number of replacements
+system.cpu0.dcache.tagsinuse               145.712770                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                   61599                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                362.347059                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::0           145.712770                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.284595                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits                 54431                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits                27578                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits                    15                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits                  82009                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits                 82009                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses                 151                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses                177                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses                  27                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses                  328                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses                 328                       # number of overall misses
+system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses             54582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses            27755                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses              82337                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses             82337                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate         0.002766                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate        0.006377                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate         0.642857                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate          0.003984                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate         0.003984                       # miss rate for overall accesses
+system.cpu0.dcache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks                       6                       # number of writebacks
+system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu0.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.numCycles                          173308                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.num_insts                          167398                       # Number of instructions executed
+system.cpu1.num_int_alu_accesses               109926                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu1.num_func_calls                        633                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts        32743                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                      109926                       # number of integer instructions
+system.cpu1.num_fp_insts                            0                       # number of float instructions
+system.cpu1.num_int_register_reads             270038                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            100721                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                        53394                       # number of memory refs
+system.cpu1.num_load_insts                      40652                       # Number of load instructions
+system.cpu1.num_store_insts                     12742                       # Number of store instructions
+system.cpu1.num_idle_cycles               7886.574443                       # Number of idle cycles
+system.cpu1.num_busy_cycles              165421.425557                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.954494                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.045506                       # Percentage of idle cycles
+system.cpu1.icache.replacements                   278                       # number of replacements
+system.cpu1.icache.tagsinuse                76.746014                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                  167072                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                   358                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                466.681564                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::0            76.746014                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.149895                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits                167072                       # number of ReadReq hits
+system.cpu1.icache.demand_hits                 167072                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits                167072                       # number of overall hits
+system.cpu1.icache.ReadReq_misses                 358                       # number of ReadReq misses
+system.cpu1.icache.demand_misses                  358                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses                 358                       # number of overall misses
+system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses            167430                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses             167430                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses            167430                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate         0.002138                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate          0.002138                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate         0.002138                       # miss rate for overall accesses
+system.cpu1.icache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks                       0                       # number of writebacks
+system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu1.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.replacements                     2                       # number of replacements
+system.cpu1.dcache.tagsinuse                29.073016                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                   26889                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                960.321429                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0            29.073016                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.056783                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits                 40468                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits                12563                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits                    14                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits                  53031                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits                 53031                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses                 176                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses                106                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses                  57                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses                  282                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses                 282                       # number of overall misses
+system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses             40644                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses            12669                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses                71                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses              53313                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses             53313                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate         0.004330                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate        0.008367                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate         0.802817                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate          0.005290                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate         0.005290                       # miss rate for overall accesses
+system.cpu1.dcache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks                       1                       # number of writebacks
+system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu1.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.numCycles                          173308                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.num_insts                          167334                       # Number of instructions executed
+system.cpu2.num_int_alu_accesses               113333                       # Number of integer alu accesses
+system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu2.num_func_calls                        633                       # number of times a function call or return occured
+system.cpu2.num_conditional_control_insts        31007                       # number of instructions that are conditional controls
+system.cpu2.num_int_insts                      113333                       # number of integer instructions
+system.cpu2.num_fp_insts                            0                       # number of float instructions
+system.cpu2.num_int_register_reads             290613                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            109308                       # number of times the integer registers were written
+system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu2.num_mem_refs                        58537                       # number of memory refs
+system.cpu2.num_load_insts                      42362                       # Number of load instructions
+system.cpu2.num_store_insts                     16175                       # Number of store instructions
+system.cpu2.num_idle_cycles               7949.801380                       # Number of idle cycles
+system.cpu2.num_busy_cycles              165358.198620                       # Number of busy cycles
+system.cpu2.not_idle_fraction                0.954129                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                    0.045871                       # Percentage of idle cycles
+system.cpu2.icache.replacements                   278                       # number of replacements
+system.cpu2.icache.tagsinuse                74.775474                       # Cycle average of tags in use
+system.cpu2.icache.total_refs                  167008                       # Total number of references to valid blocks.
+system.cpu2.icache.sampled_refs                   358                       # Sample count of references to valid blocks.
+system.cpu2.icache.avg_refs                466.502793                       # Average number of references to valid blocks.
+system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.occ_blocks::0            74.775474                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.146046                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits                167008                       # number of ReadReq hits
+system.cpu2.icache.demand_hits                 167008                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits                167008                       # number of overall hits
+system.cpu2.icache.ReadReq_misses                 358                       # number of ReadReq misses
+system.cpu2.icache.demand_misses                  358                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses                 358                       # number of overall misses
+system.cpu2.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses            167366                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses             167366                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses            167366                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate         0.002139                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate          0.002139                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate         0.002139                       # miss rate for overall accesses
+system.cpu2.icache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.icache.writebacks                       0                       # number of writebacks
+system.cpu2.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu2.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu2.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.dcache.replacements                     2                       # number of replacements
+system.cpu2.dcache.tagsinuse                28.420699                       # Cycle average of tags in use
+system.cpu2.dcache.total_refs                   33771                       # Total number of references to valid blocks.
+system.cpu2.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
+system.cpu2.dcache.avg_refs               1206.107143                       # Average number of references to valid blocks.
+system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.occ_blocks::0            28.420699                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.055509                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits                 42192                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits                15998                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits                    11                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits                  58190                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits                 58190                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses                 162                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses                109                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses                  55                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses                  271                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses                 271                       # number of overall misses
+system.cpu2.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses             42354                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses            16107                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses                66                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses              58461                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses             58461                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate         0.003825                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate        0.006767                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate         0.833333                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate          0.004636                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate         0.004636                       # miss rate for overall accesses
+system.cpu2.dcache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.dcache.writebacks                       1                       # number of writebacks
+system.cpu2.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu2.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu2.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.numCycles                          173307                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.num_insts                          167269                       # Number of instructions executed
+system.cpu3.num_int_alu_accesses               111554                       # Number of integer alu accesses
+system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu3.num_func_calls                        633                       # number of times a function call or return occured
+system.cpu3.num_conditional_control_insts        31865                       # number of instructions that are conditional controls
+system.cpu3.num_int_insts                      111554                       # number of integer instructions
+system.cpu3.num_fp_insts                            0                       # number of float instructions
+system.cpu3.num_int_register_reads             280060                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            104916                       # number of times the integer registers were written
+system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu3.num_mem_refs                        55900                       # number of memory refs
+system.cpu3.num_load_insts                      41466                       # Number of load instructions
+system.cpu3.num_store_insts                     14434                       # Number of store instructions
+system.cpu3.num_idle_cycles               8013.969997                       # Number of idle cycles
+system.cpu3.num_busy_cycles              165293.030003                       # Number of busy cycles
+system.cpu3.not_idle_fraction                0.953759                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                    0.046241                       # Percentage of idle cycles
+system.cpu3.icache.replacements                   279                       # number of replacements
+system.cpu3.icache.tagsinuse                72.869097                       # Cycle average of tags in use
+system.cpu3.icache.total_refs                  166942                       # Total number of references to valid blocks.
+system.cpu3.icache.sampled_refs                   359                       # Sample count of references to valid blocks.
+system.cpu3.icache.avg_refs                465.019499                       # Average number of references to valid blocks.
+system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.occ_blocks::0            72.869097                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.142322                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits                166942                       # number of ReadReq hits
+system.cpu3.icache.demand_hits                 166942                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits                166942                       # number of overall hits
+system.cpu3.icache.ReadReq_misses                 359                       # number of ReadReq misses
+system.cpu3.icache.demand_misses                  359                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses                 359                       # number of overall misses
+system.cpu3.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses            167301                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses             167301                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses            167301                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate         0.002146                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate          0.002146                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate         0.002146                       # miss rate for overall accesses
+system.cpu3.icache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.icache.writebacks                       0                       # number of writebacks
+system.cpu3.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu3.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu3.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.dcache.replacements                     2                       # number of replacements
+system.cpu3.dcache.tagsinuse                27.588376                       # Cycle average of tags in use
+system.cpu3.dcache.total_refs                   30309                       # Total number of references to valid blocks.
+system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
+system.cpu3.dcache.avg_refs               1045.137931                       # Average number of references to valid blocks.
+system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.occ_blocks::0            27.588376                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.053884                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits                 41299                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits                14260                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits                    15                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits                  55559                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits                 55559                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses                 159                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses                102                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses                  55                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses                  261                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses                 261                       # number of overall misses
+system.cpu3.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses             41458                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses            14362                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses                70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses              55820                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses             55820                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate         0.003835                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate        0.007102                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate         0.785714                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate          0.004676                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate         0.004676                       # miss rate for overall accesses
+system.cpu3.dcache.demand_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.dcache.writebacks                       1                       # number of writebacks
+system.cpu3.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu3.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
+system.cpu3.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.l2c.replacements                             0                       # number of replacements
+system.l2c.tagsinuse                       371.980910                       # Cycle average of tags in use
+system.l2c.total_refs                            1223                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                           426                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          2.870892                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                   294.613840                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                    66.228089                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                     2.865859                       # Average occupied blocks per context
+system.l2c.occ_blocks::3                     1.883074                       # Average occupied blocks per context
+system.l2c.occ_blocks::4                     6.390048                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.004495                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.001011                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.000044                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.000029                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000098                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                        190                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                        301                       # number of ReadReq hits
+system.l2c.ReadReq_hits::2                        367                       # number of ReadReq hits
+system.l2c.ReadReq_hits::3                        368                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                   1226                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
+system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                       2                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
+system.l2c.demand_hits::0                         190                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                         301                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                         367                       # number of demand (read+write) hits
+system.l2c.demand_hits::3                         368                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                    1226                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                        190                       # number of overall hits
+system.l2c.overall_hits::1                        301                       # number of overall hits
+system.l2c.overall_hits::2                        367                       # number of overall hits
+system.l2c.overall_hits::3                        368                       # number of overall hits
+system.l2c.overall_hits::total                   1226                       # number of overall hits
+system.l2c.ReadReq_misses::0                      348                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                       69                       # number of ReadReq misses
+system.l2c.ReadReq_misses::2                        3                       # number of ReadReq misses
+system.l2c.ReadReq_misses::3                        3                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                  423                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                    29                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                    19                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::2                    20                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::3                    19                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                87                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                     99                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                     13                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::2                     12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::3                     12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                136                       # number of ReadExReq misses
+system.l2c.demand_misses::0                       447                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                        82                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                        15                       # number of demand (read+write) misses
+system.l2c.demand_misses::3                        15                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                   559                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                      447                       # number of overall misses
+system.l2c.overall_misses::1                       82                       # number of overall misses
+system.l2c.overall_misses::2                       15                       # number of overall misses
+system.l2c.overall_misses::3                       15                       # number of overall misses
+system.l2c.overall_misses::total                  559                       # number of overall misses
+system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                    538                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                    370                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2                    370                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::3                    371                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               1649                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                  31                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                  19                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::2                  20                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::3                  19                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              89                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0                   99                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                   13                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::2                   12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::3                   12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              136                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                     637                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                     383                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                     382                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::3                     383                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                1785                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                    637                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                    383                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                    382                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::3                    383                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               1785                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.646840                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.186486                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2              0.008108                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3              0.008086                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.849521                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.935484                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       3.935484                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.701727                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.214099                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               0.039267                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::3               0.039164                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.994258                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.701727                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.214099                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              0.039267                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::3              0.039164                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.994258                       # miss rate for overall accesses
+system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::3               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::3              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                               0                       # number of writebacks
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::3                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total             0                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::3                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total            0                       # mshr miss rate for overall accesses
+system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
new file mode 100644
index 000000000..a2a28909c
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
@@ -0,0 +1,206 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 membus physmem
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu0.tracer
+workload=system.cpu0.workload
+dcache_port=system.membus.port[1]
+icache_port=system.membus.port[0]
+
+[system.cpu0.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu0.itb]
+type=SparcTLB
+size=64
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu0.workload]
+type=LiveProcess
+cmd=test_atomic 4
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dtb itb tracer
+checker=Null
+clock=500
+cpu_id=1
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu1.tracer
+workload=system.cpu0.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu1.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu1.itb]
+type=SparcTLB
+size=64
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu2]
+type=TimingSimpleCPU
+children=dtb itb tracer
+checker=Null
+clock=500
+cpu_id=2
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu2.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu2.tracer
+workload=system.cpu0.workload
+dcache_port=system.membus.port[5]
+icache_port=system.membus.port[4]
+
+[system.cpu2.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu2.itb]
+type=SparcTLB
+size=64
+
+[system.cpu2.tracer]
+type=ExeTracer
+
+[system.cpu3]
+type=TimingSimpleCPU
+children=dtb itb tracer
+checker=Null
+clock=500
+cpu_id=3
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu3.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu3.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu3.tracer
+workload=system.cpu0.workload
+dcache_port=system.membus.port[7]
+icache_port=system.membus.port[6]
+
+[system.cpu3.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu3.itb]
+type=SparcTLB
+size=64
+
+[system.cpu3.tracer]
+type=ExeTracer
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port system.cpu2.icache_port system.cpu2.dcache_port system.cpu3.icache_port system.cpu3.dcache_port system.physmem.port[0]
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=4
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[8]
+
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
new file mode 100644
index 000000000..5758c154e
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
@@ -0,0 +1,1004 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:54:24, May  4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 4
+g_NUM_L2_BANKS: 4
+g_NUM_MEMORIES: 4
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 4
+g_NUM_CHIP_BITS: 2
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 2
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 2
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 2
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 24
+g_MEMORY_MODULE_BLOCKS: 16777216
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 4
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+  cache_associativity: 4
+  num_cache_sets_bits: 8
+  num_cache_sets: 256
+  cache_set_size_bytes: 16384
+  cache_set_size_Kbytes: 16
+  cache_set_size_Mbytes: 0.015625
+  cache_size_bytes: 65536
+  cache_size_Kbytes: 64
+  cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+  cache_associativity: 4
+  num_cache_sets_bits: 8
+  num_cache_sets: 256
+  cache_set_size_bytes: 16384
+  cache_set_size_Kbytes: 16
+  cache_set_size_Mbytes: 0.015625
+  cache_size_bytes: 65536
+  cache_size_Kbytes: 64
+  cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+  cache_associativity: 4
+  num_cache_sets_bits: 16
+  num_cache_sets: 65536
+  cache_set_size_bytes: 4194304
+  cache_set_size_Kbytes: 4096
+  cache_set_size_Mbytes: 4
+  cache_size_bytes: 16777216
+  cache_size_Kbytes: 16384
+  cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+  max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+  memory_bits: 32
+  memory_size_bytes: 4294967296
+  memory_size_Kbytes: 4.1943e+06
+  memory_size_Mbytes: 4096
+  memory_size_Gbytes: 4
+  module_bits: 24
+  module_size_lines: 16777216
+  module_size_bytes: 1073741824
+  module_size_Kbytes: 1.04858e+06
+  module_size_Mbytes: 1024
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+  L1Cache-0 -> L1Cache-1 net_lat: 9
+  L1Cache-0 -> L1Cache-2 net_lat: 9
+  L1Cache-0 -> L1Cache-3 net_lat: 9
+  L1Cache-0 -> Directory-0 net_lat: 9
+  L1Cache-0 -> Directory-1 net_lat: 9
+  L1Cache-0 -> Directory-2 net_lat: 9
+  L1Cache-0 -> Directory-3 net_lat: 9
+
+L1Cache-1 Network Latencies
+  L1Cache-1 -> L1Cache-0 net_lat: 9
+  L1Cache-1 -> L1Cache-2 net_lat: 9
+  L1Cache-1 -> L1Cache-3 net_lat: 9
+  L1Cache-1 -> Directory-0 net_lat: 9
+  L1Cache-1 -> Directory-1 net_lat: 9
+  L1Cache-1 -> Directory-2 net_lat: 9
+  L1Cache-1 -> Directory-3 net_lat: 9
+
+L1Cache-2 Network Latencies
+  L1Cache-2 -> L1Cache-0 net_lat: 9
+  L1Cache-2 -> L1Cache-1 net_lat: 9
+  L1Cache-2 -> L1Cache-3 net_lat: 9
+  L1Cache-2 -> Directory-0 net_lat: 9
+  L1Cache-2 -> Directory-1 net_lat: 9
+  L1Cache-2 -> Directory-2 net_lat: 9
+  L1Cache-2 -> Directory-3 net_lat: 9
+
+L1Cache-3 Network Latencies
+  L1Cache-3 -> L1Cache-0 net_lat: 9
+  L1Cache-3 -> L1Cache-1 net_lat: 9
+  L1Cache-3 -> L1Cache-2 net_lat: 9
+  L1Cache-3 -> Directory-0 net_lat: 9
+  L1Cache-3 -> Directory-1 net_lat: 9
+  L1Cache-3 -> Directory-2 net_lat: 9
+  L1Cache-3 -> Directory-3 net_lat: 9
+
+Directory-0 Network Latencies
+  Directory-0 -> L1Cache-0 net_lat: 9
+  Directory-0 -> L1Cache-1 net_lat: 9
+  Directory-0 -> L1Cache-2 net_lat: 9
+  Directory-0 -> L1Cache-3 net_lat: 9
+  Directory-0 -> Directory-1 net_lat: 9
+  Directory-0 -> Directory-2 net_lat: 9
+  Directory-0 -> Directory-3 net_lat: 9
+
+Directory-1 Network Latencies
+  Directory-1 -> L1Cache-0 net_lat: 9
+  Directory-1 -> L1Cache-1 net_lat: 9
+  Directory-1 -> L1Cache-2 net_lat: 9
+  Directory-1 -> L1Cache-3 net_lat: 9
+  Directory-1 -> Directory-0 net_lat: 9
+  Directory-1 -> Directory-2 net_lat: 9
+  Directory-1 -> Directory-3 net_lat: 9
+
+Directory-2 Network Latencies
+  Directory-2 -> L1Cache-0 net_lat: 9
+  Directory-2 -> L1Cache-1 net_lat: 9
+  Directory-2 -> L1Cache-2 net_lat: 9
+  Directory-2 -> L1Cache-3 net_lat: 9
+  Directory-2 -> Directory-0 net_lat: 9
+  Directory-2 -> Directory-1 net_lat: 9
+  Directory-2 -> Directory-3 net_lat: 9
+
+Directory-3 Network Latencies
+  Directory-3 -> L1Cache-0 net_lat: 9
+  Directory-3 -> L1Cache-1 net_lat: 9
+  Directory-3 -> L1Cache-2 net_lat: 9
+  Directory-3 -> L1Cache-3 net_lat: 9
+  Directory-3 -> Directory-0 net_lat: 9
+  Directory-3 -> Directory-1 net_lat: 9
+  Directory-3 -> Directory-2 net_lat: 9
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:42
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 40
+Elapsed_time_in_minutes: 0.666667
+Elapsed_time_in_hours: 0.0111111
+Elapsed_time_in_days: 0.000462963
+
+Virtual_time_in_seconds: 37.33
+Virtual_time_in_minutes: 0.622167
+Virtual_time_in_hours:   0.0103694
+Virtual_time_in_days:    0.0103694
+
+Ruby_current_time: 2480212001
+Ruby_start_time: 1
+Ruby_cycles: 2480212000
+
+mbytes_resident: 90.6484
+mbytes_total: 252.043
+resident_ratio: 0.35967
+
+Total_misses: 1949
+total_misses: 1949 [ 424 409 702 414 ]
+user_misses: 1949 [ 424 409 702 414 ]
+supervisor_misses: 0 [ 0 0 0 0 ]
+
+instruction_executed: 4 [ 1 1 1 1 ]
+cycles_executed: 4 [ 1 1 1 1 ]
+cycles_per_instruction: 2.48021e+09 [ 2.48021e+09 2.48021e+09 2.48021e+09 2.48021e+09 ]
+misses_per_thousand_instructions: 487250 [ 424000 409000 702000 414000 ]
+
+transactions_started: 0 [ 0 0 0 0 ]
+transactions_ended: 0 [ 0 0 0 0 ]
+instructions_per_transaction: 0 [ 0 0 0 0 ]
+cycles_per_transaction: 0 [ 0 0 0 0 ]
+misses_per_transaction: 0 [ 0 0 0 0 ]
+
+L1D_cache cache stats: 
+  L1D_cache_total_misses: 1340
+  L1D_cache_total_demand_misses: 1340
+  L1D_cache_total_prefetches: 0
+  L1D_cache_total_sw_prefetches: 0
+  L1D_cache_total_hw_prefetches: 0
+  L1D_cache_misses_per_transaction: 1340
+  L1D_cache_misses_per_instruction: 1340
+  L1D_cache_instructions_per_misses: 0.000746269
+
+  L1D_cache_request_type_LD:   47.4627%
+  L1D_cache_request_type_ST:   38.0597%
+  L1D_cache_request_type_ATOMIC:   14.4776%
+
+  L1D_cache_access_mode_type_UserMode:   1340    100%
+  L1D_cache_request_size: [binsize: log2 max: 8 count: 1340 average: 3.48881 | standard deviation: 2.44812 | 0 527 4 583 226 ]
+
+L1I_cache cache stats: 
+  L1I_cache_total_misses: 610
+  L1I_cache_total_demand_misses: 610
+  L1I_cache_total_prefetches: 0
+  L1I_cache_total_sw_prefetches: 0
+  L1I_cache_total_hw_prefetches: 0
+  L1I_cache_misses_per_transaction: 610
+  L1I_cache_misses_per_instruction: 610
+  L1I_cache_instructions_per_misses: 0.00163934
+
+  L1I_cache_request_type_IFETCH:   100%
+
+  L1I_cache_access_mode_type_UserMode:   610    100%
+  L1I_cache_request_size: [binsize: log2 max: 4 count: 610 average:     4 | standard deviation: 0 | 0 0 0 610 ]
+
+L2_cache cache stats: 
+  L2_cache_total_misses: 1949
+  L2_cache_total_demand_misses: 1949
+  L2_cache_total_prefetches: 0
+  L2_cache_total_sw_prefetches: 0
+  L2_cache_total_hw_prefetches: 0
+  L2_cache_misses_per_transaction: 1949
+  L2_cache_misses_per_instruction: 1949
+  L2_cache_instructions_per_misses: 0.000513084
+
+  L2_cache_request_type_LD:   32.6321%
+  L2_cache_request_type_ST:   26.1673%
+  L2_cache_request_type_ATOMIC:   9.95382%
+  L2_cache_request_type_IFETCH:   31.2468%
+
+  L2_cache_access_mode_type_UserMode:   1949    100%
+  L2_cache_request_size: [binsize: log2 max: 8 count: 1949 average: 3.64854 | standard deviation: 2.04355 | 0 527 4 1192 226 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  
+Directory-0:0  Directory-1:0  Directory-2:0  Directory-3:0  
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 1949 average:     0 | standard deviation: 0 | 1949 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 1950 average:     1 | standard deviation: 0 | 0 1950 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ]
+miss_latency_LD: [binsize: 1 max: 184 count: 636 average: 57.2925 | standard deviation: 53.9711 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 536 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 19 26 17 23 ]
+miss_latency_ST: [binsize: 1 max: 184 count: 510 average: 73.749 | standard deviation: 69.6824 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34 27 26 19 42 ]
+miss_latency_ATOMIC: [binsize: 1 max: 183 count: 194 average: 37.7887 | standard deviation: 23.3543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 0 1 ]
+miss_latency_IFETCH: [binsize: 1 max: 184 count: 610 average: 181.728 | standard deviation: 7.34165 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 113 125 131 117 123 ]
+miss_latency_NULL: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+conflicting_histogram: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 6 7 6 10 37 57 33 164 243 38 123 210 142 218 449 203 ]
+conflicting_histogram_percent: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 0.0513084 0 0 0 0 0 0 0 0 0 0 0.0513084 0 0.0513084 0.30785 0.359159 0.30785 0.513084 1.89841 2.92458 1.69318 8.41457 12.4679 1.94972 6.31093 10.7748 7.28579 11.1852 23.0375 10.4156 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+         I         M      GETS        310       15.9056
+         I         M      GETX        216       11.0826
+         I        OS      GETS        142       7.28579
+         I        OS      GETX         33       1.69318
+         I       OSS      GETS         54       2.77065
+         I       OSS      GETX         15      0.769625
+        NP         C      GETS         75       3.84813
+        NP         C      GETX        136       6.97794
+        NP         C GET_INSTR        348       17.8553
+        NP         M      GETS         17      0.872242
+        NP         M      GETX         11      0.564392
+        NP        OS      GETS          6       0.30785
+        NP       OSS      GETS          7      0.359159
+        NP         S      GETS          9      0.461775
+        NP         S GET_INSTR         93       4.77168
+        NP        SS      GETS         16      0.820934
+        NP        SS GET_INSTR        168       8.61981
+         O        OS      GETX         22       1.12878
+         O       OSS      GETX         60        3.0785
+         S        OS      GETX        124       6.36224
+         S       OSS      GETX         70       3.59159
+         S         S      GETX         17      0.872242
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 37
+system_time: 0
+page_reclaims: 23404
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 656
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:424 full:0
+MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:409 full:0
+MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:703 full:0
+MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:414 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 8.82828e-05
+  links_utilized_percent_switch_0_link_0: 8.82828e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Control: 424 3392 [ 424 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Data: 257 18504 [ 0 257 0 0 ] base_latency: 1
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 8.92504e-05
+  links_utilized_percent_switch_1_link_0: 8.92504e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Control: 409 3272 [ 409 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Data: 262 18864 [ 0 262 0 0 ] base_latency: 1
+
+switch_2_inlinks: 1
+switch_2_outlinks: 1
+links_utilized_percent_switch_2: 8.94117e-05
+  links_utilized_percent_switch_2_link_0: 8.94117e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Control: 702 5616 [ 702 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Data: 230 16560 [ 0 230 0 0 ] base_latency: 1
+
+switch_3_inlinks: 1
+switch_3_outlinks: 1
+links_utilized_percent_switch_3: 8.76699e-05
+  links_utilized_percent_switch_3_link_0: 8.76699e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Control: 414 3312 [ 414 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Data: 256 18432 [ 0 256 0 0 ] base_latency: 1
+
+switch_4_inlinks: 1
+switch_4_outlinks: 1
+links_utilized_percent_switch_4: 6.76394e-05
+  links_utilized_percent_switch_4_link_0: 6.76394e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_Data: 233 16776 [ 0 233 0 0 ] base_latency: 1
+
+switch_5_inlinks: 1
+switch_5_outlinks: 1
+links_utilized_percent_switch_5: 6.21237e-05
+  links_utilized_percent_switch_5_link_0: 6.21237e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Data: 214 15408 [ 0 214 0 0 ] base_latency: 1
+
+switch_6_inlinks: 1
+switch_6_outlinks: 1
+links_utilized_percent_switch_6: 5.9511e-05
+  links_utilized_percent_switch_6_link_0: 5.9511e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Data: 205 14760 [ 0 205 0 0 ] base_latency: 1
+
+switch_7_inlinks: 1
+switch_7_outlinks: 1
+links_utilized_percent_switch_7: 6.09625e-05
+  links_utilized_percent_switch_7_link_0: 6.09625e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Data: 210 15120 [ 0 210 0 0 ] base_latency: 1
+
+switch_8_inlinks: 4
+switch_8_outlinks: 1
+links_utilized_percent_switch_8: 0.000354615
+  links_utilized_percent_switch_8_link_0: 0.000354615 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Data: 1005 72360 [ 0 1005 0 0 ] base_latency: 1
+
+switch_9_inlinks: 4
+switch_9_outlinks: 1
+links_utilized_percent_switch_9: 0.000250237
+  links_utilized_percent_switch_9_link_0: 0.000250237 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Data: 862 62064 [ 0 862 0 0 ] base_latency: 1
+
+switch_10_inlinks: 2
+switch_10_outlinks: 2
+links_utilized_percent_switch_10: 0.000333859
+  links_utilized_percent_switch_10_link_0: 0.000604852 bw: 10000 base_latency: 1
+  links_utilized_percent_switch_10_link_1: 6.28656e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_10_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Data: 1867 134424 [ 0 1867 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+
+switch_11_inlinks: 1
+switch_11_outlinks: 4
+links_utilized_percent_switch_11: 0.000198362
+  links_utilized_percent_switch_11_link_0: 0.000181597 bw: 10000 base_latency: 1
+  links_utilized_percent_switch_11_link_1: 0.000176082 bw: 10000 base_latency: 1
+  links_utilized_percent_switch_11_link_2: 0.000257655 bw: 10000 base_latency: 1
+  links_utilized_percent_switch_11_link_3: 0.000178114 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_11_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_11_link_0_Data: 409 29448 [ 0 409 0 0 ] base_latency: 1
+  outgoing_messages_switch_11_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_11_link_1_Data: 390 28080 [ 0 390 0 0 ] base_latency: 1
+  outgoing_messages_switch_11_link_2_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_11_link_2_Data: 671 48312 [ 0 671 0 0 ] base_latency: 1
+  outgoing_messages_switch_11_link_3_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_11_link_3_Data: 397 28584 [ 0 397 0 0 ] base_latency: 1
+
+switch_12_inlinks: 1
+switch_12_outlinks: 4
+links_utilized_percent_switch_12: 1.57164e-05
+  links_utilized_percent_switch_12_link_0: 2.37399e-05 bw: 10000 base_latency: 1
+  links_utilized_percent_switch_12_link_1: 1.05475e-05 bw: 10000 base_latency: 1
+  links_utilized_percent_switch_12_link_2: 6.87038e-06 bw: 10000 base_latency: 1
+  links_utilized_percent_switch_12_link_3: 2.17078e-05 bw: 10000 base_latency: 1
+
+  outgoing_messages_switch_12_link_0_Control: 736 5888 [ 736 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_12_link_1_Control: 327 2616 [ 327 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_12_link_2_Control: 213 1704 [ 213 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_12_link_3_Control: 673 5384 [ 673 0 0 0 ] base_latency: 1
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load  636
+Ifetch  610
+Store  704
+L1_to_L2  3
+L2_to_L1D  0
+L2_to_L1I  1
+L2_Replacement  0
+Own_GETS  636
+Own_GET_INSTR  609
+Own_GETX  704
+Own_PUTX  0
+Other_GETS  1908
+Other_GET_INSTR  1827
+Other_GETX  2112
+Other_PUTX  0
+Data  1867
+
+ - Transitions -
+NP  Load  130
+NP  Ifetch  609
+NP  Store  147
+NP  Other_GETS  289
+NP  Other_GET_INSTR  1323
+NP  Other_GETX  514
+NP  Other_PUTX  0 <-- 
+
+I  Load  506
+I  Ifetch  0 <-- 
+I  Store  264
+I  L1_to_L2  0 <-- 
+I  L2_to_L1D  0 <-- 
+I  L2_to_L1I  0 <-- 
+I  L2_Replacement  0 <-- 
+I  Other_GETS  765
+I  Other_GET_INSTR  0 <-- 
+I  Other_GETX  796
+I  Other_PUTX  0 <-- 
+
+S  Load  0 <-- 
+S  Ifetch  1
+S  Store  211
+S  L1_to_L2  2
+S  L2_to_L1D  0 <-- 
+S  L2_to_L1I  1
+S  L2_Replacement  0 <-- 
+S  Other_GETS  318
+S  Other_GET_INSTR  504
+S  Other_GETX  333
+S  Other_PUTX  0 <-- 
+
+O  Load  0 <-- 
+O  Ifetch  0 <-- 
+O  Store  82
+O  L1_to_L2  0 <-- 
+O  L2_to_L1D  0 <-- 
+O  L2_to_L1I  0 <-- 
+O  L2_Replacement  0 <-- 
+O  Other_GETS  209
+O  Other_GET_INSTR  0 <-- 
+O  Other_GETX  242
+O  Other_PUTX  0 <-- 
+
+M  Load  0 <-- 
+M  Ifetch  0 <-- 
+M  Store  0 <-- 
+M  L1_to_L2  1
+M  L2_to_L1D  0 <-- 
+M  L2_to_L1I  0 <-- 
+M  L2_Replacement  0 <-- 
+M  Other_GETS  327
+M  Other_GET_INSTR  0 <-- 
+M  Other_GETX  227
+M  Other_PUTX  0 <-- 
+
+IS_AD  Load  0 <-- 
+IS_AD  Ifetch  0 <-- 
+IS_AD  Store  0 <-- 
+IS_AD  L1_to_L2  0 <-- 
+IS_AD  L2_to_L1D  0 <-- 
+IS_AD  L2_to_L1I  0 <-- 
+IS_AD  L2_Replacement  0 <-- 
+IS_AD  Own_GETS  636
+IS_AD  Own_GET_INSTR  609
+IS_AD  Other_GETS  0 <-- 
+IS_AD  Other_GET_INSTR  0 <-- 
+IS_AD  Other_GETX  0 <-- 
+IS_AD  Other_PUTX  0 <-- 
+IS_AD  Data  0 <-- 
+
+IM_AD  Load  0 <-- 
+IM_AD  Ifetch  0 <-- 
+IM_AD  Store  0 <-- 
+IM_AD  L1_to_L2  0 <-- 
+IM_AD  L2_to_L1D  0 <-- 
+IM_AD  L2_to_L1I  0 <-- 
+IM_AD  L2_Replacement  0 <-- 
+IM_AD  Own_GETX  411
+IM_AD  Other_GETS  0 <-- 
+IM_AD  Other_GET_INSTR  0 <-- 
+IM_AD  Other_GETX  0 <-- 
+IM_AD  Other_PUTX  0 <-- 
+IM_AD  Data  0 <-- 
+
+SM_AD  Load  0 <-- 
+SM_AD  Ifetch  0 <-- 
+SM_AD  Store  0 <-- 
+SM_AD  L1_to_L2  0 <-- 
+SM_AD  L2_to_L1D  0 <-- 
+SM_AD  L2_to_L1I  0 <-- 
+SM_AD  L2_Replacement  0 <-- 
+SM_AD  Own_GETX  211
+SM_AD  Other_GETS  0 <-- 
+SM_AD  Other_GET_INSTR  0 <-- 
+SM_AD  Other_GETX  0 <-- 
+SM_AD  Other_PUTX  0 <-- 
+SM_AD  Data  0 <-- 
+
+OM_A  Load  0 <-- 
+OM_A  Ifetch  0 <-- 
+OM_A  Store  0 <-- 
+OM_A  L1_to_L2  0 <-- 
+OM_A  L2_to_L1D  0 <-- 
+OM_A  L2_to_L1I  0 <-- 
+OM_A  L2_Replacement  0 <-- 
+OM_A  Own_GETX  82
+OM_A  Other_GETS  0 <-- 
+OM_A  Other_GET_INSTR  0 <-- 
+OM_A  Other_GETX  0 <-- 
+OM_A  Other_PUTX  0 <-- 
+OM_A  Data  0 <-- 
+
+IS_A  Load  0 <-- 
+IS_A  Ifetch  0 <-- 
+IS_A  Store  0 <-- 
+IS_A  L1_to_L2  0 <-- 
+IS_A  L2_to_L1D  0 <-- 
+IS_A  L2_to_L1I  0 <-- 
+IS_A  L2_Replacement  0 <-- 
+IS_A  Own_GETS  0 <-- 
+IS_A  Own_GET_INSTR  0 <-- 
+IS_A  Other_GETS  0 <-- 
+IS_A  Other_GET_INSTR  0 <-- 
+IS_A  Other_GETX  0 <-- 
+IS_A  Other_PUTX  0 <-- 
+
+IM_A  Load  0 <-- 
+IM_A  Ifetch  0 <-- 
+IM_A  Store  0 <-- 
+IM_A  L1_to_L2  0 <-- 
+IM_A  L2_to_L1D  0 <-- 
+IM_A  L2_to_L1I  0 <-- 
+IM_A  L2_Replacement  0 <-- 
+IM_A  Own_GETX  0 <-- 
+IM_A  Other_GETS  0 <-- 
+IM_A  Other_GET_INSTR  0 <-- 
+IM_A  Other_GETX  0 <-- 
+IM_A  Other_PUTX  0 <-- 
+
+SM_A  Load  0 <-- 
+SM_A  Ifetch  0 <-- 
+SM_A  Store  0 <-- 
+SM_A  L1_to_L2  0 <-- 
+SM_A  L2_to_L1D  0 <-- 
+SM_A  L2_to_L1I  0 <-- 
+SM_A  L2_Replacement  0 <-- 
+SM_A  Own_GETX  0 <-- 
+SM_A  Other_GETS  0 <-- 
+SM_A  Other_GET_INSTR  0 <-- 
+SM_A  Other_GETX  0 <-- 
+SM_A  Other_PUTX  0 <-- 
+
+MI_A  Load  0 <-- 
+MI_A  Ifetch  0 <-- 
+MI_A  Store  0 <-- 
+MI_A  L1_to_L2  0 <-- 
+MI_A  L2_to_L1D  0 <-- 
+MI_A  L2_to_L1I  0 <-- 
+MI_A  L2_Replacement  0 <-- 
+MI_A  Own_PUTX  0 <-- 
+MI_A  Other_GETS  0 <-- 
+MI_A  Other_GET_INSTR  0 <-- 
+MI_A  Other_GETX  0 <-- 
+MI_A  Other_PUTX  0 <-- 
+
+OI_A  Load  0 <-- 
+OI_A  Ifetch  0 <-- 
+OI_A  Store  0 <-- 
+OI_A  L1_to_L2  0 <-- 
+OI_A  L2_to_L1D  0 <-- 
+OI_A  L2_to_L1I  0 <-- 
+OI_A  L2_Replacement  0 <-- 
+OI_A  Own_PUTX  0 <-- 
+OI_A  Other_GETS  0 <-- 
+OI_A  Other_GET_INSTR  0 <-- 
+OI_A  Other_GETX  0 <-- 
+OI_A  Other_PUTX  0 <-- 
+
+II_A  Load  0 <-- 
+II_A  Ifetch  0 <-- 
+II_A  Store  0 <-- 
+II_A  L1_to_L2  0 <-- 
+II_A  L2_to_L1D  0 <-- 
+II_A  L2_to_L1I  0 <-- 
+II_A  L2_Replacement  0 <-- 
+II_A  Own_PUTX  0 <-- 
+II_A  Other_GETS  0 <-- 
+II_A  Other_GET_INSTR  0 <-- 
+II_A  Other_GETX  0 <-- 
+II_A  Other_PUTX  0 <-- 
+
+IS_D  Load  0 <-- 
+IS_D  Ifetch  0 <-- 
+IS_D  Store  0 <-- 
+IS_D  L1_to_L2  0 <-- 
+IS_D  L2_to_L1D  0 <-- 
+IS_D  L2_to_L1I  0 <-- 
+IS_D  L2_Replacement  0 <-- 
+IS_D  Other_GETS  0 <-- 
+IS_D  Other_GET_INSTR  0 <-- 
+IS_D  Other_GETX  0 <-- 
+IS_D  Other_PUTX  0 <-- 
+IS_D  Data  1245
+
+IS_D_I  Load  0 <-- 
+IS_D_I  Ifetch  0 <-- 
+IS_D_I  Store  0 <-- 
+IS_D_I  L1_to_L2  0 <-- 
+IS_D_I  L2_to_L1D  0 <-- 
+IS_D_I  L2_to_L1I  0 <-- 
+IS_D_I  L2_Replacement  0 <-- 
+IS_D_I  Other_GETS  0 <-- 
+IS_D_I  Other_GET_INSTR  0 <-- 
+IS_D_I  Other_GETX  0 <-- 
+IS_D_I  Other_PUTX  0 <-- 
+IS_D_I  Data  0 <-- 
+
+IM_D  Load  0 <-- 
+IM_D  Ifetch  0 <-- 
+IM_D  Store  0 <-- 
+IM_D  L1_to_L2  0 <-- 
+IM_D  L2_to_L1D  0 <-- 
+IM_D  L2_to_L1I  0 <-- 
+IM_D  L2_Replacement  0 <-- 
+IM_D  Other_GETS  0 <-- 
+IM_D  Other_GET_INSTR  0 <-- 
+IM_D  Other_GETX  0 <-- 
+IM_D  Other_PUTX  0 <-- 
+IM_D  Data  411
+
+IM_D_O  Load  0 <-- 
+IM_D_O  Ifetch  0 <-- 
+IM_D_O  Store  0 <-- 
+IM_D_O  L1_to_L2  0 <-- 
+IM_D_O  L2_to_L1D  0 <-- 
+IM_D_O  L2_to_L1I  0 <-- 
+IM_D_O  L2_Replacement  0 <-- 
+IM_D_O  Other_GETS  0 <-- 
+IM_D_O  Other_GET_INSTR  0 <-- 
+IM_D_O  Other_GETX  0 <-- 
+IM_D_O  Other_PUTX  0 <-- 
+IM_D_O  Data  0 <-- 
+
+IM_D_I  Load  0 <-- 
+IM_D_I  Ifetch  0 <-- 
+IM_D_I  Store  0 <-- 
+IM_D_I  L1_to_L2  0 <-- 
+IM_D_I  L2_to_L1D  0 <-- 
+IM_D_I  L2_to_L1I  0 <-- 
+IM_D_I  L2_Replacement  0 <-- 
+IM_D_I  Other_GETS  0 <-- 
+IM_D_I  Other_GET_INSTR  0 <-- 
+IM_D_I  Other_GETX  0 <-- 
+IM_D_I  Other_PUTX  0 <-- 
+IM_D_I  Data  0 <-- 
+
+IM_D_OI  Load  0 <-- 
+IM_D_OI  Ifetch  0 <-- 
+IM_D_OI  Store  0 <-- 
+IM_D_OI  L1_to_L2  0 <-- 
+IM_D_OI  L2_to_L1D  0 <-- 
+IM_D_OI  L2_to_L1I  0 <-- 
+IM_D_OI  L2_Replacement  0 <-- 
+IM_D_OI  Other_GETS  0 <-- 
+IM_D_OI  Other_GET_INSTR  0 <-- 
+IM_D_OI  Other_GETX  0 <-- 
+IM_D_OI  Other_PUTX  0 <-- 
+IM_D_OI  Data  0 <-- 
+
+SM_D  Load  0 <-- 
+SM_D  Ifetch  0 <-- 
+SM_D  Store  0 <-- 
+SM_D  L1_to_L2  0 <-- 
+SM_D  L2_to_L1D  0 <-- 
+SM_D  L2_to_L1I  0 <-- 
+SM_D  L2_Replacement  0 <-- 
+SM_D  Other_GETS  0 <-- 
+SM_D  Other_GET_INSTR  0 <-- 
+SM_D  Other_GETX  0 <-- 
+SM_D  Other_PUTX  0 <-- 
+SM_D  Data  211
+
+SM_D_O  Load  0 <-- 
+SM_D_O  Ifetch  0 <-- 
+SM_D_O  Store  0 <-- 
+SM_D_O  L1_to_L2  0 <-- 
+SM_D_O  L2_to_L1D  0 <-- 
+SM_D_O  L2_to_L1I  0 <-- 
+SM_D_O  L2_Replacement  0 <-- 
+SM_D_O  Other_GETS  0 <-- 
+SM_D_O  Other_GET_INSTR  0 <-- 
+SM_D_O  Other_GETX  0 <-- 
+SM_D_O  Other_PUTX  0 <-- 
+SM_D_O  Data  0 <-- 
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress  0
+GETS  636
+GET_INSTR  609
+GETX  704
+PUTX_Owner  0
+PUTX_NotOwner  0
+
+ - Transitions -
+C  OtherAddress  0 <-- 
+C  GETS  75
+C  GET_INSTR  348
+C  GETX  136
+
+I  GETS  0 <-- 
+I  GET_INSTR  0 <-- 
+I  GETX  0 <-- 
+I  PUTX_NotOwner  0 <-- 
+
+S  GETS  9
+S  GET_INSTR  93
+S  GETX  17
+S  PUTX_NotOwner  0 <-- 
+
+SS  GETS  16
+SS  GET_INSTR  168
+SS  GETX  0 <-- 
+SS  PUTX_NotOwner  0 <-- 
+
+OS  GETS  148
+OS  GET_INSTR  0 <-- 
+OS  GETX  179
+OS  PUTX_Owner  0 <-- 
+OS  PUTX_NotOwner  0 <-- 
+
+OSS  GETS  61
+OSS  GET_INSTR  0 <-- 
+OSS  GETX  145
+OSS  PUTX_Owner  0 <-- 
+OSS  PUTX_NotOwner  0 <-- 
+
+M  GETS  327
+M  GET_INSTR  0 <-- 
+M  GETX  227
+M  PUTX_Owner  0 <-- 
+M  PUTX_NotOwner  0 <-- 
+
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
new file mode 100755
index 000000000..24f1aa5ae
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
@@ -0,0 +1,94 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May  5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May  5 2009 07:34:02
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/SPARC_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+  Processors: 4
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0.  Starting simulation...
+Init done
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 1 completed
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
+Iteration 2 completed
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+Iteration 3 completed
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 4 completed
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 5 completed
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 6 completed
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 7 completed
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+Iteration 8 completed
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 9 completed
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 10 completed
+PASSED :-)
+Exiting @ tick 2480212000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
new file mode 100644
index 000000000..9b90a4abd
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
@@ -0,0 +1 @@
+Skipping for now due to broken atomics in ruby
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
new file mode 100644
index 000000000..977b2c7d7
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
@@ -0,0 +1,33 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                  15492                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 258096                       # Number of bytes of host memory used
+host_seconds                                    39.33                       # Real time elapsed on the host
+host_tick_rate                               63054672                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                      609352                       # Number of instructions simulated
+sim_seconds                                  0.002480                       # Number of seconds simulated
+sim_ticks                                  2480212000                       # Number of ticks simulated
+system.cpu0.idle_fraction                    0.011975                       # Percentage of idle cycles
+system.cpu0.not_idle_fraction                0.988025                       # Percentage of non-idle cycles
+system.cpu0.numCycles                         4944742                       # number of cpu cycles simulated
+system.cpu0.num_insts                          156931                       # Number of instructions executed
+system.cpu0.num_refs                            47256                       # Number of memory references
+system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
+system.cpu1.idle_fraction                    0.012259                       # Percentage of idle cycles
+system.cpu1.not_idle_fraction                0.987741                       # Percentage of non-idle cycles
+system.cpu1.numCycles                         4944666                       # number of cpu cycles simulated
+system.cpu1.num_insts                          152657                       # Number of instructions executed
+system.cpu1.num_refs                            51452                       # Number of memory references
+system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu2.numCycles                         4960424                       # number of cpu cycles simulated
+system.cpu2.num_insts                          146173                       # Number of instructions executed
+system.cpu2.num_refs                            67815                       # Number of memory references
+system.cpu3.idle_fraction                    0.011794                       # Percentage of idle cycles
+system.cpu3.not_idle_fraction                0.988206                       # Percentage of non-idle cycles
+system.cpu3.numCycles                         4944758                       # number of cpu cycles simulated
+system.cpu3.num_insts                          153591                       # Number of instructions executed
+system.cpu3.num_refs                            50671                       # Number of memory references
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
new file mode 100644
index 000000000..ae7e021b5
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -0,0 +1,508 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+mem_mode=timing
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[1]
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dcache dtb icache itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu0.tracer
+workload=system.cpu0.workload
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu0.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.itb]
+type=SparcTLB
+size=64
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu0.workload]
+type=LiveProcess
+cmd=test_atomic 4
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dcache dtb icache itb tracer
+checker=Null
+clock=500
+cpu_id=1
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu1.tracer
+workload=system.cpu0.workload
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.dcache_port
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu1.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu1.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu1.itb]
+type=SparcTLB
+size=64
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu2]
+type=TimingSimpleCPU
+children=dcache dtb icache itb tracer
+checker=Null
+clock=500
+cpu_id=2
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu2.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu2.tracer
+workload=system.cpu0.workload
+dcache_port=system.cpu2.dcache.cpu_side
+icache_port=system.cpu2.icache.cpu_side
+
+[system.cpu2.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.dcache_port
+mem_side=system.toL2Bus.port[6]
+
+[system.cpu2.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu2.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.icache_port
+mem_side=system.toL2Bus.port[5]
+
+[system.cpu2.itb]
+type=SparcTLB
+size=64
+
+[system.cpu2.tracer]
+type=ExeTracer
+
+[system.cpu3]
+type=TimingSimpleCPU
+children=dcache dtb icache itb tracer
+checker=Null
+clock=500
+cpu_id=3
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu3.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu3.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu3.tracer
+workload=system.cpu0.workload
+dcache_port=system.cpu3.dcache.cpu_side
+icache_port=system.cpu3.icache.cpu_side
+
+[system.cpu3.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.dcache_port
+mem_side=system.toL2Bus.port[8]
+
+[system.cpu3.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu3.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.icache_port
+mem_side=system.toL2Bus.port[7]
+
+[system.cpu3.itb]
+type=SparcTLB
+size=64
+
+[system.cpu3.tracer]
+type=ExeTracer
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=4
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[0]
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.mem_side system.system_port system.physmem.port[0]
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[2]
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
new file mode 100755
index 000000000..6f90c0dd1
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -0,0 +1,82 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:33
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Init done
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 1 completed
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
+Iteration 2 completed
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 3 completed
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
+Iteration 4 completed
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 5 completed
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
+Iteration 6 completed
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 7 completed
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+Iteration 8 completed
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 9 completed
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 10 completed
+PASSED :-)
+Exiting @ tick 262298000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
new file mode 100644
index 000000000..0ce3fe3af
--- /dev/null
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -0,0 +1,833 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000262                       # Number of seconds simulated
+sim_ticks                                   262298000                       # Number of ticks simulated
+final_tick                                  262298000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1158712                       # Simulator instruction rate (inst/s)
+host_tick_rate                              458877844                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222944                       # Number of bytes of host memory used
+host_seconds                                     0.57                       # Real time elapsed on the host
+sim_insts                                      662307                       # Number of instructions simulated
+system.physmem.bytes_read                       36608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  22656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          572                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      139566447                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  86375039                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     139566447                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu0.workload.num_syscalls                  89                       # Number of system calls
+system.cpu0.numCycles                          524596                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.num_insts                          158353                       # Number of instructions executed
+system.cpu0.num_int_alu_accesses               109064                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts        25994                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      109064                       # number of integer instructions
+system.cpu0.num_fp_insts                            0                       # number of float instructions
+system.cpu0.num_int_register_reads             315336                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            110671                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                        73905                       # number of memory refs
+system.cpu0.num_load_insts                      48930                       # Number of load instructions
+system.cpu0.num_store_insts                     24975                       # Number of store instructions
+system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
+system.cpu0.num_busy_cycles                    524596                       # Number of busy cycles
+system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.icache.replacements                   215                       # number of replacements
+system.cpu0.icache.tagsinuse               212.479188                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                  157949                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                   467                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                338.220557                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0           212.479188                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.414998                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits                157949                       # number of ReadReq hits
+system.cpu0.icache.demand_hits                 157949                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits                157949                       # number of overall hits
+system.cpu0.icache.ReadReq_misses                 467                       # number of ReadReq misses
+system.cpu0.icache.demand_misses                  467                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses                 467                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency      18524000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency       18524000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency      18524000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses            158416                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses             158416                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses            158416                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate         0.002948                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate          0.002948                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate         0.002948                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency 39665.952891                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency 39665.952891                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency 39665.952891                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks                       0                       # number of writebacks
+system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses            467                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses             467                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses            467                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency     17123000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency     17123000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency     17123000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate     0.002948                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate     0.002948                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate     0.002948                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36665.952891                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 36665.952891                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements                     9                       # number of replacements
+system.cpu0.dcache.tagsinuse               141.233342                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                   56009                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                329.464706                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::0           141.233342                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.275846                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits                 48758                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits                24741                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits                    16                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits                  73499                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits                 73499                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses                 162                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses                183                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses                  26                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses                  345                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses                 345                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency       4749000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency      7175000                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency        387000                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency       11924000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency      11924000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses             48920                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses            24924                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses              73844                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses             73844                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate         0.003312                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate        0.007342                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate         0.619048                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate          0.004672                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate         0.004672                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency 39207.650273                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency 14884.615385                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency 34562.318841                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency 34562.318841                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks                       6                       # number of writebacks
+system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses            162                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses           183                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses             26                       # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses             345                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses            345                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency      4263000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency      6626000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency       309000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency     10889000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency     10889000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate     0.003312                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate     0.007342                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate     0.619048                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate     0.004672                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate     0.004672                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36207.650273                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 11884.615385                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 31562.318841                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 31562.318841                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.numCycles                          524596                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.num_insts                          172325                       # Number of instructions executed
+system.cpu1.num_int_alu_accesses               107932                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts        36203                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                      107932                       # number of integer instructions
+system.cpu1.num_fp_insts                            0                       # number of float instructions
+system.cpu1.num_int_register_reads             249091                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes             92744                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                        47898                       # number of memory refs
+system.cpu1.num_load_insts                      39616                       # Number of load instructions
+system.cpu1.num_store_insts                      8282                       # Number of store instructions
+system.cpu1.num_idle_cycles              68578.001739                       # Number of idle cycles
+system.cpu1.num_busy_cycles              456017.998261                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.869275                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.130725                       # Percentage of idle cycles
+system.cpu1.icache.replacements                   280                       # number of replacements
+system.cpu1.icache.tagsinuse                70.076133                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                  171992                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                469.923497                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::0            70.076133                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.136867                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits                171992                       # number of ReadReq hits
+system.cpu1.icache.demand_hits                 171992                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits                171992                       # number of overall hits
+system.cpu1.icache.ReadReq_misses                 366                       # number of ReadReq misses
+system.cpu1.icache.demand_misses                  366                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses                 366                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency       7920500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency        7920500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency       7920500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses            172358                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses             172358                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses            172358                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate         0.002123                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate          0.002123                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate         0.002123                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency 21640.710383                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency 21640.710383                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency 21640.710383                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks                       0                       # number of writebacks
+system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses            366                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses             366                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses            366                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency      6822000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency      6822000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency      6822000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate     0.002123                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate     0.002123                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate     0.002123                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 18639.344262                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 18639.344262                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 18639.344262                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.replacements                     2                       # number of replacements
+system.cpu1.dcache.tagsinuse                22.703917                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                   18908                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                    31                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                609.935484                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0            26.693562                       # Average occupied blocks per context
+system.cpu1.dcache.occ_blocks::1            -3.989645                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.052136                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::1           -0.007792                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits                 39428                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits                 8099                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits                    18                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits                  47527                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits                 47527                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses                 181                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses                 98                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses                  65                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses                  279                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses                 279                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency       3713000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency      1889000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency        415000                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency        5602000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency       5602000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses             39609                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses             8197                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses                83                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses              47806                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses             47806                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate         0.004570                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate        0.011956                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate         0.783133                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate          0.005836                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate         0.005836                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency 20513.812155                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency 19275.510204                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency  6384.615385                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency 20078.853047                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency 20078.853047                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks                       1                       # number of writebacks
+system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses            181                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses            98                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses             65                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses             279                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses            279                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency      3170000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency      1595000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency       220000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency      4765000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency      4765000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate     0.004570                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate     0.011956                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate     0.783133                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate     0.005836                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate     0.005836                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17513.812155                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16275.510204                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency  3384.615385                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 17078.853047                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 17078.853047                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.numCycles                          524596                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.num_insts                          165499                       # Number of instructions executed
+system.cpu2.num_int_alu_accesses               112355                       # Number of integer alu accesses
+system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
+system.cpu2.num_conditional_control_insts        30582                       # number of instructions that are conditional controls
+system.cpu2.num_int_insts                      112355                       # number of integer instructions
+system.cpu2.num_fp_insts                            0                       # number of float instructions
+system.cpu2.num_int_register_reads             289268                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            110631                       # number of times the integer registers were written
+system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu2.num_mem_refs                        57941                       # number of memory refs
+system.cpu2.num_load_insts                      41852                       # Number of load instructions
+system.cpu2.num_store_insts                     16089                       # Number of store instructions
+system.cpu2.num_idle_cycles              68840.001738                       # Number of idle cycles
+system.cpu2.num_busy_cycles              455755.998262                       # Number of busy cycles
+system.cpu2.not_idle_fraction                0.868775                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                    0.131225                       # Percentage of idle cycles
+system.cpu2.icache.replacements                   280                       # number of replacements
+system.cpu2.icache.tagsinuse                65.601019                       # Cycle average of tags in use
+system.cpu2.icache.total_refs                  165166                       # Total number of references to valid blocks.
+system.cpu2.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
+system.cpu2.icache.avg_refs                451.273224                       # Average number of references to valid blocks.
+system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.occ_blocks::0            65.601019                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.128127                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits                165166                       # number of ReadReq hits
+system.cpu2.icache.demand_hits                 165166                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits                165166                       # number of overall hits
+system.cpu2.icache.ReadReq_misses                 366                       # number of ReadReq misses
+system.cpu2.icache.demand_misses                  366                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses                 366                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency       5648500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency        5648500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency       5648500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses            165532                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses             165532                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses            165532                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate         0.002211                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate          0.002211                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate         0.002211                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency 15433.060109                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency 15433.060109                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency 15433.060109                       # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.icache.writebacks                       0                       # number of writebacks
+system.cpu2.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses            366                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses             366                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses            366                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.icache.ReadReq_mshr_miss_latency      4550500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency      4550500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency      4550500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate     0.002211                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate     0.002211                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate     0.002211                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency 12433.060109                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency 12433.060109                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency 12433.060109                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu2.dcache.replacements                     2                       # number of replacements
+system.cpu2.dcache.tagsinuse                23.305393                       # Cycle average of tags in use
+system.cpu2.dcache.total_refs                   34578                       # Total number of references to valid blocks.
+system.cpu2.dcache.sampled_refs                    31                       # Sample count of references to valid blocks.
+system.cpu2.dcache.avg_refs               1115.419355                       # Average number of references to valid blocks.
+system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.occ_blocks::0            24.943438                       # Average occupied blocks per context
+system.cpu2.dcache.occ_blocks::1            -1.638045                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.048718                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::1           -0.003199                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits                 41688                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits                15916                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits                    11                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits                  57604                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits                 57604                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses                 156                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses                109                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses                  51                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses                  265                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses                 265                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency       2527000                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency      2084000                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency        305000                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency        4611000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency       4611000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses             41844                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses            16025                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses                62                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses              57869                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses             57869                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate         0.003728                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate        0.006802                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate         0.822581                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate          0.004579                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate         0.004579                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency 16198.717949                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency 19119.266055                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency  5980.392157                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency        17400                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency        17400                       # average overall miss latency
+system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.dcache.writebacks                       1                       # number of writebacks
+system.cpu2.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses            156                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses           109                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses             51                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses             265                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses            265                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency      2059000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency      1757000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency       152000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency      3816000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency      3816000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate     0.003728                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate     0.006802                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate     0.822581                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate     0.004579                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate     0.004579                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 13198.717949                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16119.266055                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency  2980.392157                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency        14400                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency        14400                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.numCycles                          524596                       # number of cpu cycles simulated
+system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu3.num_insts                          166130                       # Number of instructions executed
+system.cpu3.num_int_alu_accesses               112098                       # Number of integer alu accesses
+system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
+system.cpu3.num_conditional_control_insts        31024                       # number of instructions that are conditional controls
+system.cpu3.num_int_insts                      112098                       # number of integer instructions
+system.cpu3.num_fp_insts                            0                       # number of float instructions
+system.cpu3.num_int_register_reads             286475                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            109360                       # number of times the integer registers were written
+system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu3.num_mem_refs                        57243                       # number of memory refs
+system.cpu3.num_load_insts                      41720                       # Number of load instructions
+system.cpu3.num_store_insts                     15523                       # Number of store instructions
+system.cpu3.num_idle_cycles              69090.001737                       # Number of idle cycles
+system.cpu3.num_busy_cycles              455505.998263                       # Number of busy cycles
+system.cpu3.not_idle_fraction                0.868299                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                    0.131701                       # Percentage of idle cycles
+system.cpu3.icache.replacements                   281                       # number of replacements
+system.cpu3.icache.tagsinuse                67.737646                       # Cycle average of tags in use
+system.cpu3.icache.total_refs                  165796                       # Total number of references to valid blocks.
+system.cpu3.icache.sampled_refs                   367                       # Sample count of references to valid blocks.
+system.cpu3.icache.avg_refs                451.760218                       # Average number of references to valid blocks.
+system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.occ_blocks::0            67.737646                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.132300                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits                165796                       # number of ReadReq hits
+system.cpu3.icache.demand_hits                 165796                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits                165796                       # number of overall hits
+system.cpu3.icache.ReadReq_misses                 367                       # number of ReadReq misses
+system.cpu3.icache.demand_misses                  367                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses                 367                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency       5531500                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency        5531500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency       5531500                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses            166163                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses             166163                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses            166163                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate         0.002209                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate          0.002209                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate         0.002209                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency 15072.207084                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency 15072.207084                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency 15072.207084                       # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.icache.writebacks                       0                       # number of writebacks
+system.cpu3.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_misses            367                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses             367                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses            367                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.icache.ReadReq_mshr_miss_latency      4430500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency      4430500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency      4430500                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate     0.002209                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate     0.002209                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate     0.002209                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency 12072.207084                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency 12072.207084                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency 12072.207084                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.dcache.replacements                     2                       # number of replacements
+system.cpu3.dcache.tagsinuse                22.083417                       # Cycle average of tags in use
+system.cpu3.dcache.total_refs                   33474                       # Total number of references to valid blocks.
+system.cpu3.dcache.sampled_refs                    32                       # Sample count of references to valid blocks.
+system.cpu3.dcache.avg_refs               1046.062500                       # Average number of references to valid blocks.
+system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.occ_blocks::0            25.684916                       # Average occupied blocks per context
+system.cpu3.dcache.occ_blocks::1            -3.601499                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.050166                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::1           -0.007034                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits                 41555                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits                15348                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits                    11                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits                  56903                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits                 56903                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses                 157                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses                108                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses                  54                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses                  265                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses                 265                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency       2569000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency      2080000                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency        326000                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency        4649000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency       4649000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses             41712                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses            15456                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses                65                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses              57168                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses             57168                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate         0.003764                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate        0.006988                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate         0.830769                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate          0.004635                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate         0.004635                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency 16363.057325                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency 19259.259259                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency  6037.037037                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency 17543.396226                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency 17543.396226                       # average overall miss latency
+system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.dcache.writebacks                       1                       # number of writebacks
+system.cpu3.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses            157                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses           108                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses             54                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses             265                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses            265                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency      2098000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency      1756000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency       164000                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency      3854000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency      3854000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate     0.003764                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate     0.006988                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate     0.830769                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate     0.004635                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate     0.004635                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13363.057325                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16259.259259                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency  3037.037037                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency 14543.396226                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency 14543.396226                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.l2c.replacements                             0                       # number of replacements
+system.l2c.tagsinuse                       353.886259                       # Cycle average of tags in use
+system.l2c.total_refs                            1223                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                           434                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          2.817972                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                   286.079543                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                    57.730360                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                     2.746586                       # Average occupied blocks per context
+system.l2c.occ_blocks::3                     1.731874                       # Average occupied blocks per context
+system.l2c.occ_blocks::4                     5.597896                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.004365                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.000881                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.000042                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.000026                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000085                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                        187                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                        305                       # number of ReadReq hits
+system.l2c.ReadReq_hits::2                        365                       # number of ReadReq hits
+system.l2c.ReadReq_hits::3                        369                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                   1226                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
+system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                       2                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
+system.l2c.demand_hits::0                         187                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                         305                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                         365                       # number of demand (read+write) hits
+system.l2c.demand_hits::3                         369                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                    1226                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                        187                       # number of overall hits
+system.l2c.overall_hits::1                        305                       # number of overall hits
+system.l2c.overall_hits::2                        365                       # number of overall hits
+system.l2c.overall_hits::3                        369                       # number of overall hits
+system.l2c.overall_hits::total                   1226                       # number of overall hits
+system.l2c.ReadReq_misses::0                      351                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                       74                       # number of ReadReq misses
+system.l2c.ReadReq_misses::2                       14                       # number of ReadReq misses
+system.l2c.ReadReq_misses::3                       11                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                  450                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                    28                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                    12                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::2                    16                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::3                    16                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                72                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                     99                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                     15                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::2                     14                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::3                     14                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
+system.l2c.demand_misses::0                       450                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                        89                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                        28                       # number of demand (read+write) misses
+system.l2c.demand_misses::3                        25                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                   592                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                      450                       # number of overall misses
+system.l2c.overall_misses::1                       89                       # number of overall misses
+system.l2c.overall_misses::2                       28                       # number of overall misses
+system.l2c.overall_misses::3                       25                       # number of overall misses
+system.l2c.overall_misses::total                  592                       # number of overall misses
+system.l2c.ReadReq_miss_latency              23330000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency             156000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency             7385000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency               30715000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency              30715000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                    538                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                    379                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2                    379                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::3                    380                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               1676                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                  30                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                  12                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::2                  16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::3                  16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              74                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0                   99                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                   15                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::2                   14                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::3                   14                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                     637                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                     394                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                     393                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::3                     394                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                1818                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                    637                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                    394                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                    393                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::3                    394                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               1818                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.652416                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.195251                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2              0.036939                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3              0.028947                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.913554                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.933333                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       3.933333                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.706436                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.225888                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               0.071247                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::3               0.063452                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           1.067023                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.706436                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.225888                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              0.071247                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::3              0.063452                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          1.067023                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   66467.236467                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   315270.270270                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2   1666428.571429                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3   2120909.090909                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 4169075.169075                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0  5571.428571                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1        13000                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2         9750                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::3         9750                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 38071.428571                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 74595.959596                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 492333.333333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2       527500                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::3       527500                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 1621929.292929                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0    68255.555556                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    345112.359551                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2    1096964.285714                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::3         1228600                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 2738932.200820                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   68255.555556                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   345112.359551                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2   1096964.285714                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::3        1228600                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 2738932.200820                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                               0                       # number of writebacks
+system.l2c.ReadReq_mshr_hits                       20                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits                        20                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                       20                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                    430                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                  72                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses                  142                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                     572                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                    572                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency         17203000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency       2880000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency        5681000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency          22884000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency         22884000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.799257                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         1.134565                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2         1.134565                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::3         1.131579                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     4.199965                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      2.400000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1             6                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2      4.500000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::3      4.500000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total    17.400000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       1.434343                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       9.466667                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2      10.142857                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::3      10.142857                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total    31.186724                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0          0.897959                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.451777                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2          1.455471                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::3          1.451777                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      5.256983                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0         0.897959                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.451777                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2         1.455471                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::3         1.451777                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     5.256983                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40006.976744                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40007.042254                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40006.993007                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40006.993007                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------