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authorNathan Binkert <nate@binkert.org>2012-05-09 11:52:14 -0700
committerNathan Binkert <nate@binkert.org>2012-05-09 11:52:14 -0700
commit4a644767c58754339965cecc5d85853255652a30 (patch)
treee435caa3b1ba7f5e395c58ca0fdfdfa91804d2dd /tests/quick/se/40.m5threads-test-atomic/ref
parent55411f7f713a42f67552a9621051fae8f7869648 (diff)
downloadgem5-4a644767c58754339965cecc5d85853255652a30.tar.xz
stats: update stats for no_value -> nan
Lots of accumulated older changes too.
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref')
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini53
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout8
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt40
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini57
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout8
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt46
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini53
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout8
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt46
9 files changed, 166 insertions, 153 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index bb8df191a..5684cea4e 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
-physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[1]
[system.cpu0]
type=DerivO3CPU
@@ -127,7 +126,7 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -148,7 +147,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
[system.cpu0.dtb]
type=SparcTLB
@@ -419,7 +418,7 @@ opLat=3
[system.cpu0.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -440,7 +439,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=SparcInterrupts
@@ -570,7 +569,7 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -591,7 +590,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
[system.cpu1.dtb]
type=SparcTLB
@@ -862,7 +861,7 @@ opLat=3
[system.cpu1.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -883,7 +882,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
[system.cpu1.interrupts]
type=SparcInterrupts
@@ -994,7 +993,7 @@ icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -1015,7 +1014,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
[system.cpu2.dtb]
type=SparcTLB
@@ -1286,7 +1285,7 @@ opLat=3
[system.cpu2.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -1307,7 +1306,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
[system.cpu2.interrupts]
type=SparcInterrupts
@@ -1418,7 +1417,7 @@ icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -1439,7 +1438,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
[system.cpu3.dtb]
type=SparcTLB
@@ -1710,7 +1709,7 @@ opLat=3
[system.cpu3.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -1731,7 +1730,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
[system.cpu3.interrupts]
type=SparcInterrupts
@@ -1745,7 +1744,7 @@ type=ExeTracer
[system.l2c]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
@@ -1765,8 +1764,8 @@ tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
[system.membus]
type=Bus
@@ -1776,17 +1775,20 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.mem_side system.physmem.port[0] system.system_port
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
[system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
file=
+in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
[system.toL2Bus]
type=Bus
@@ -1796,5 +1798,6 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 84d6c3ee2..9445b3529 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 12 2012 17:18:12
-gem5 started Feb 12 2012 18:18:13
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled May 8 2012 15:05:42
+gem5 started May 8 2012 15:42:58
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index f6ac2f26c..243852286 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000111 # Nu
sim_ticks 111402500 # Number of ticks simulated
final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 189621 # Simulator instruction rate (inst/s)
-host_op_rate 189621 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19396106 # Simulator tick rate (ticks/s)
-host_mem_usage 226052 # Number of bytes of host memory used
-host_seconds 5.74 # Real time elapsed on the host
+host_inst_rate 79928 # Simulator instruction rate (inst/s)
+host_op_rate 79928 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8175729 # Simulator tick rate (ticks/s)
+host_mem_usage 236248 # Number of bytes of host memory used
+host_seconds 13.63 # Real time elapsed on the host
sim_insts 1089093 # Number of instructions simulated
sim_ops 1089093 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 43072 # Number of bytes read from this memory
@@ -329,7 +329,7 @@ system.cpu0.icache.blocked_cycles::no_targets 0
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits
@@ -421,7 +421,7 @@ system.cpu0.dcache.blocked_cycles::no_targets 0
system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks
@@ -774,8 +774,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs 0 #
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 70 # number of ReadReq MSHR hits
@@ -866,8 +866,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs 0 #
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks
@@ -1221,7 +1221,7 @@ system.cpu2.icache.blocked_cycles::no_targets 0
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 72 # number of ReadReq MSHR hits
@@ -1312,8 +1312,8 @@ system.cpu2.dcache.blocked_cycles::no_mshrs 0 #
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
@@ -1666,8 +1666,8 @@ system.cpu3.icache.blocked_cycles::no_mshrs 0 #
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits
@@ -1758,8 +1758,8 @@ system.cpu3.dcache.blocked_cycles::no_mshrs 0 #
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks
@@ -2038,8 +2038,8 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 90b4c4184..a47e5e15d 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
-physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[1]
[system.cpu0]
type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
+fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
@@ -62,7 +62,7 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -83,7 +83,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
[system.cpu0.dtb]
type=SparcTLB
@@ -91,7 +91,7 @@ size=64
[system.cpu0.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -112,7 +112,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=SparcInterrupts
@@ -154,6 +154,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
+fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
@@ -177,7 +178,7 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -198,7 +199,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
[system.cpu1.dtb]
type=SparcTLB
@@ -206,7 +207,7 @@ size=64
[system.cpu1.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -227,7 +228,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
[system.cpu1.interrupts]
type=SparcInterrupts
@@ -250,6 +251,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
+fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu2.interrupts
@@ -273,7 +275,7 @@ icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -294,7 +296,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
[system.cpu2.dtb]
type=SparcTLB
@@ -302,7 +304,7 @@ size=64
[system.cpu2.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -323,7 +325,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
[system.cpu2.interrupts]
type=SparcInterrupts
@@ -346,6 +348,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
+fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu3.interrupts
@@ -369,7 +372,7 @@ icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -390,7 +393,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
[system.cpu3.dtb]
type=SparcTLB
@@ -398,7 +401,7 @@ size=64
[system.cpu3.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -419,7 +422,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
[system.cpu3.interrupts]
type=SparcInterrupts
@@ -433,7 +436,7 @@ type=ExeTracer
[system.l2c]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
@@ -453,8 +456,8 @@ tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
[system.membus]
type=Bus
@@ -464,17 +467,20 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.mem_side system.physmem.port[0] system.system_port
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
[system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
file=
+in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:1073741823
zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
[system.toL2Bus]
type=Bus
@@ -484,5 +490,6 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 4d44fa6f6..ab456df4c 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:55:56
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+gem5 compiled May 8 2012 15:05:42
+gem5 started May 8 2012 15:43:05
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 71dd904a3..e871b4c6b 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu
sim_ticks 87713500 # Number of ticks simulated
final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1664146 # Simulator instruction rate (inst/s)
-host_op_rate 1664073 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 215483439 # Simulator tick rate (ticks/s)
-host_mem_usage 1139232 # Number of bytes of host memory used
-host_seconds 0.41 # Real time elapsed on the host
+host_inst_rate 523852 # Simulator instruction rate (inst/s)
+host_op_rate 523839 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 67834135 # Simulator tick rate (ticks/s)
+host_mem_usage 1149444 # Number of bytes of host memory used
+host_seconds 1.29 # Real time elapsed on the host
sim_insts 677340 # Number of instructions simulated
sim_ops 677340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 35776 # Number of bytes read from this memory
@@ -77,8 +77,8 @@ system.cpu0.icache.blocked_cycles::no_mshrs 0 #
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -130,8 +130,8 @@ system.cpu0.dcache.blocked_cycles::no_mshrs 0 #
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks
@@ -193,8 +193,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs 0 #
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -246,8 +246,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs 0 #
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks
@@ -309,8 +309,8 @@ system.cpu2.icache.blocked_cycles::no_mshrs 0 #
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -362,8 +362,8 @@ system.cpu2.dcache.blocked_cycles::no_mshrs 0 #
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
@@ -425,8 +425,8 @@ system.cpu3.icache.blocked_cycles::no_mshrs 0 #
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -478,8 +478,8 @@ system.cpu3.dcache.blocked_cycles::no_mshrs 0 #
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks
@@ -653,8 +653,8 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index c00589f53..7658e05d6 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
-physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.port[1]
+system_port=system.membus.slave[1]
[system.cpu0]
type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
[system.cpu0.dtb]
type=SparcTLB
@@ -88,7 +87,7 @@ size=64
[system.cpu0.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=SparcInterrupts
@@ -171,7 +170,7 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -192,7 +191,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
[system.cpu1.dtb]
type=SparcTLB
@@ -200,7 +199,7 @@ size=64
[system.cpu1.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -221,7 +220,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
[system.cpu1.interrupts]
type=SparcInterrupts
@@ -264,7 +263,7 @@ icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -285,7 +284,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
[system.cpu2.dtb]
type=SparcTLB
@@ -293,7 +292,7 @@ size=64
[system.cpu2.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -314,7 +313,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
[system.cpu2.interrupts]
type=SparcInterrupts
@@ -357,7 +356,7 @@ icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -378,7 +377,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
[system.cpu3.dtb]
type=SparcTLB
@@ -386,7 +385,7 @@ size=64
[system.cpu3.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -407,7 +406,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
[system.cpu3.interrupts]
type=SparcInterrupts
@@ -421,7 +420,7 @@ type=ExeTracer
[system.l2c]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
@@ -441,8 +440,8 @@ tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
[system.membus]
type=Bus
@@ -452,17 +451,20 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.mem_side system.system_port system.physmem.port[0]
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
[system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
file=
+in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[2]
+port=system.membus.master[0]
[system.toL2Bus]
type=Bus
@@ -472,5 +474,6 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index bd048d482..bd4b2c9b4 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 13:56:07
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+gem5 compiled May 8 2012 15:05:42
+gem5 started May 8 2012 15:43:05
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index fcff65a90..70ef2d753 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000262 # Nu
sim_ticks 262298000 # Number of ticks simulated
final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1330969 # Simulator instruction rate (inst/s)
-host_op_rate 1330920 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 527074583 # Simulator tick rate (ticks/s)
-host_mem_usage 221728 # Number of bytes of host memory used
-host_seconds 0.50 # Real time elapsed on the host
+host_inst_rate 323904 # Simulator instruction rate (inst/s)
+host_op_rate 323899 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 128274037 # Simulator tick rate (ticks/s)
+host_mem_usage 231956 # Number of bytes of host memory used
+host_seconds 2.05 # Real time elapsed on the host
sim_insts 662307 # Number of instructions simulated
sim_ops 662307 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 36608 # Number of bytes read from this memory
@@ -86,8 +86,8 @@ system.cpu0.icache.blocked_cycles::no_mshrs 0 #
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
@@ -172,8 +172,8 @@ system.cpu0.dcache.blocked_cycles::no_mshrs 0 #
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks
@@ -274,8 +274,8 @@ system.cpu1.icache.blocked_cycles::no_mshrs 0 #
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
@@ -360,8 +360,8 @@ system.cpu1.dcache.blocked_cycles::no_mshrs 0 #
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks
@@ -462,8 +462,8 @@ system.cpu2.icache.blocked_cycles::no_mshrs 0 #
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
@@ -548,8 +548,8 @@ system.cpu2.dcache.blocked_cycles::no_mshrs 0 #
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
@@ -650,8 +650,8 @@ system.cpu3.icache.blocked_cycles::no_mshrs 0 #
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
@@ -736,8 +736,8 @@ system.cpu3.dcache.blocked_cycles::no_mshrs 0 #
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks
@@ -1008,8 +1008,8 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits