diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/quick/se/40.m5threads-test-atomic | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic')
| -rwxr-xr-x | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout | 68 | ||||
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 4419 |
2 files changed, 2255 insertions, 2232 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 679d3d472..9368b9f49 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 3 2015 17:16:20 -gem5 started Jul 3 2015 17:20:44 +gem5 compiled Sep 14 2015 22:05:26 +gem5 started Sep 14 2015 22:09:42 gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp @@ -18,33 +18,33 @@ Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 Iteration 3 completed [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 Iteration 4 completed [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 Iteration 5 completed [Iteration 6, Thread 3] Got lock [Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 @@ -53,33 +53,33 @@ Iteration 5 completed [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 Iteration 7 completed -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 Iteration 8 completed -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 Iteration 9 completed -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 107900000 because target called exit() +Exiting @ tick 107049000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 37bdd5ca5..b23c645a0 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,85 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 107900000 # Number of ticks simulated -final_tick 107900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000107 # Number of seconds simulated +sim_ticks 107049000 # Number of ticks simulated +final_tick 107049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161691 # Simulator instruction rate (inst/s) -host_op_rate 161690 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17527940 # Simulator tick rate (ticks/s) -host_mem_usage 308804 # Number of bytes of host memory used -host_seconds 6.16 # Real time elapsed on the host -sim_insts 995346 # Number of instructions simulated -sim_ops 995346 # Number of ops (including micro ops) simulated +host_inst_rate 93620 # Simulator instruction rate (inst/s) +host_op_rate 93620 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10161795 # Simulator tick rate (ticks/s) +host_mem_usage 304708 # Number of bytes of host memory used +host_seconds 10.53 # Real time elapsed on the host +sim_insts 986230 # Number of instructions simulated +sim_ops 986230 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 85 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 671 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 214717331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 100240964 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50417053 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11862836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7710843 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 5338276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7710843 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 397998146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 214717331 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50417053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 5338276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270472660 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 214717331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 100240964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50417053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11862836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7710843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 5338276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7710843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 397998146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 672 # Number of read requests accepted +system.physmem.num_reads::total 665 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 215228540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101037842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49024279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11957141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1793571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7772142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2989285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7772142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 397574942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 215228540 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49024279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1793571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2989285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269035675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 215228540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101037842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49024279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11957141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1793571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7772142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2989285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7772142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 397574942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 666 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 672 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 43008 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 42624 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 43008 # Total read bytes from the system interface side +system.physmem.bytesReadSys 42624 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 75 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 30 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts system.physmem.perBankRdBursts::4 66 # Per bank write bursts -system.physmem.perBankRdBursts::5 28 # Per bank write bursts +system.physmem.perBankRdBursts::5 27 # Per bank write bursts system.physmem.perBankRdBursts::6 18 # Per bank write bursts system.physmem.perBankRdBursts::7 24 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 29 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts -system.physmem.perBankRdBursts::11 14 # Per bank write bursts -system.physmem.perBankRdBursts::12 65 # Per bank write bursts +system.physmem.perBankRdBursts::11 13 # Per bank write bursts +system.physmem.perBankRdBursts::12 61 # Per bank write bursts system.physmem.perBankRdBursts::13 38 # Per bank write bursts -system.physmem.perBankRdBursts::14 17 # Per bank write bursts +system.physmem.perBankRdBursts::14 18 # Per bank write bursts system.physmem.perBankRdBursts::15 97 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -99,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107872000 # Total gap between requests +system.physmem.totGap 107021000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 672 # Read request sizes (log2) +system.physmem.readPktSize::6 666 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -114,11 +120,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -210,966 +216,970 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.744966 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.953250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 233.682770 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 43 28.86% 28.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40 26.85% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25 16.78% 72.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 17 11.41% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8 5.37% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 4.70% 93.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 2.68% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.34% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 2.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 149 # Bytes accessed per row activation -system.physmem.totQLat 7242000 # Total ticks spent queuing -system.physmem.totMemAccLat 19842000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10776.79 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 276.444444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.969078 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 251.786617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 36 25.00% 54.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 19.44% 74.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 8.33% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 4.86% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 5.56% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 1.39% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 2.08% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation +system.physmem.totQLat 6009250 # Total ticks spent queuing +system.physmem.totMemAccLat 18496750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9022.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29526.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 398.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27772.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 398.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 398.59 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 398.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.11 # Data bus utilization in percentage system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 512 # Number of row buffer hits during reads +system.physmem.readRowHits 511 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.19 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.73 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 160523.81 # Average gap between requests -system.physmem.pageHitRate 76.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2776800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 160692.19 # Average gap between requests +system.physmem.pageHitRate 76.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 34825860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30339750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75652080 # Total energy per rank (pJ) -system.physmem_0.averagePower 745.478401 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 52910500 # Time in different power states +system.physmem_0.actBackEnergy 37638810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27872250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75978045 # Total energy per rank (pJ) +system.physmem_0.averagePower 748.690472 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 47858250 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 47852500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 51979250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 31297275 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 33426750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 73998240 # Total energy per rank (pJ) -system.physmem_1.averagePower 729.280213 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 59054500 # Time in different power states +system.physmem_1.actBackEnergy 32994450 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 31946250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 74129175 # Total energy per rank (pJ) +system.physmem_1.averagePower 730.471639 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 55670750 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 42666000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45162250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81516 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78639 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1206 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78220 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75547 # Number of BTB hits +system.cpu0.branchPred.lookups 81022 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78376 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 78355 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75640 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.582715 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 751 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 96.535001 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 215801 # number of cpu cycles simulated +system.cpu0.numCycles 214099 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19984 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 481810 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81516 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76298 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 165347 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 19687 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 478911 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81022 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76285 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 164512 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2206 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 7238 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 188895 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.550676 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.226315 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1992 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 617 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 187540 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.553647 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.214546 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 31263 16.55% 16.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77878 41.23% 57.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 817 0.43% 58.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1146 0.61% 58.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 622 0.33% 59.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 73043 38.67% 97.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 702 0.37% 98.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 447 0.24% 98.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2977 1.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30407 16.21% 16.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77695 41.43% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 798 0.43% 58.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1205 0.64% 58.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 612 0.33% 59.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73095 38.98% 98.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 670 0.36% 98.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 402 0.21% 98.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2656 1.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 188895 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.377737 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.232659 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15795 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18848 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 152228 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 669 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1355 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 470263 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1355 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16424 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2157 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15249 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 152226 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1484 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 466822 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 991 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 319803 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 930944 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 703631 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 305659 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14144 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 901 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4515 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148895 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75333 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72583 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72320 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 390748 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 387435 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 13210 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11146 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 188895 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.051060 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.134423 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 187540 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.378432 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.236867 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15435 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18383 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 151822 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 650 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 468409 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16041 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2079 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14982 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 151818 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1370 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 465227 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 867 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 318145 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 927822 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 700792 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 305063 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13082 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4377 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148776 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75241 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72733 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72329 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 389183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 385745 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 12312 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11729 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 187540 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.056868 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.126403 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34285 18.15% 18.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4265 2.26% 20.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73704 39.02% 59.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73391 38.85% 98.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1671 0.88% 99.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 904 0.48% 99.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 416 0.22% 99.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 183 0.10% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33477 17.85% 17.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4232 2.26% 20.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73531 39.21% 59.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73185 39.02% 98.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1601 0.85% 99.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 889 0.47% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 403 0.21% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 75 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 188895 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 187540 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 90 32.14% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 85 30.36% 62.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 105 37.50% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61 21.11% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 125 43.25% 64.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 164414 42.44% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.44% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 148348 38.29% 80.73% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74673 19.27% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 163127 42.29% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 148129 38.40% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74489 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 387435 # Type of FU issued -system.cpu0.iq.rate 1.795335 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 280 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000723 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 964068 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 404976 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 385522 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 385745 # Type of FU issued +system.cpu0.iq.rate 1.801713 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000749 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 959350 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 402446 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 383893 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 387715 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 386034 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71972 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71845 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2476 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2655 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1617 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2123 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 464714 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148895 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75333 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2043 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 463105 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148776 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75241 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 331 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1444 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 386358 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 148024 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1077 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 990 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1308 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 384734 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 147791 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72999 # number of nop insts executed -system.cpu0.iew.exec_refs 222560 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76623 # Number of branches executed -system.cpu0.iew.exec_stores 74536 # Number of stores executed -system.cpu0.iew.exec_rate 1.790344 # Inst execution rate -system.cpu0.iew.wb_sent 385902 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 385522 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 228646 # num instructions producing a value -system.cpu0.iew.wb_consumers 231982 # num instructions consuming a value +system.cpu0.iew.exec_nop 73033 # number of nop insts executed +system.cpu0.iew.exec_refs 222131 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76355 # Number of branches executed +system.cpu0.iew.exec_stores 74340 # Number of stores executed +system.cpu0.iew.exec_rate 1.796991 # Inst execution rate +system.cpu0.iew.wb_sent 384301 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 383893 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 227714 # num instructions producing a value +system.cpu0.iew.wb_consumers 230757 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.786470 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.985620 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.793063 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986813 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13812 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13101 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1206 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186239 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.420760 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.150366 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 185078 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.431116 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.149204 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34563 18.56% 18.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75593 40.59% 59.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1959 1.05% 60.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 634 0.34% 60.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 503 0.27% 60.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71729 38.51% 99.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 522 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33718 18.22% 18.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75423 40.75% 58.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1935 1.05% 60.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 662 0.36% 60.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 535 0.29% 60.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71534 38.65% 99.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 523 0.28% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186239 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 450840 # Number of instructions committed -system.cpu0.commit.committedOps 450840 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 185078 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 449946 # Number of instructions committed +system.cpu0.commit.committedOps 449946 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 220135 # Number of memory references committed -system.cpu0.commit.loads 146419 # Number of loads committed +system.cpu0.commit.refs 219688 # Number of memory references committed +system.cpu0.commit.loads 146121 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75603 # Number of branches committed +system.cpu0.commit.branches 75454 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 303990 # Number of committed integer instructions. +system.cpu0.commit.int_insts 303394 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72335 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 158286 35.11% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 146503 32.50% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73716 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72186 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 157988 35.11% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 146205 32.49% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73567 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 450840 # Class of committed instruction -system.cpu0.commit.bw_lim_events 486 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 649244 # The number of ROB reads -system.cpu0.rob.rob_writes 931981 # The number of ROB writes -system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26906 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 378421 # Number of Instructions Simulated -system.cpu0.committedOps 378421 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.570267 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.570267 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.753565 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.753565 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 690917 # number of integer regfile reads -system.cpu0.int_regfile_writes 311762 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 449946 # Class of committed instruction +system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 646481 # The number of ROB reads +system.cpu0.rob.rob_writes 928572 # The number of ROB writes +system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26559 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 377676 # Number of Instructions Simulated +system.cpu0.committedOps 377676 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.566885 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.566885 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.764025 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.764025 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 688304 # number of integer regfile reads +system.cpu0.int_regfile_writes 310378 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 224455 # number of misc regfile reads +system.cpu0.misc_regfile_reads 223999 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.011743 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148491 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.054653 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 148243 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 868.368421 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 866.918129 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.011743 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275414 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.054653 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275497 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275497 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 599051 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 599051 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75429 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75429 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73130 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73130 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148559 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148559 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148559 # number of overall hits -system.cpu0.dcache.overall_hits::total 148559 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 540 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 540 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1084 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1084 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1084 # number of overall misses -system.cpu0.dcache.overall_misses::total 1084 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16932500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16932500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35823993 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 35823993 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 460000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 460000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 52756493 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 52756493 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 52756493 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 52756493 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75969 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75969 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73674 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73674 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 598124 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 598124 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75326 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75326 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72968 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72968 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 148294 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 148294 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148294 # number of overall hits +system.cpu0.dcache.overall_hits::total 148294 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 561 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 561 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1118 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1118 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1118 # number of overall misses +system.cpu0.dcache.overall_misses::total 1118 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17156000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17156000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33757980 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 33757980 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 50913980 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 50913980 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 50913980 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 50913980 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75887 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75887 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73525 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73525 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149643 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149643 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 149643 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 149643 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007108 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.007108 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007384 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007384 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007244 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007244 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007244 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007244 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31356.481481 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31356.481481 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65852.928309 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65852.928309 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21904.761905 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 21904.761905 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48668.351476 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 48668.351476 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48668.351476 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 48668.351476 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 149412 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149412 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 149412 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 149412 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007393 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007576 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007576 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007483 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007483 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007483 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007483 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30581.105169 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30581.105169 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60606.786355 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 60606.786355 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 45540.232558 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 45540.232558 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 357 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 357 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 369 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 369 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 726 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 726 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 726 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 726 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 380 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 380 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 758 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 758 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 758 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 758 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6813000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6813000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8643000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8643000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 439000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 439000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15456000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15456000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15456000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15456000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002409 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002375 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002375 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37229.508197 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37229.508197 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 49388.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 49388.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20904.761905 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20904.761905 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43173.184358 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43173.184358 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43173.184358 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43173.184358 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6883000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6883000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8240500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8240500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15123500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15123500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15123500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15123500 # number of overall MSHR miss cycles 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ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40829000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40829000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40829000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40829000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40829000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7238 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7238 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7238 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7238 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7238 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7238 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110390 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110390 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110390 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110390 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110390 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110390 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51100.125156 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 51100.125156 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 51100.125156 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 51100.125156 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.042514 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470786 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.470786 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of 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of overall misses +system.cpu0.icache.overall_misses::total 784 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40365000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40365000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40365000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40365000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40365000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6733 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6733 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6733 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116441 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116441 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51485.969388 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51485.969388 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51485.969388 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51485.969388 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR 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accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084968 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084968 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51416.260163 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 176 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 176 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 176 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 176 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 176 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 176 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31177000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31177000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31177000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31177000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31177000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31177000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51277.960526 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 53963 # Number of BP lookups -system.cpu1.branchPred.condPredicted 50167 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1346 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46229 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 44971 # Number of BTB hits +system.cpu1.branchPred.lookups 50039 # Number of BP lookups +system.cpu1.branchPred.condPredicted 46665 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 42823 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 41749 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.278764 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 927 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.492002 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 914 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 162372 # number of cpu cycles simulated +system.cpu1.numCycles 161348 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 29926 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 299894 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53963 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 45898 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 123960 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2845 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.icacheStallCycles 31303 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 275372 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 50039 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 42663 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 121719 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1155 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 20576 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 156476 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.916550 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.231802 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps +system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 21928 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 155480 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.771109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.178899 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 52995 33.87% 33.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 51987 33.22% 67.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5834 3.73% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3448 2.20% 73.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 958 0.61% 73.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 34873 22.29% 95.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1256 0.80% 96.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 838 0.54% 97.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4287 2.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 58088 37.36% 37.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 49421 31.79% 69.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6835 4.40% 73.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3518 2.26% 75.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 944 0.61% 76.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 30727 19.76% 96.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1228 0.79% 96.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 804 0.52% 97.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3915 2.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 156476 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.332342 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.846956 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 18007 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50929 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 83026 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3082 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1422 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 283749 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1422 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18719 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22929 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13387 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 84356 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 15653 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 280426 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 13898 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 155480 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.310131 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.706696 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17833 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 58352 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 74506 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3430 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1349 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 260078 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1349 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18539 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 27109 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13862 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 76429 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 18182 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 256857 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 16651 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 198372 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 540599 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 420692 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 183271 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15101 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1203 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1280 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 20103 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 79058 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 37890 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 37399 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 32713 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 233810 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5671 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 234514 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 14000 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11968 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 653 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 156476 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.498722 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.383815 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 180872 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 489824 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 382391 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 167019 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13853 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 22657 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 71171 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 33454 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 33920 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 28372 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 213121 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6586 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 214969 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13076 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 730 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 155480 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.382615 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.383057 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 56669 36.22% 36.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 19562 12.50% 48.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 37085 23.70% 72.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 36801 23.52% 95.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3420 2.19% 98.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1602 1.02% 99.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 884 0.56% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 239 0.15% 99.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 214 0.14% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 61906 39.82% 39.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 21977 14.13% 53.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 32894 21.16% 75.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 32429 20.86% 95.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3365 2.16% 98.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1605 1.03% 99.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 896 0.58% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 208 0.13% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 156476 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 155480 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 87 24.58% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 58 16.38% 40.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 59.04% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 79 23.72% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 45 13.51% 37.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 114757 48.93% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 82569 35.21% 84.14% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37188 15.86% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 106597 49.59% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 75532 35.14% 84.72% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 32840 15.28% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 234514 # Type of FU issued -system.cpu1.iq.rate 1.444301 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 354 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001510 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 625904 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 253521 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 232777 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 214969 # Type of FU issued +system.cpu1.iq.rate 1.332331 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 333 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001549 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 585768 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 232822 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 213429 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 234868 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 215302 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 32465 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 28182 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2830 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1669 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1503 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1422 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6958 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 277649 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 222 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 79058 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 37890 # Number of dispatched store instructions +system.cpu1.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7989 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 254448 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 71171 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 33454 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 481 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1587 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 233397 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 77941 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1117 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1051 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 213962 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 70077 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1007 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 38168 # number of nop insts executed -system.cpu1.iew.exec_refs 115010 # number of memory reference insts executed -system.cpu1.iew.exec_branches 47577 # Number of branches executed -system.cpu1.iew.exec_stores 37069 # Number of stores executed -system.cpu1.iew.exec_rate 1.437421 # Inst execution rate -system.cpu1.iew.wb_sent 233106 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 232777 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 132706 # num instructions producing a value -system.cpu1.iew.wb_consumers 139339 # num instructions consuming a value +system.cpu1.iew.exec_nop 34741 # number of nop insts executed +system.cpu1.iew.exec_refs 102825 # number of memory reference insts executed +system.cpu1.iew.exec_branches 44094 # Number of branches executed +system.cpu1.iew.exec_stores 32748 # Number of stores executed +system.cpu1.iew.exec_rate 1.326090 # Inst execution rate +system.cpu1.iew.wb_sent 213711 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 213429 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 120431 # num instructions producing a value +system.cpu1.iew.wb_consumers 127039 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.433603 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.952397 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.322787 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.947984 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14853 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5018 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1346 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 153761 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.708866 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.078798 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13922 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5856 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 152910 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.572631 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.035068 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61362 39.91% 39.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 44235 28.77% 68.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5219 3.39% 72.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5854 3.81% 75.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1519 0.99% 76.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 32513 21.15% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 819 0.53% 98.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 953 0.62% 99.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1287 0.84% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 67472 44.13% 44.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 40678 26.60% 70.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5251 3.43% 74.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6680 4.37% 78.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1520 0.99% 79.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 28236 18.47% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 823 0.54% 98.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 947 0.62% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1303 0.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 153761 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 262757 # Number of instructions committed -system.cpu1.commit.committedOps 262757 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 152910 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 240471 # Number of instructions committed +system.cpu1.commit.committedOps 240471 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 112449 # Number of memory references committed -system.cpu1.commit.loads 76228 # Number of loads committed -system.cpu1.commit.membars 4303 # Number of memory barriers committed -system.cpu1.commit.branches 46487 # Number of branches committed +system.cpu1.commit.refs 100469 # Number of memory references committed +system.cpu1.commit.loads 68518 # Number of loads committed +system.cpu1.commit.membars 5139 # Number of memory barriers committed +system.cpu1.commit.branches 43053 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 181057 # Number of committed integer instructions. +system.cpu1.commit.int_insts 165641 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 37276 14.19% 14.19% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 108729 41.38% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.57% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 80531 30.65% 86.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 36221 13.78% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 33840 14.07% 14.07% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 101023 42.01% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.08% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 73657 30.63% 86.71% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 31951 13.29% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 262757 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1287 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 429498 # The number of ROB reads -system.cpu1.rob.rob_writes 557934 # The number of ROB writes -system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5896 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 46085 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 221178 # Number of Instructions Simulated -system.cpu1.committedOps 221178 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.734124 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.734124 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.362168 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.362168 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 405088 # number of integer regfile reads -system.cpu1.int_regfile_writes 189742 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 240471 # Class of committed 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regfile reads +system.cpu1.int_regfile_writes 172947 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 116634 # number of misc regfile reads +system.cpu1.misc_regfile_reads 104453 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.592984 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 42361 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1512.892857 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.714463 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 38066 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1312.620690 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.592984 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049986 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.049986 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.714463 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050224 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050224 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 326938 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 326938 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 44990 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 44990 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 35982 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 35982 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 80972 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 80972 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 80972 # number of overall hits -system.cpu1.dcache.overall_hits::total 80972 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 461 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 461 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 170 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 170 # number of WriteReq misses +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 295559 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 295559 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 41369 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41369 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 31720 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 31720 # number of WriteReq hits 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overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 81603 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010143 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.010143 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004702 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004702 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007733 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007733 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007733 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007733 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18888.286334 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 18888.286334 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24835.294118 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24835.294118 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11651.785714 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 11651.785714 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20490.491284 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20490.491284 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20490.491284 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20490.491284 # average overall miss latency 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for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.009003 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19382.936508 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19382.936508 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21059.375000 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21059.375000 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12383.928571 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 12383.928571 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19786.897590 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19786.897590 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1178,518 +1188,517 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 303 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 303 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 62 # number of WriteReq MSHR hits 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WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 385 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 385 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 385 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 385 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 596500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 596500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3884000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3884000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3884000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3884000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003476 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003476 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002987 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002987 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003260 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003260 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003260 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003260 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.379747 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12180.379747 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18143.518519 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18143.518519 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10651.785714 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10651.785714 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14601.503759 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14601.503759 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14601.503759 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14601.503759 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2195000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2195000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1746000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1746000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 637500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 637500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3941000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3941000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3941000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3941000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004108 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004108 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003356 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003356 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.788732 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003783 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003783 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12761.627907 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12761.627907 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16317.757009 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16317.757009 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11383.928571 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11383.928571 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 385 # number of replacements -system.cpu1.icache.tags.tagsinuse 85.488179 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19990 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.980000 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 383 # number of replacements +system.cpu1.icache.tags.tagsinuse 84.275379 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 21349 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 43.042339 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 85.488179 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.166969 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.166969 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 115 # Occupied blocks per task id +system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.275379 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164600 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.164600 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.224609 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21076 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21076 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 19990 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19990 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19990 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19990 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19990 # number of overall hits -system.cpu1.icache.overall_hits::total 19990 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 586 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 586 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 586 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 586 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 586 # number of overall misses -system.cpu1.icache.overall_misses::total 586 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14253000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 14253000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 14253000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 14253000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 14253000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 14253000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20576 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20576 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20576 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20576 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20576 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20576 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028480 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.028480 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028480 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.028480 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028480 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.028480 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24322.525597 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24322.525597 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24322.525597 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24322.525597 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked +system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 22424 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 22424 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 21349 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 21349 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 21349 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 21349 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 21349 # number of overall hits +system.cpu1.icache.overall_hits::total 21349 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 579 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 579 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 579 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 579 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 579 # number of overall misses +system.cpu1.icache.overall_misses::total 579 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13955500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 13955500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 13955500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 13955500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 13955500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 13955500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21928 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21928 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21928 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21928 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21928 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21928 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026405 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.026405 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026405 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.026405 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026405 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.026405 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24102.763385 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24102.763385 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24102.763385 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24102.763385 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 86 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 86 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 86 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 86 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 500 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 500 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 500 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11778500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11778500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11778500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11778500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11778500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11778500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024300 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024300 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024300 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23557 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23557 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 83 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 83 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 83 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 83 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11502500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11502500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11502500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11502500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11502500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11502500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022619 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022619 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022619 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23190.524194 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 40179 # Number of BP lookups -system.cpu2.branchPred.condPredicted 36730 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1284 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 32851 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 31814 # Number of BTB hits +system.cpu2.branchPred.lookups 42880 # Number of BP lookups +system.cpu2.branchPred.condPredicted 39445 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1259 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 35521 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 34492 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 96.843323 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 891 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.103122 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 162000 # number of cpu cycles simulated +system.cpu2.numCycles 160976 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 38502 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 208114 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 40179 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 32705 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 119095 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2725 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 36449 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 226588 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 42880 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 35396 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 120624 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1151 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 29772 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 430 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 160123 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.299713 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.967894 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1157 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 27680 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 159581 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.419893 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.036694 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 78817 49.22% 49.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 43234 27.00% 76.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 10666 6.66% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3447 2.15% 85.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1063 0.66% 85.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 17019 10.63% 96.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1193 0.75% 97.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 770 0.48% 97.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3914 2.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 73772 46.23% 46.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 45044 28.23% 74.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 9695 6.08% 80.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3476 2.18% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 968 0.61% 83.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 20661 12.95% 96.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1186 0.74% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 799 0.50% 97.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3980 2.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 160123 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.248019 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.284654 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17927 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 88037 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 47537 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5250 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1362 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 193193 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1362 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18611 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 44936 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13295 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 49321 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 32588 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 189743 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 29082 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 12 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 159581 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.266375 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.407589 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17760 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 80804 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 54882 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4787 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1338 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 211151 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1338 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18439 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 40468 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13548 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 56825 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 28953 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 208031 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 26065 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 129905 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 340650 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 270570 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 115581 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 14324 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1221 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1285 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 37412 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 47453 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 19802 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 23979 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 14667 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 152040 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 10334 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 157175 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13577 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11994 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.rename.RenamedOperands 143630 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 381000 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 300757 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 129882 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13748 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1262 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 33404 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 53977 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 23458 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 26723 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 18373 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 168634 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 9408 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 173236 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 12983 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10808 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 160123 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.981589 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.305622 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::samples 159581 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.085568 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.335871 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 83163 51.94% 51.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 32837 20.51% 72.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 19129 11.95% 84.39% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 18742 11.70% 96.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3350 2.09% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1588 0.99% 99.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 888 0.55% 99.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 204 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 77748 48.72% 48.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 30232 18.94% 67.66% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 22868 14.33% 81.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 22470 14.08% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3364 2.11% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1606 1.01% 99.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 879 0.55% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 214 0.13% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 160123 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 159581 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 85 23.42% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 69 19.01% 42.42% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 79 23.94% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 42 12.73% 36.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 82729 52.63% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.63% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 55347 35.21% 87.85% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 19099 12.15% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 89318 51.56% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.56% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 61054 35.24% 86.80% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 22864 13.20% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 157175 # Type of FU issued -system.cpu2.iq.rate 0.970216 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.002310 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 474890 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 175995 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 155491 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 173236 # Type of FU issued +system.cpu2.iq.rate 1.076160 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 330 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001905 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 506398 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 191064 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 171727 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 157538 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 173566 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 14398 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 18193 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2822 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1616 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1362 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 11555 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 187117 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 206 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 47453 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 19802 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1131 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10563 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 81 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 205567 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 53977 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 23458 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1137 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 462 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1028 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1490 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 156065 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 46210 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1110 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1053 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1483 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 172231 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 52840 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1005 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 24743 # number of nop insts executed -system.cpu2.iew.exec_refs 65197 # number of memory reference insts executed -system.cpu2.iew.exec_branches 33975 # Number of branches executed -system.cpu2.iew.exec_stores 18987 # Number of stores executed -system.cpu2.iew.exec_rate 0.963364 # Inst execution rate -system.cpu2.iew.wb_sent 155796 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 155491 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 82775 # num instructions producing a value -system.cpu2.iew.wb_consumers 89322 # num instructions consuming a value +system.cpu2.iew.exec_nop 27525 # number of nop insts executed +system.cpu2.iew.exec_refs 75615 # number of memory reference insts executed +system.cpu2.iew.exec_branches 36863 # Number of branches executed +system.cpu2.iew.exec_stores 22775 # Number of stores executed +system.cpu2.iew.exec_rate 1.069917 # Inst execution rate +system.cpu2.iew.wb_sent 171997 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 171727 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 93200 # num instructions producing a value +system.cpu2.iew.wb_consumers 99800 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.959821 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.926703 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.066786 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.933868 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14525 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9553 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1284 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 157478 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.095639 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.783689 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 13823 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 8627 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1259 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 157016 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.220837 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.865055 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 92218 58.56% 58.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 30640 19.46% 78.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5207 3.31% 81.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 10311 6.55% 87.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1532 0.97% 88.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 14554 9.24% 98.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 759 0.48% 98.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 956 0.61% 99.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1301 0.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 86039 54.80% 54.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 33434 21.29% 76.09% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5238 3.34% 79.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 9429 6.01% 85.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1533 0.98% 86.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 18255 11.63% 98.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 831 0.53% 98.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1302 0.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 157478 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 172539 # Number of instructions committed -system.cpu2.commit.committedOps 172539 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 157016 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 191691 # Number of instructions committed +system.cpu2.commit.committedOps 191691 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 62817 # Number of memory references committed -system.cpu2.commit.loads 44631 # Number of loads committed -system.cpu2.commit.membars 8825 # Number of memory barriers committed -system.cpu2.commit.branches 32966 # Number of branches committed +system.cpu2.commit.refs 73311 # Number of memory references committed +system.cpu2.commit.loads 51335 # Number of loads committed +system.cpu2.commit.membars 7910 # Number of memory barriers committed +system.cpu2.commit.branches 35845 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 117894 # Number of committed integer instructions. +system.cpu2.commit.int_insts 131277 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 23742 13.76% 13.76% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 77155 44.72% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 58.48% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 53456 30.98% 89.46% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 18186 10.54% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 26632 13.89% 13.89% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 83838 43.74% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 59245 30.91% 88.54% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 21976 11.46% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 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CPI of All Threads -system.cpu2.ipc 0.864025 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.864025 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 255225 # number of integer regfile reads -system.cpu2.int_regfile_writes 121437 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 191691 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1302 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 360642 # The number of ROB reads +system.cpu2.rob.rob_writes 413593 # The number of ROB writes +system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1395 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 157149 # Number of Instructions Simulated +system.cpu2.committedOps 157149 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.024353 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.024353 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.976226 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.976226 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 286558 # number of integer regfile reads +system.cpu2.int_regfile_writes 135654 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 66781 # number of misc regfile reads +system.cpu2.misc_regfile_reads 77226 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 23.055357 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 24315 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 838.448276 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 23.071332 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 27978 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 999.214286 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.055357 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045030 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.045030 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per 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18041.237113 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18041.237113 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 9923.076923 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 9923.076923 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12638.376384 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12638.376384 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12638.376384 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12638.376384 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits 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of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 275 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 275 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1811500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1811500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1702500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1702500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 619500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 619500 # number of SwapReq MSHR miss cycles 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for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004865 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004865 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10531.976744 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10531.976744 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16529.126214 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16529.126214 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11913.461538 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11913.461538 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.tags.replacements 387 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.683777 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 29208 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 58.887097 # Average number of references to valid blocks. +system.cpu2.icache.tags.replacements 386 # number of replacements +system.cpu2.icache.tags.tagsinuse 77.667456 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 27109 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 54.218000 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.683777 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.145867 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.145867 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id +system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.667456 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151694 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.151694 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 30268 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 30268 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 29208 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 29208 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 29208 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 29208 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 29208 # number of overall hits -system.cpu2.icache.overall_hits::total 29208 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 564 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 564 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 564 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 564 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 564 # number of overall misses -system.cpu2.icache.overall_misses::total 564 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7822000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7822000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7822000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7822000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7822000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7822000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 29772 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 29772 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 29772 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 29772 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 29772 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 29772 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018944 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.018944 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018944 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.018944 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018944 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.018944 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13868.794326 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13868.794326 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13868.794326 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13868.794326 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13868.794326 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13868.794326 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 28180 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 28180 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 27109 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 27109 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 27109 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 27109 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 27109 # number of overall hits +system.cpu2.icache.overall_hits::total 27109 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 571 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 571 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 571 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 571 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 571 # number of overall misses +system.cpu2.icache.overall_misses::total 571 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7541500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7541500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7541500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7541500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7541500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7541500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 27680 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 27680 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 27680 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 27680 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 27680 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 27680 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020629 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.020629 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020629 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.020629 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020629 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.020629 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13207.530648 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13207.530648 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13207.530648 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13207.530648 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 496 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 496 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 496 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 496 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6709500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6709500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6709500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6709500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6709500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6709500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.016660 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.016660 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.016660 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13527.217742 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 71 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 71 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 71 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6543500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6543500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6543500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6543500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6543500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6543500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.018064 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.018064 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.018064 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13087 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13087 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 59537 # Number of BP lookups -system.cpu3.branchPred.condPredicted 56113 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1261 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 52336 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 51268 # Number of BTB hits +system.cpu3.branchPred.lookups 58611 # Number of BP lookups +system.cpu3.branchPred.condPredicted 55067 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 51125 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 50131 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.959340 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 894 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.055746 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 161647 # number of cpu cycles simulated +system.cpu3.numCycles 160611 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 26901 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 335954 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 59537 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 52162 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 130682 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2681 # Number of cycles fetch has spent squashing -system.cpu3.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.icacheStallCycles 27021 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 330369 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 58611 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 51037 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 129883 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2715 # Number of cycles fetch has spent squashing +system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps -system.cpu3.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 18139 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 423 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 160153 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 2.097707 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.240976 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 18269 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 159439 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 2.072071 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.246890 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 45773 28.58% 28.58% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 56940 35.55% 64.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 4846 3.03% 67.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3496 2.18% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1060 0.66% 70.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 42180 26.34% 96.34% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1201 0.75% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 768 0.48% 97.57% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3889 2.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 47077 29.53% 29.53% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 55913 35.07% 64.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 4932 3.09% 67.69% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3522 2.21% 69.90% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 934 0.59% 70.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 40952 25.69% 96.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1272 0.80% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 798 0.50% 97.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 4039 2.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 160153 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.368315 # Number of branch fetches per cycle -system.cpu3.fetch.rate 2.078319 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 16971 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 42083 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 97172 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 2577 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1340 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 322134 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1340 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 17645 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 17747 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12855 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 98257 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 12299 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 318864 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 10783 # Number of times rename has blocked due to IQ full +system.cpu3.fetch.rateDist::total 159439 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.364925 # Number of branch fetches per cycle +system.cpu3.fetch.rate 2.056951 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 16993 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 43740 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 94729 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 2610 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1357 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 315004 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1357 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 17735 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 17944 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 14128 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 95562 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 12703 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 311495 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 10931 # Number of times rename has blocked due to IQ full system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 225541 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 621446 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 481213 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 211532 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14009 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1171 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16730 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 92339 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 45060 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 43467 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 39931 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 267326 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 4600 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 267770 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12807 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10139 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 551 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 160153 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.671964 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.354316 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 220426 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 606441 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 469854 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 206787 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 13639 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1207 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 17457 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 89942 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 43802 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 42282 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 38692 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 261084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 4750 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 261694 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12498 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 9712 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 614 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 159439 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.641342 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.359128 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 48755 30.44% 30.44% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 16655 10.40% 40.84% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 44376 27.71% 68.55% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 43948 27.44% 95.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3484 2.18% 98.17% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1651 1.03% 99.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 50249 31.52% 31.52% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 16842 10.56% 42.08% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 43259 27.13% 69.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 42799 26.84% 96.05% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3393 2.13% 98.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1616 1.01% 99.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 876 0.55% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 194 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 160153 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 159439 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 86 25.67% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 40 11.94% 37.61% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 81 26.21% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.21% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 19 6.15% 32.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 67.64% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 128178 47.87% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 95149 35.53% 83.40% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 44443 16.60% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 125700 48.03% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 92778 35.45% 83.49% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 43216 16.51% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 267770 # Type of FU issued -system.cpu3.iq.rate 1.656511 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 335 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001251 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 696028 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 284773 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 266078 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 261694 # Type of FU issued +system.cpu3.iq.rate 1.629365 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 683137 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 278366 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 260191 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 268105 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 262003 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 39763 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 38539 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2450 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1547 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1484 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1340 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 5357 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 316296 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 170 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 92339 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 45060 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1357 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 5389 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 51 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 309030 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 159 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 89942 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 43802 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1001 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1467 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 266621 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 91475 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1149 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 441 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1075 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1516 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 260676 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 89042 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1018 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 44370 # number of nop insts executed -system.cpu3.iew.exec_refs 135810 # number of memory reference insts executed -system.cpu3.iew.exec_branches 53906 # Number of branches executed -system.cpu3.iew.exec_stores 44335 # Number of stores executed -system.cpu3.iew.exec_rate 1.649403 # Inst execution rate -system.cpu3.iew.wb_sent 266372 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 266078 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 153535 # num instructions producing a value -system.cpu3.iew.wb_consumers 160065 # num instructions consuming a value +system.cpu3.iew.exec_nop 43196 # number of nop insts executed +system.cpu3.iew.exec_refs 132177 # number of memory reference insts executed +system.cpu3.iew.exec_branches 52784 # Number of branches executed +system.cpu3.iew.exec_stores 43135 # Number of stores executed +system.cpu3.iew.exec_rate 1.623027 # Inst execution rate +system.cpu3.iew.wb_sent 260451 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 260191 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 149829 # num instructions producing a value +system.cpu3.iew.wb_consumers 156442 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.646044 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.959204 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.620007 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.957729 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 13497 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 4049 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1261 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 157643 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.920440 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.127029 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 13144 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 4136 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 156952 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.884863 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.121598 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 52663 33.41% 33.41% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 50442 32.00% 65.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5240 3.32% 68.73% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 4903 3.11% 71.84% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1534 0.97% 72.81% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 39716 25.19% 98.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 903 0.57% 98.58% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 957 0.61% 99.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1285 0.82% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 54210 34.54% 34.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 49323 31.43% 65.96% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5280 3.36% 69.33% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 4930 3.14% 72.47% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1531 0.98% 73.45% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 38585 24.58% 98.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 839 0.53% 98.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1299 0.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 157643 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 302744 # Number of instructions committed -system.cpu3.commit.committedOps 302744 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 156952 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 295833 # Number of instructions committed +system.cpu3.commit.committedOps 295833 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 133402 # Number of memory references committed -system.cpu3.commit.loads 89889 # Number of loads committed -system.cpu3.commit.membars 3344 # Number of memory barriers committed -system.cpu3.commit.branches 52826 # Number of branches committed +system.cpu3.commit.refs 129866 # Number of memory references committed +system.cpu3.commit.loads 87548 # Number of loads committed +system.cpu3.commit.membars 3423 # Number of memory barriers committed +system.cpu3.commit.branches 51706 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 208356 # Number of committed integer instructions. +system.cpu3.commit.int_insts 203693 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 43625 14.41% 14.41% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 122373 40.42% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.83% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 93233 30.80% 85.63% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 43513 14.37% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 42497 14.37% 14.37% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 120047 40.58% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.94% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 90971 30.75% 85.70% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 42318 14.30% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 302744 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1285 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 472013 # The number of ROB reads -system.cpu3.rob.rob_writes 634991 # The number of ROB writes -system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1494 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 46809 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 255775 # Number of Instructions Simulated -system.cpu3.committedOps 255775 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.631989 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.631989 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.582306 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.582306 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 467282 # number of integer regfile reads -system.cpu3.int_regfile_writes 217631 # number of integer regfile writes +system.cpu3.commit.op_class_0::total 295833 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1299 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 464044 # The number of ROB reads +system.cpu3.rob.rob_writes 620441 # The number of ROB writes +system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1172 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 249913 # Number of Instructions Simulated +system.cpu3.committedOps 249913 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.642668 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.642668 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.556014 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.556014 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 456401 # number of integer regfile reads +system.cpu3.int_regfile_writes 212686 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 137439 # number of misc regfile reads +system.cpu3.misc_regfile_reads 133817 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.171664 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 49547 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.217896 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 48316 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1769.535714 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1725.571429 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.171664 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047210 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047210 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.217896 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047301 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047301 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 381069 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 381069 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 51168 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 51168 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 43290 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 43290 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 10 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 94458 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 94458 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 94458 # number of overall hits -system.cpu3.dcache.overall_hits::total 94458 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 527 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 527 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 164 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 164 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 49 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 49 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 691 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 691 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 691 # number of overall misses -system.cpu3.dcache.overall_misses::total 691 # number of overall misses +system.cpu3.dcache.tags.tag_accesses 371433 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 371433 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 49959 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 49959 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 42098 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 42098 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 92057 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 92057 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 92057 # number of overall hits +system.cpu3.dcache.overall_hits::total 92057 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 521 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 521 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 153 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 153 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses 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number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 11299000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 11299000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 11299000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 51695 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 51695 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 43454 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 43454 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 59 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 59 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 95149 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 95149 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 95149 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 95149 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010194 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010194 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003774 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003774 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830508 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.830508 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007262 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007262 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007262 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007262 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15325.426945 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 15325.426945 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19649.390244 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19649.390244 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12397.959184 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 12397.959184 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16351.664255 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 16351.664255 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16351.664255 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 16351.664255 # average overall miss latency +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3408500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3408500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 574500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 574500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11485000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11485000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11485000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11485000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 50480 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 50480 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 42251 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 42251 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 92731 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 92731 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 92731 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 92731 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010321 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.010321 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003621 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003621 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805970 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007268 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007268 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007268 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007268 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15501.919386 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15501.919386 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22277.777778 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 22277.777778 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10638.888889 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 10638.888889 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17040.059347 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17040.059347 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2217,389 +2226,391 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 382 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 434 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 434 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 434 # 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-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12013.618677 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12013.618677 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12013.618677 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1413000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1413000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2020500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2020500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 520500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 520500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3433500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3433500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3433500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3433500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003011 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003011 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002485 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002485 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805970 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805970 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.002771 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.002771 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9296.052632 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9296.052632 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19242.857143 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19242.857143 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9638.888889 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9638.888889 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.tags.replacements 388 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.972544 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 17573 # Total number of references to valid blocks. +system.cpu3.icache.tags.replacements 384 # number of replacements +system.cpu3.icache.tags.tagsinuse 80.866510 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 17696 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 35.287149 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 35.534137 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.972544 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.152290 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.152290 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.866510 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157942 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.157942 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 18637 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 18637 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 17573 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 17573 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 17573 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 17573 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 17573 # number of overall hits -system.cpu3.icache.overall_hits::total 17573 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 566 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 566 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 566 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 566 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 566 # number of overall misses -system.cpu3.icache.overall_misses::total 566 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7887000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7887000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7887000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7887000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7887000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7887000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 18139 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 18139 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 18139 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 18139 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 18139 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 18139 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.031203 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.031203 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.031203 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.031203 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.031203 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.031203 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13934.628975 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13934.628975 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13934.628975 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13934.628975 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13934.628975 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13934.628975 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked +system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id 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+system.cpu3.icache.overall_misses::total 573 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7430000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7430000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7430000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7430000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7430000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7430000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 18269 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 18269 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 18269 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 18269 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 18269 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 18269 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.031365 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.031365 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.031365 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.031365 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.031365 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.031365 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12966.841187 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 12966.841187 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 12966.841187 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 12966.841187 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 68 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 68 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 68 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 75 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 75 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 75 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 75 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6839000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6839000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6839000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6839000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6839000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6839000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.027455 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.027455 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.027455 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13732.931727 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13732.931727 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13732.931727 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13732.931727 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13732.931727 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13732.931727 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6421000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6421000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6421000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6421000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6421000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6421000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.027259 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.027259 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.027259 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12893.574297 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 422.903421 # Cycle average of tags in use -system.l2c.tags.total_refs 2336 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 538 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.342007 # Average number of references to valid blocks. +system.l2c.tags.tagsinuse 418.779018 # Cycle average of tags in use +system.l2c.tags.total_refs 2347 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.784815 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 289.208824 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.009977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 62.701446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5.295227 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.676960 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 5.511844 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.714328 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.786962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 287.801372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.040061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 61.655177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.312296 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2.346047 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.677363 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1.443236 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.716504 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004413 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000885 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000957 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004392 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000941 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000084 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000022 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006453 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 538 # Occupied blocks per task id +system.l2c.tags.occ_percent::total 0.006390 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 139 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008209 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25512 # Number of tag accesses -system.l2c.tags.data_accesses 25512 # Number of data accesses +system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of 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accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.170000 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.018072 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.216690 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.170000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.018072 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.170000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.018072 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20815.789474 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20785.500000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20850 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.960000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74335.106383 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89884.615385 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 87916.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 79583.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 77603.053435 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67206.611570 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 67388.235294 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 67195.842451 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69826.666667 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 68785.714286 # average ReadSharedReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.259259 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20842.105263 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20880.761905 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20886.318182 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20837.022472 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68617.021277 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69708.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 99041.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71786.259542 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72800 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66273.835920 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69740 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69970.238095 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67206.611570 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72334.319527 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67388.235294 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 86730.769231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 80115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69571.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67206.611570 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72334.319527 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67388.235294 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86730.769231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 80115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69571.428571 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadResp 540 # Transaction distribution -system.membus.trans_dist::UpgradeReq 281 # Transaction distribution -system.membus.trans_dist::UpgradeResp 75 # Transaction distribution -system.membus.trans_dist::ReadExReq 168 # Transaction distribution +system.membus.trans_dist::ReadResp 534 # Transaction distribution +system.membus.trans_dist::UpgradeReq 292 # Transaction distribution +system.membus.trans_dist::UpgradeResp 89 # Transaction distribution +system.membus.trans_dist::ReadExReq 161 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 541 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42944 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 243 # Total snoops (count) -system.membus.snoop_fanout::samples 990 # Request fanout histogram +system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1742 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1742 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 233 # Total snoops (count) +system.membus.snoop_fanout::samples 988 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 990 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 988 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 990 # Request fanout histogram -system.membus.reqLayer0.occupancy 926003 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 988 # Request fanout histogram +system.membus.reqLayer0.occupancy 929005 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3714925 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.4 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadResp 2768 # Transaction distribution +system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.5 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadResp 2782 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 670 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 2109 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 660 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1469 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1144 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1136 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 350 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6560 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::CleanEvict 677 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 295 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 295 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 681 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6585 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 150784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1022 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4941 # Request fanout histogram +system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1026 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4937 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -2828,29 +2851,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 4941 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4937 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4941 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2489462 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4937 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2487961 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 921499 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 506002 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 509492 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 751497 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 425967 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 443468 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 748987 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 752993 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 449462 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 440464 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 748992 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 400481 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 407479 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |