diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
| commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
| tree | 81108e7ff1951b652258f53bd5615a617b734ce2 /tests/quick/se/40.m5threads-test-atomic | |
| parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
| download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz | |
update stats for preceeding changes
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic')
9 files changed, 2164 insertions, 2152 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 07b9bbe53..1c2308afb 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -129,10 +129,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -140,7 +140,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -423,10 +423,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -434,7 +434,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -463,7 +463,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -575,10 +575,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -586,7 +586,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -869,10 +869,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -880,7 +880,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1002,10 +1002,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -1013,7 +1013,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1296,10 +1296,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -1307,7 +1307,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1429,10 +1429,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -1440,7 +1440,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1723,10 +1723,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -1734,7 +1734,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1760,22 +1760,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1793,22 +1793,35 @@ master=system.physmem.port slave=system.l2c.mem_side system.system_port [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 63ee30b34..b5c2c149d 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:31 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:40 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -15,54 +15,54 @@ Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 Iteration 4 completed -[Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 Iteration 5 completed +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 6, Thread 3] Got lock [Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 Iteration 6 completed [Iteration 7, Thread 2] Got lock [Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1 Iteration 7 completed -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 Iteration 8 completed [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 @@ -71,12 +71,12 @@ Iteration 8 completed [Iteration 9, Thread 2] Got lock [Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 10, Thread 3] Got lock [Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 113910500 because target called exit() +Exiting @ tick 104830500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index c68736462..13ed71f23 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,86 +1,86 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000109 # Number of seconds simulated -sim_ticks 108678000 # Number of ticks simulated -final_tick 108678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000105 # Number of seconds simulated +sim_ticks 104830500 # Number of ticks simulated +final_tick 104830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97735 # Simulator instruction rate (inst/s) -host_op_rate 97735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9914053 # Simulator tick rate (ticks/s) -host_mem_usage 237564 # Number of bytes of host memory used -host_seconds 10.96 # Real time elapsed on the host -sim_insts 1071369 # Number of instructions simulated -sim_ops 1071369 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory +host_inst_rate 100032 # Simulator instruction rate (inst/s) +host_op_rate 100032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10132772 # Simulator tick rate (ticks/s) +host_mem_usage 236868 # Number of bytes of host memory used +host_seconds 10.35 # Real time elapsed on the host +sim_insts 1034897 # Number of instructions simulated +sim_ops 1034897 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28416 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 86 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 81 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 668 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 212002429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 98934467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50645025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11777913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 3533374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7655643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1177791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7655643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 393382285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212002429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50645025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 3533374 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1177791 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267358619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212002429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 98934467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50645025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11777913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 3533374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7655643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1177791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7655643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 393382285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 669 # Total number of read requests seen +system.physmem.num_reads::total 658 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 217341327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 102565570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49451257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 12210187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1831528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7936621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2442037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7936621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 401715150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 217341327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49451257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1831528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2442037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 271066150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 217341327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 102565570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49451257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 12210187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1831528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7936621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2442037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7936621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401715150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 659 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 993 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 42752 # Total number of bytes read from memory +system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 42112 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 42112 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 72 # Reqs where no action is needed system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 71 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 36 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 29 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 56 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 61 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 53 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 71 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 60 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 5 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 79 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 78 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 44 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -100,14 +100,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 108650000 # Total gap between requests +system.physmem.totGap 104802500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 669 # Categorize read packet sizes +system.physmem.readPktSize::6 659 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,12 +125,12 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 76 # categorize neither packet sizes +system.physmem.neitherpktsize::6 72 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -194,335 +194,335 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3390669 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18414669 # Sum of mem lat for all requests -system.physmem.totBusLat 2676000 # Total cycles spent in databus access -system.physmem.totBankLat 12348000 # Total cycles spent in bank access -system.physmem.avgQLat 5068.26 # Average queueing delay per request -system.physmem.avgBankLat 18457.40 # Average bank access latency per request +system.physmem.totQLat 2987155 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 17761155 # Sum of mem lat for all requests +system.physmem.totBusLat 2636000 # Total cycles spent in databus access +system.physmem.totBankLat 12138000 # Total cycles spent in bank access +system.physmem.avgQLat 4532.86 # Average queueing delay per request +system.physmem.avgBankLat 18418.82 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27525.66 # Average memory access latency -system.physmem.avgRdBW 393.38 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26951.68 # Average memory access latency +system.physmem.avgRdBW 401.72 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 393.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 401.72 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.46 # Data bus utilization in percentage +system.physmem.busUtil 2.51 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 513 # Number of row buffer hits during reads +system.physmem.readRowHits 506 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 162406.58 # Average gap between requests +system.physmem.avgGap 159032.63 # Average gap between requests system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 217357 # number of cpu cycles simulated +system.cpu0.numCycles 209662 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 85486 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 83146 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1297 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 83094 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 80730 # Number of BTB hits +system.cpu0.BPredUnit.lookups 82004 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 79765 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1218 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 79291 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 77227 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 510 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 516 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17254 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 507547 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 85486 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81240 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 166653 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3954 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12694 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 16907 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 12545 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1571 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6105 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 500 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 200686 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.529060 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.210670 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 192893 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.523176 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215866 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34033 16.96% 16.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 82572 41.14% 58.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 593 0.30% 58.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 970 0.48% 58.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 529 0.26% 59.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 78464 39.10% 98.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 697 0.35% 98.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 363 0.18% 98.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2465 1.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33256 17.24% 17.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79042 40.98% 58.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 987 0.51% 59.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 75108 38.94% 98.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 578 0.30% 98.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 200686 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.393298 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.335085 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18097 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14161 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 165636 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 283 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2509 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 504485 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2509 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18775 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 695 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12879 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 165279 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 549 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 501228 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 342771 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 999720 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 999720 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 329211 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13560 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 922 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 944 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3899 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 160553 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 81037 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 78269 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 78067 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 419118 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 416267 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 155 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11107 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10171 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 200686 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.074220 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.084012 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 192893 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391125 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.321370 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14000 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 483730 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12765 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 329027 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 958899 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 958899 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 315995 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3587 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 399521 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10786 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9496 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 192893 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.071205 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.088777 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33200 16.54% 16.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5091 2.54% 19.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 80178 39.95% 59.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 79595 39.66% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1563 0.78% 99.47% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 681 0.34% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 279 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 88 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 11 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 32269 16.73% 16.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4844 2.51% 19.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 76822 39.83% 59.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76327 39.57% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1582 0.82% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 687 0.36% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 200686 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 192893 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 45 20.36% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 64 28.96% 49.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 53 23.66% 49.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 114 50.89% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 175769 42.23% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 160047 38.45% 80.67% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 80451 19.33% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 169105 42.33% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 153283 38.37% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77133 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 416267 # Type of FU issued -system.cpu0.iq.rate 1.915130 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000531 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1033596 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 431231 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 414361 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 399521 # Type of FU issued +system.cpu0.iq.rate 1.905548 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 992323 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 413903 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 397700 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 416488 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 399745 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 77814 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2358 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1433 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2133 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1389 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2509 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 439 # Number of cycles IEW is blocking +system.cpu0.iew.iewSquashCycles 2438 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 389 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 498940 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 337 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 160553 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 81037 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 840 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewDispatchedInsts 478542 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 300 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 153720 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 77689 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 377 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1128 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 415155 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 159727 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1112 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 398429 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 152970 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1092 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 78871 # number of nop insts executed -system.cpu0.iew.exec_refs 240043 # number of memory reference insts executed -system.cpu0.iew.exec_branches 82509 # Number of branches executed -system.cpu0.iew.exec_stores 80316 # Number of stores executed -system.cpu0.iew.exec_rate 1.910014 # Inst execution rate -system.cpu0.iew.wb_sent 414703 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 414361 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 245547 # num instructions producing a value -system.cpu0.iew.wb_consumers 248019 # num instructions consuming a value +system.cpu0.iew.exec_nop 75469 # number of nop insts executed +system.cpu0.iew.exec_refs 229968 # number of memory reference insts executed +system.cpu0.iew.exec_branches 79152 # Number of branches executed +system.cpu0.iew.exec_stores 76998 # Number of stores executed +system.cpu0.iew.exec_rate 1.900340 # Inst execution rate +system.cpu0.iew.wb_sent 398024 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 397700 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 235727 # num instructions producing a value +system.cpu0.iew.wb_consumers 238246 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.906361 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990033 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.896863 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12749 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1297 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 198194 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.452991 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.132633 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 190472 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.448360 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.135276 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33728 17.02% 17.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 82160 41.45% 58.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2430 1.23% 59.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 731 0.37% 60.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 570 0.29% 60.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 77594 39.15% 99.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 452 0.23% 99.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 290 0.15% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32802 17.22% 17.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2340 1.23% 59.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 74330 39.02% 99.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 198194 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 486168 # Number of instructions committed -system.cpu0.commit.committedOps 486168 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 190472 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 466344 # Number of instructions committed +system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 237799 # Number of memory references committed -system.cpu0.commit.loads 158195 # Number of loads committed +system.cpu0.commit.refs 227887 # Number of memory references committed +system.cpu0.commit.loads 151587 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 81491 # Number of branches committed +system.cpu0.commit.branches 78187 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 327542 # Number of committed integer instructions. +system.cpu0.commit.int_insts 314326 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 290 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 695660 # The number of ROB reads -system.cpu0.rob.rob_writes 1000360 # The number of ROB writes -system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 16671 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 407861 # Number of Instructions Simulated -system.cpu0.committedOps 407861 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 407861 # Number of Instructions Simulated -system.cpu0.cpi 0.532919 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.532919 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.876457 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.876457 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 742624 # number of integer regfile reads -system.cpu0.int_regfile_writes 334702 # number of integer regfile writes +system.cpu0.rob.rob_reads 667502 # The number of ROB reads +system.cpu0.rob.rob_writes 959472 # The number of ROB writes +system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 16769 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 391341 # Number of Instructions Simulated +system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated +system.cpu0.cpi 0.535753 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.535753 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.866533 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.866533 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 712669 # number of integer regfile reads +system.cpu0.int_regfile_writes 321346 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 241901 # number of misc regfile reads +system.cpu0.misc_regfile_reads 231752 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 305 # number of replacements -system.cpu0.icache.tagsinuse 247.227558 # Cycle average of tags in use -system.cpu0.icache.total_refs 5357 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 596 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.988255 # Average number of references to valid blocks. +system.cpu0.icache.replacements 297 # number of replacements +system.cpu0.icache.tagsinuse 245.466325 # Cycle average of tags in use +system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 247.227558 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.482866 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.482866 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5357 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5357 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5357 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5357 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5357 # number of overall hits -system.cpu0.icache.overall_hits::total 5357 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 748 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 748 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 748 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 748 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 748 # number of overall misses -system.cpu0.icache.overall_misses::total 748 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25787000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 25787000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 25787000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 25787000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 25787000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 25787000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6105 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6105 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6105 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6105 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6105 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6105 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122523 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.122523 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122523 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.122523 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122523 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.122523 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34474.598930 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 34474.598930 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34474.598930 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 34474.598930 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34474.598930 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 34474.598930 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 245.466325 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.479426 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.479426 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5129 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5129 # number of overall hits +system.cpu0.icache.overall_hits::total 5129 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 742 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 742 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 742 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses +system.cpu0.icache.overall_misses::total 742 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25612000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 25612000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 25612000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 25612000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 25612000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 25612000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5871 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5871 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5871 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126384 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.126384 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126384 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34517.520216 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 34517.520216 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 34517.520216 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 34517.520216 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,106 +531,106 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 151 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 151 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 151 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 151 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 151 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 151 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 597 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 597 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 597 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 597 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 597 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 597 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20662500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20662500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20662500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20662500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20662500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20662500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097789 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097789 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097789 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.097789 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097789 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.097789 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34610.552764 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34610.552764 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34610.552764 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 34610.552764 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34610.552764 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 34610.552764 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 154 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20478500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 20478500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20478500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 20478500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20478500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 20478500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34827.380952 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 144.093465 # Cycle average of tags in use -system.cpu0.dcache.total_refs 160308 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 143.868426 # Cycle average of tags in use +system.cpu0.dcache.total_refs 153554 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 942.988235 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 903.258824 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 144.093465 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.281433 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.281433 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 81376 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 81376 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79021 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 79021 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 143.868426 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.280993 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.280993 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 77923 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77923 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75708 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75708 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 160397 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 160397 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 160397 # number of overall hits -system.cpu0.dcache.overall_hits::total 160397 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 473 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 473 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 541 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 541 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 153631 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153631 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153631 # number of overall hits +system.cpu0.dcache.overall_hits::total 153631 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 550 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1014 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1014 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1014 # number of overall misses -system.cpu0.dcache.overall_misses::total 1014 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11124000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11124000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22939498 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 22939498 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 377000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 377000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34063498 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34063498 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34063498 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34063498 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 81849 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 81849 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 79562 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 79562 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1021 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1021 # number of overall misses +system.cpu0.dcache.overall_misses::total 1021 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22991498 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 22991498 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34076998 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34076998 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34076998 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34076998 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78394 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78394 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 161411 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 161411 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161411 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 161411 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005779 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005779 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006800 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006800 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 154652 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 154652 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154652 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154652 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006008 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006008 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006282 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006282 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006282 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006282 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23517.970402 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23517.970402 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42402.029575 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42402.029575 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18850 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 18850 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33593.193294 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33593.193294 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33593.193294 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33593.193294 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006602 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006602 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006602 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41802.723636 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41802.723636 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33376.099902 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33376.099902 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -641,364 +641,363 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 282 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 282 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 652 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 652 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 652 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 652 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 191 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 384 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 384 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 661 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 661 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 661 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 661 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 194 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 194 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4857000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4857000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5583500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5583500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 337000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 337000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10440500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10440500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10440500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10440500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002334 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002334 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002149 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002149 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5605500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5605500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10499500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10499500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002475 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002475 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002243 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002243 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002243 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002243 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25429.319372 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25429.319372 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32652.046784 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32652.046784 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16850 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16850 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28841.160221 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28841.160221 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28841.160221 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28841.160221 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002328 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33768.072289 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33768.072289 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 181799 # number of cpu cycles simulated +system.cpu1.numCycles 174084 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 59567 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 56529 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1500 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 52860 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 52019 # Number of BTB hits +system.cpu1.BPredUnit.lookups 52904 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 50238 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1268 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 46828 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 46138 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 823 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 659 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 25837 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 338154 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 59567 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 52842 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 115388 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4298 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 25769 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 297398 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52904 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46797 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 103835 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 29305 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6220 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1046 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 17180 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 176992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.910561 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.213171 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 6116 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 169680 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.752699 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.165176 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 61604 34.81% 34.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 57789 32.65% 67.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4656 2.63% 70.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3206 1.81% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 672 0.38% 72.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 43499 24.58% 96.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1205 0.68% 97.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 866 0.49% 98.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3495 1.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 65845 38.81% 38.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52566 30.98% 69.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 36566 21.55% 96.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 176992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.327653 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.860043 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 29997 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 23620 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 110723 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3705 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2727 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 334194 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2727 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 30767 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 10715 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12086 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 107285 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7192 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 331783 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 53 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 234003 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 646246 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 646246 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 218850 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15153 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1340 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9848 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 96301 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 46898 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 45474 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 41683 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 277198 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 277583 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 147 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12330 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11288 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 176992 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.568336 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.306945 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 169680 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.303899 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.708359 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 26240 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 98388 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 293925 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11858 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 94082 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 291891 # Number of instructions processed by rename +system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 205019 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 562522 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 562522 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 192184 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 83196 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 39822 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 39557 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 34785 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 242788 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 244431 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10770 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 169680 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.440541 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 58949 33.31% 33.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 18466 10.43% 43.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 46965 26.54% 70.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 47589 26.89% 97.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3312 1.87% 99.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1274 0.72% 99.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 318 0.18% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 58 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 63213 37.25% 37.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 39930 23.53% 73.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 40650 23.96% 97.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 176992 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 169680 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 20 6.43% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 81 26.05% 32.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 67.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 68 23.05% 28.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 132190 47.62% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 99212 35.74% 83.36% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 46181 16.64% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 118248 48.38% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 87044 35.61% 83.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 39139 16.01% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 277583 # Type of FU issued -system.cpu1.iq.rate 1.526868 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 311 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001120 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 732616 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 294445 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 275571 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 244431 # Type of FU issued +system.cpu1.iq.rate 1.404098 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 658925 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 259421 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 242675 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 277894 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 244726 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 41481 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 34549 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1604 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2727 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 837 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 328541 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 96301 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 46898 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 60 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 289058 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 83196 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 39822 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1175 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 276246 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 95320 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1337 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 243269 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 82226 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1162 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 46466 # number of nop insts executed -system.cpu1.iew.exec_refs 141403 # number of memory reference insts executed -system.cpu1.iew.exec_branches 55896 # Number of branches executed -system.cpu1.iew.exec_stores 46083 # Number of stores executed -system.cpu1.iew.exec_rate 1.519513 # Inst execution rate -system.cpu1.iew.wb_sent 275857 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 275571 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 158251 # num instructions producing a value -system.cpu1.iew.wb_consumers 163120 # num instructions consuming a value +system.cpu1.iew.exec_nop 40452 # number of nop insts executed +system.cpu1.iew.exec_refs 121286 # number of memory reference insts executed +system.cpu1.iew.exec_branches 49717 # Number of branches executed +system.cpu1.iew.exec_stores 39060 # Number of stores executed +system.cpu1.iew.exec_rate 1.397423 # Inst execution rate +system.cpu1.iew.wb_sent 242942 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 242675 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 138073 # num instructions producing a value +system.cpu1.iew.wb_consumers 142763 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.515800 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.970151 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.394011 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.967148 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14237 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4286 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1500 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 168046 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.870327 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.085151 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 161217 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.716302 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.045846 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 57008 33.92% 33.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 53849 32.04% 65.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6186 3.68% 69.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5193 3.09% 72.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1537 0.91% 73.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 41906 24.94% 98.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 558 0.33% 98.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 997 0.59% 99.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 812 0.48% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 62248 38.61% 38.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 47764 29.63% 68.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 35062 21.75% 98.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 168046 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 314301 # Number of instructions committed -system.cpu1.commit.committedOps 314301 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161217 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 276697 # Number of instructions committed +system.cpu1.commit.committedOps 276697 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 138950 # Number of memory references committed -system.cpu1.commit.loads 93656 # Number of loads committed -system.cpu1.commit.membars 3574 # Number of memory barriers committed -system.cpu1.commit.branches 54833 # Number of branches committed +system.cpu1.commit.refs 119191 # Number of memory references committed +system.cpu1.commit.loads 80801 # Number of loads committed +system.cpu1.commit.membars 4532 # Number of memory barriers committed +system.cpu1.commit.branches 48885 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 215906 # Number of committed integer instructions. +system.cpu1.commit.int_insts 190199 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 495185 # The number of ROB reads -system.cpu1.rob.rob_writes 659817 # The number of ROB writes -system.cpu1.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4807 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35556 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 265102 # Number of Instructions Simulated -system.cpu1.committedOps 265102 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 265102 # Number of Instructions Simulated -system.cpu1.cpi 0.685770 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.685770 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.458215 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.458215 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 483798 # number of integer regfile reads -system.cpu1.int_regfile_writes 224930 # number of integer regfile writes +system.cpu1.rob.rob_reads 448868 # The number of ROB reads +system.cpu1.rob.rob_writes 580470 # The number of ROB writes +system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 232489 # Number of Instructions Simulated +system.cpu1.committedOps 232489 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 232489 # Number of Instructions Simulated +system.cpu1.cpi 0.748784 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.748784 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.335499 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.335499 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 422509 # number of integer regfile reads +system.cpu1.int_regfile_writes 197149 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 143054 # number of misc regfile reads +system.cpu1.misc_regfile_reads 122869 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 321 # number of replacements -system.cpu1.icache.tagsinuse 91.372145 # Cycle average of tags in use -system.cpu1.icache.total_refs 16670 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 38.233945 # Average number of references to valid blocks. +system.cpu1.icache.replacements 317 # number of replacements +system.cpu1.icache.tagsinuse 85.783317 # Cycle average of tags in use +system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 91.372145 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.178461 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.178461 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 16670 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16670 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16670 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16670 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16670 # number of overall hits -system.cpu1.icache.overall_hits::total 16670 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 510 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 510 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 510 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 510 # number of overall misses -system.cpu1.icache.overall_misses::total 510 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10781500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10781500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10781500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10781500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10781500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10781500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 17180 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 17180 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 17180 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 17180 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 17180 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 17180 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029686 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029686 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029686 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029686 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029686 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029686 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21140.196078 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21140.196078 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21140.196078 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21140.196078 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21140.196078 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21140.196078 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 85.783317 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.167546 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.167546 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 18178 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 18178 # number of overall hits +system.cpu1.icache.overall_hits::total 18178 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses +system.cpu1.icache.overall_misses::total 482 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9898500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9898500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9898500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9898500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9898500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9898500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 18660 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 18660 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 18660 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025831 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.025831 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025831 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20536.307054 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20536.307054 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20536.307054 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20536.307054 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1007,106 +1006,106 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 74 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 74 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 74 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8808000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8808000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8808000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8808000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8808000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8808000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.025378 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.025378 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.025378 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.025378 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.025378 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.025378 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20201.834862 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20201.834862 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20201.834862 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 20201.834862 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20201.834862 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 20201.834862 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 57 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 57 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 57 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 57 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8055000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8055000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8055000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8055000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8055000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8055000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022776 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022776 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022776 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18952.941176 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.445610 # Cycle average of tags in use -system.cpu1.dcache.total_refs 51579 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1778.586207 # Average number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.224773 # Cycle average of tags in use +system.cpu1.dcache.total_refs 44406 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1585.928571 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.445610 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.053605 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.053605 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 53407 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 53407 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 45083 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 45083 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 98490 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 98490 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 98490 # number of overall hits -system.cpu1.dcache.overall_hits::total 98490 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 415 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 415 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 145 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 145 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 560 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 560 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 560 # number of overall misses -system.cpu1.dcache.overall_misses::total 560 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6026000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6026000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3157000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3157000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 555500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 555500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 9183000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 9183000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 9183000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 9183000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 53822 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 53822 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 45228 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 45228 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 99050 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 99050 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 99050 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 99050 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007711 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.007711 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003206 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003206 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.818182 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005654 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005654 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005654 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005654 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14520.481928 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14520.481928 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21772.413793 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21772.413793 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 10287.037037 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 10287.037037 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16398.214286 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16398.214286 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16398.214286 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16398.214286 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 27.224773 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 47254 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 47254 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 38186 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 38186 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 85440 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 85440 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 85440 # number of overall hits +system.cpu1.dcache.overall_hits::total 85440 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 407 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 407 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 53 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 544 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 544 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 544 # number of overall misses +system.cpu1.dcache.overall_misses::total 544 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6159500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6159500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2649500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2649500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 528500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 528500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8809000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8809000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8809000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8809000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 47661 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 47661 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 38323 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 38323 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 85984 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 85984 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 85984 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 85984 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008539 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008539 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003575 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003575 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.791045 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.791045 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006327 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006327 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006327 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006327 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19339.416058 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19339.416058 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9971.698113 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9971.698113 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16193.014706 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16193.014706 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1115,364 +1114,364 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 257 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 37 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 37 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 294 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 294 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 294 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 294 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1540500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1540500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1377000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1377000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 447500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 447500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2917500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2917500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2917500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2917500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002388 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002388 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.818182 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.818182 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002686 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002686 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002686 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002686 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9750 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9750 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12750 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12750 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8287.037037 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8287.037037 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10968.045113 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10968.045113 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10968.045113 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10968.045113 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 252 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 284 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 284 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 284 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 284 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1383500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1383500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2913500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2913500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2913500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2913500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.791045 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.791045 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003024 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13176.190476 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13176.190476 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 181474 # number of cpu cycles simulated +system.cpu2.numCycles 173759 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 55930 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 52799 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1548 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 49143 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 48122 # Number of BTB hits +system.cpu2.BPredUnit.lookups 43658 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 40905 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1282 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 37514 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 36718 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 28647 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 313051 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 55930 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 48979 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 109339 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4440 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 31939 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 41179 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6238 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 20302 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 180005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.739124 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.167787 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6107 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 172022 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.367924 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.005612 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 70666 39.26% 39.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 55453 30.81% 70.06% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6160 3.42% 73.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3207 1.78% 75.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 684 0.38% 75.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 38160 21.20% 96.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1206 0.67% 97.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 867 0.48% 98.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3602 2.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 83795 48.71% 48.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 732 0.43% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 24119 14.02% 96.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1119 0.65% 97.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 764 0.44% 98.08% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3307 1.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 180005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.308198 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.725046 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 34354 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 28279 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 103112 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5207 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2815 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 308841 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2815 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 35130 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 15148 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12314 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 98150 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 10210 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 306064 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 214486 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 588858 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 588858 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 198873 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15613 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1249 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1373 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 13264 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 87101 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 41559 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 41593 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 36327 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 253620 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6426 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 255375 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 12537 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11608 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 180005 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.418711 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.312032 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 172022 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.251256 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.354249 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 35177 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 231751 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11999 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 158064 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 425055 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 425055 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 145196 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12868 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1106 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 17601 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 61347 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 27349 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 30218 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 22307 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 186544 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11074 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10969 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 172022 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.110277 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.273783 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68069 37.82% 37.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23048 12.80% 50.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 41620 23.12% 73.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 42277 23.49% 97.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3294 1.83% 99.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1277 0.71% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 306 0.17% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 81441 47.34% 47.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3303 1.92% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1178 0.68% 99.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 180005 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172022 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 123049 48.18% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 91506 35.83% 84.02% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 40820 15.98% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 96218 50.38% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 68109 35.66% 86.04% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 26665 13.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 255375 # Type of FU issued -system.cpu2.iq.rate 1.407226 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 299 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001171 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 691125 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 272626 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 253322 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued +system.cpu2.iq.rate 1.099178 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 554402 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 206628 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 189208 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 255674 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 191279 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 36105 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 22028 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2679 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1636 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2518 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1460 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2815 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 752 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 302670 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 87101 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 41559 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 904 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 226591 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 61347 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 27349 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1066 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1214 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1723 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 254008 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 86102 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1367 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 189816 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 42624 # number of nop insts executed -system.cpu2.iew.exec_refs 126828 # number of memory reference insts executed -system.cpu2.iew.exec_branches 52054 # Number of branches executed -system.cpu2.iew.exec_stores 40726 # Number of stores executed -system.cpu2.iew.exec_rate 1.399694 # Inst execution rate -system.cpu2.iew.wb_sent 253605 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 253322 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 143679 # num instructions producing a value -system.cpu2.iew.wb_consumers 148564 # num instructions consuming a value +system.cpu2.iew.exec_nop 31084 # number of nop insts executed +system.cpu2.iew.exec_refs 86812 # number of memory reference insts executed +system.cpu2.iew.exec_branches 40244 # Number of branches executed +system.cpu2.iew.exec_stores 26581 # Number of stores executed +system.cpu2.iew.exec_rate 1.092410 # Inst execution rate +system.cpu2.iew.wb_sent 189478 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 189208 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 103581 # num instructions producing a value +system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.395913 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.967119 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.088911 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14523 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5804 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1548 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 170953 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.685416 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.035354 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 163490 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.308153 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.875243 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 67602 39.54% 39.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 50009 29.25% 68.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6225 3.64% 72.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6684 3.91% 76.35% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1541 0.90% 77.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 36526 21.37% 98.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 553 0.32% 98.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1000 0.58% 99.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 83402 51.01% 51.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1555 0.95% 84.76% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 22612 13.83% 98.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 481 0.29% 98.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1011 0.62% 99.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 815 0.50% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 170953 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 288127 # Number of instructions committed -system.cpu2.commit.committedOps 288127 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 163490 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 213870 # Number of instructions committed +system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 124345 # Number of memory references committed -system.cpu2.commit.loads 84422 # Number of loads committed -system.cpu2.commit.membars 5089 # Number of memory barriers committed -system.cpu2.commit.branches 50979 # Number of branches committed +system.cpu2.commit.refs 84718 # Number of memory references committed +system.cpu2.commit.loads 58829 # Number of loads committed +system.cpu2.commit.membars 7592 # Number of memory barriers committed +system.cpu2.commit.branches 39438 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 197443 # Number of committed integer instructions. +system.cpu2.commit.int_insts 146274 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 813 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 472203 # The number of ROB reads -system.cpu2.rob.rob_writes 608127 # The number of ROB writes -system.cpu2.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1469 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35881 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 241270 # Number of Instructions Simulated -system.cpu2.committedOps 241270 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 241270 # Number of Instructions Simulated -system.cpu2.cpi 0.752161 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.752161 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.329502 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.329502 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 440107 # number of integer regfile reads -system.cpu2.int_regfile_writes 204983 # number of integer regfile writes +system.cpu2.rob.rob_reads 388659 # The number of ROB reads +system.cpu2.rob.rob_writes 455572 # The number of ROB writes +system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1737 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35901 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 176057 # Number of Instructions Simulated +system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated +system.cpu2.cpi 0.986947 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.986947 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.013225 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.013225 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 319017 # number of integer regfile reads +system.cpu2.int_regfile_writes 150022 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 128465 # number of misc regfile reads +system.cpu2.misc_regfile_reads 88362 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 323 # number of replacements -system.cpu2.icache.tagsinuse 83.164978 # Cycle average of tags in use -system.cpu2.icache.total_refs 19795 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 45.194064 # Average number of references to valid blocks. +system.cpu2.icache.replacements 319 # number of replacements +system.cpu2.icache.tagsinuse 80.119670 # Cycle average of tags in use +system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 83.164978 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.162432 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.162432 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 19795 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19795 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19795 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19795 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19795 # number of overall hits -system.cpu2.icache.overall_hits::total 19795 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 507 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 507 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 507 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 507 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 507 # number of overall misses -system.cpu2.icache.overall_misses::total 507 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6587500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6587500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6587500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6587500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6587500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6587500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 20302 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 20302 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 20302 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 20302 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 20302 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 20302 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024973 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024973 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024973 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024973 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024973 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024973 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 12993.096647 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 12993.096647 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 12993.096647 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 12993.096647 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 12993.096647 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 12993.096647 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 80.119670 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 24566 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 24566 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 24566 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 24566 # number of overall hits +system.cpu2.icache.overall_hits::total 24566 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 475 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 475 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses +system.cpu2.icache.overall_misses::total 475 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6356500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6356500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6356500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6356500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6356500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6356500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 25041 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 25041 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 25041 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018969 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.018969 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018969 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13382.105263 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13382.105263 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13382.105263 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13382.105263 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1481,106 +1480,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 69 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 69 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 69 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5265000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5265000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5265000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5265000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5265000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5265000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021574 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021574 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021574 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021574 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021574 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021574 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12020.547945 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12020.547945 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12020.547945 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12020.547945 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12020.547945 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12020.547945 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 429 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 429 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 429 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 429 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5130000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5130000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5130000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5130000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5130000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017132 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.017132 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.017132 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11958.041958 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 24.743159 # Cycle average of tags in use -system.cpu2.dcache.total_refs 46094 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1646.214286 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 24.750979 # Cycle average of tags in use +system.cpu2.dcache.total_refs 32016 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1104 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.743159 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048326 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048326 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 49553 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 49553 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 39712 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 39712 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 89265 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 89265 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 89265 # number of overall hits -system.cpu2.dcache.overall_hits::total 89265 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 426 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 426 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 142 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 142 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 568 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 568 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 568 # number of overall misses -system.cpu2.dcache.overall_misses::total 568 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5684000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5684000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2389500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2389500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 598500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 598500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8073500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8073500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8073500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8073500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 49979 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 49979 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 39854 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 39854 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 89833 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 89833 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 89833 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 89833 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008524 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.008524 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003563 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003563 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.840580 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.840580 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006323 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.006323 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006323 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.006323 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13342.723005 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 13342.723005 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 16827.464789 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 16827.464789 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10318.965517 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 10318.965517 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14213.908451 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14213.908451 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14213.908451 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14213.908451 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 24.750979 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.048342 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.048342 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 37788 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 37788 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 25681 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 25681 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 63469 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 63469 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 63469 # number of overall hits +system.cpu2.dcache.overall_hits::total 63469 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 397 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 397 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 530 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 530 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 530 # number of overall misses +system.cpu2.dcache.overall_misses::total 530 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5135500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5135500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2343500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2343500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 565000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 565000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 7479000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 7479000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 7479000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 7479000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 38185 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 38185 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 25814 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 25814 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 75 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 75 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 63999 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 63999 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 63999 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 63999 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010397 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010397 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005152 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.005152 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.786667 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.786667 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008281 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12935.768262 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 12935.768262 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17620.300752 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 17620.300752 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14111.320755 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14111.320755 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1589,364 +1588,364 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 266 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 301 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 301 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 107 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1316000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1316000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1150500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1150500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 482500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 482500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2466500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2466500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2466500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2466500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003201 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003201 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002685 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002685 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.840580 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.840580 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002972 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.002972 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002972 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.002972 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8225 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8225 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 10752.336449 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 10752.336449 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8318.965517 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8318.965517 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9237.827715 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9237.827715 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9237.827715 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9237.827715 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 227 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 32 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 259 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 259 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 259 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1409000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1409000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1142500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1142500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2551500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2551500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2551500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2551500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003913 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.786667 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.786667 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8288.235294 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8288.235294 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11311.881188 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11311.881188 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 181164 # number of cpu cycles simulated +system.cpu3.numCycles 173449 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 41552 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 38392 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1515 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 34829 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 33780 # Number of BTB hits +system.cpu3.BPredUnit.lookups 53688 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 50962 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1276 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 47521 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 46771 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 860 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 661 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 36927 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 218203 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 41552 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 34640 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 84802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4380 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 47727 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 301358 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 53688 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 47432 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 105431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6229 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 974 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 28719 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 179453 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.215934 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 1.926514 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6125 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 172027 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.751806 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.162661 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 94651 52.74% 52.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 45326 25.26% 78.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10365 5.78% 83.78% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3238 1.80% 85.58% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 710 0.40% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 19490 10.86% 96.84% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1177 0.66% 97.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 887 0.49% 97.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3609 2.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 66596 38.71% 38.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 53420 31.05% 69.77% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 37059 21.54% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 179453 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.229361 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.204450 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 46454 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 40187 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 74815 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 8979 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2789 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 213927 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2789 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 47212 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 26606 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12751 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 66126 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 17740 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 211407 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 144414 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 382760 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 382760 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 129180 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15234 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1257 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1396 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 20650 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 54196 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 23010 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 27226 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 17768 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 169289 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 10641 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 175038 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12721 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11252 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 865 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 179453 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.975397 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.233089 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 172027 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.309532 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.737444 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 99738 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 297869 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 95158 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 295495 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 206972 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 568769 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 568769 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 194051 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 84321 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 40263 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 40233 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 35230 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 245462 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 247263 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10948 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10583 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 172027 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.437350 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.311410 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 92486 51.54% 51.54% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 34868 19.43% 70.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 23272 12.97% 83.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 23945 13.34% 97.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3213 1.79% 99.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1245 0.69% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 315 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 63993 37.20% 37.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 40281 23.42% 73.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 41063 23.87% 97.14% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 179453 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 172027 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 20 6.92% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 59 20.42% 27.34% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 72.66% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 90201 51.53% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 62467 35.69% 87.22% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 22370 12.78% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 119304 48.25% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 88373 35.74% 83.99% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 39586 16.01% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 175038 # Type of FU issued -system.cpu3.iq.rate 0.966185 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001651 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 529859 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 192688 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 173081 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 247263 # Type of FU issued +system.cpu3.iq.rate 1.425566 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 666924 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 262516 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 245480 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 175327 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 247550 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 17671 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 34961 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1490 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2789 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 857 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 208183 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 54196 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 23010 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1178 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 292666 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 84321 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 40263 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 501 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1172 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1673 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 173760 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 53123 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1278 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 246084 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 83306 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 28253 # number of nop insts executed -system.cpu3.iew.exec_refs 75420 # number of memory reference insts executed -system.cpu3.iew.exec_branches 37599 # Number of branches executed -system.cpu3.iew.exec_stores 22297 # Number of stores executed -system.cpu3.iew.exec_rate 0.959131 # Inst execution rate -system.cpu3.iew.wb_sent 173368 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 173081 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 92251 # num instructions producing a value -system.cpu3.iew.wb_consumers 97140 # num instructions consuming a value +system.cpu3.iew.exec_nop 41143 # number of nop insts executed +system.cpu3.iew.exec_refs 122808 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50377 # Number of branches executed +system.cpu3.iew.exec_stores 39502 # Number of stores executed +system.cpu3.iew.exec_rate 1.418769 # Inst execution rate +system.cpu3.iew.wb_sent 245746 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 245480 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 139608 # num instructions producing a value +system.cpu3.iew.wb_consumers 144273 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.955383 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.949671 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.415286 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.967665 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14656 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 9776 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1515 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 170436 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.135365 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.770418 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 163516 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.713105 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.043722 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 95921 56.28% 56.28% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 35624 20.90% 77.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6200 3.64% 80.82% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 10664 6.26% 87.08% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1534 0.90% 87.98% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 18221 10.69% 98.67% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 461 0.27% 98.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1004 0.59% 99.53% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 807 0.47% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 63247 38.68% 38.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48404 29.60% 68.28% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 35437 21.67% 98.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 170436 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 193507 # Number of instructions committed -system.cpu3.commit.committedOps 193507 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 163516 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 280120 # Number of instructions committed +system.cpu3.commit.committedOps 280120 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 73074 # Number of memory references committed -system.cpu3.commit.loads 51554 # Number of loads committed -system.cpu3.commit.membars 9056 # Number of memory barriers committed -system.cpu3.commit.branches 36531 # Number of branches committed +system.cpu3.commit.refs 120652 # Number of memory references committed +system.cpu3.commit.loads 81858 # Number of loads committed +system.cpu3.commit.membars 4779 # Number of memory barriers committed +system.cpu3.commit.branches 49540 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 131724 # Number of committed integer instructions. +system.cpu3.commit.int_insts 192312 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 807 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 377205 # The number of ROB reads -system.cpu3.rob.rob_writes 419128 # The number of ROB writes -system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1711 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 36191 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 157136 # Number of Instructions Simulated -system.cpu3.committedOps 157136 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 157136 # Number of Instructions Simulated -system.cpu3.cpi 1.152912 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.152912 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.867369 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.867369 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 286066 # number of integer regfile reads -system.cpu3.int_regfile_writes 135262 # number of integer regfile writes +system.cpu3.rob.rob_reads 454763 # The number of ROB reads +system.cpu3.rob.rob_writes 587684 # The number of ROB writes +system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1422 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 36211 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 235010 # Number of Instructions Simulated +system.cpu3.committedOps 235010 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 235010 # Number of Instructions Simulated +system.cpu3.cpi 0.738049 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.738049 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.354923 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.354923 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 427031 # number of integer regfile reads +system.cpu3.int_regfile_writes 198982 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 77098 # number of misc regfile reads +system.cpu3.misc_regfile_reads 124365 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 322 # number of replacements -system.cpu3.icache.tagsinuse 86.042865 # Cycle average of tags in use -system.cpu3.icache.total_refs 28227 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 64.740826 # Average number of references to valid blocks. +system.cpu3.icache.replacements 318 # number of replacements +system.cpu3.icache.tagsinuse 83.493816 # Cycle average of tags in use +system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 86.042865 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.168052 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.168052 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 28227 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 28227 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 28227 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 28227 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 28227 # number of overall hits -system.cpu3.icache.overall_hits::total 28227 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 492 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 492 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 492 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 492 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 492 # number of overall misses -system.cpu3.icache.overall_misses::total 492 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6235000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6235000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6235000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6235000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6235000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6235000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 28719 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 28719 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 28719 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 28719 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 28719 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 28719 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.017132 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.017132 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.017132 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.017132 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.017132 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.017132 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12672.764228 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 12672.764228 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12672.764228 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 12672.764228 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12672.764228 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 12672.764228 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 83.493816 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 18731 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 18731 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 18731 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 18731 # number of overall hits +system.cpu3.icache.overall_hits::total 18731 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 474 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 474 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 474 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 474 # number of overall misses +system.cpu3.icache.overall_misses::total 474 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6191000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6191000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6191000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6191000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6191000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6191000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 19205 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 19205 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 19205 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024681 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.024681 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024681 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13061.181435 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13061.181435 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13061.181435 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13061.181435 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1955,106 +1954,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 56 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 56 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 56 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 56 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 436 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 436 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 436 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4972000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4972000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4972000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4972000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4972000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4972000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.015182 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.015182 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.015182 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.015182 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.015182 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.015182 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11403.669725 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11403.669725 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11403.669725 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11403.669725 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11403.669725 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11403.669725 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 428 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 428 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 428 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4970500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4970500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4970500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4970500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4970500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4970500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022286 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.022286 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.022286 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11613.317757 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 25.903799 # Cycle average of tags in use -system.cpu3.dcache.total_refs 27667 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 25.854093 # Cycle average of tags in use +system.cpu3.dcache.total_refs 44811 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 988.107143 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1600.392857 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.903799 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050593 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050593 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 35065 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 35065 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 21307 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 21307 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 17 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 17 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 56372 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 56372 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 56372 # number of overall hits -system.cpu3.dcache.overall_hits::total 56372 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 369 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 369 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 508 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 508 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 508 # number of overall misses -system.cpu3.dcache.overall_misses::total 508 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4880000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4880000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2424000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2424000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 623500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 623500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7304000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7304000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7304000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7304000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 35434 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 35434 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 21446 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 21446 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 74 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 56880 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 56880 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 56880 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 56880 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010414 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010414 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006481 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.006481 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.770270 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.770270 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008931 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008931 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008931 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008931 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13224.932249 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 13224.932249 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17438.848921 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 17438.848921 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10938.596491 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 10938.596491 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14377.952756 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 14377.952756 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14377.952756 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 14377.952756 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 25.854093 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.050496 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.050496 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 47901 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 47901 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 38585 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 38585 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 86486 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 86486 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 86486 # number of overall hits +system.cpu3.dcache.overall_hits::total 86486 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 426 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 426 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 142 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 142 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 568 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 568 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 568 # number of overall misses +system.cpu3.dcache.overall_misses::total 568 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5342000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 5342000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2332500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2332500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 555000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 555000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7674500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7674500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7674500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7674500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 48327 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 48327 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 38727 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 38727 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 87054 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 87054 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 87054 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 87054 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008815 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.008815 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003667 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003667 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006525 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006525 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12539.906103 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12539.906103 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16426.056338 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16426.056338 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9910.714286 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9910.714286 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 13511.443662 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 13511.443662 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2063,288 +2062,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 204 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 238 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 238 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 238 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 165 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1399500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1399500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1252500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1252500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 509500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 509500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2652000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2652000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2652000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2652000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004657 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004657 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004896 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004896 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.770270 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.770270 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004747 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004747 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004747 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004747 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8481.818182 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8481.818182 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 11928.571429 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 11928.571429 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 8938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 8938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9822.222222 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9822.222222 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9822.222222 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9822.222222 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 273 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 273 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 306 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 306 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 153 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1265000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1265000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1159500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1159500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 443000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 443000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2424500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2424500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2424500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2424500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003166 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002815 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002815 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003010 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003010 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8267.973856 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8267.973856 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10637.614679 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10637.614679 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7910.714286 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7910.714286 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9253.816794 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9253.816794 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9253.816794 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9253.816794 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 434.763271 # Cycle average of tags in use -system.l2c.total_refs 1477 # Total number of references to valid blocks. -system.l2c.sampled_refs 535 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.760748 # Average number of references to valid blocks. +system.l2c.tagsinuse 425.296596 # Cycle average of tags in use +system.l2c.total_refs 1448 # Total number of references to valid blocks. +system.l2c.sampled_refs 525 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.758095 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.835045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 293.557210 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.439095 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 69.391444 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.684600 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 3.455152 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.725294 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.907046 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.768385 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.828895 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.891501 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.268437 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 63.508816 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.639642 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2.310248 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.728233 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.354110 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.766714 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004479 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000907 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001059 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000053 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000904 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000969 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000035 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000036 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006634 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 236 # number of ReadReq hits +system.l2c.occ_percent::total 0.006490 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 348 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 428 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 421 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 433 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 424 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1477 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1448 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 236 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 348 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 342 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 428 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 421 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 433 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1477 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 236 # number of overall hits +system.l2c.demand_hits::total 1448 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 229 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 348 # number of overall hits +system.l2c.overall_hits::cpu1.inst 342 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 428 # number of overall hits +system.l2c.overall_hits::cpu2.inst 421 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 433 # number of overall hits +system.l2c.overall_hits::cpu3.inst 424 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1477 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses +system.l2c.overall_hits::total 1448 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 88 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 545 # number of ReadReq misses +system.l2c.ReadReq_misses::total 537 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 19 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 88 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 676 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 361 # number of overall misses +system.l2c.demand_misses::total 668 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 359 # number of overall misses system.l2c.overall_misses::cpu0.data 168 # number of overall misses -system.l2c.overall_misses::cpu1.inst 88 # number of overall misses +system.l2c.overall_misses::cpu1.inst 83 # number of overall misses system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 10 # number of overall misses +system.l2c.overall_misses::cpu2.inst 8 # number of overall misses system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 3 # number of overall misses +system.l2c.overall_misses::cpu3.inst 4 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 676 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 17680000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 4074500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4823500 # number of ReadReq miss cycles +system.l2c.overall_misses::total 668 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 17565000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 4069000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4146500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 381000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 461000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 396000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 144000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 233000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 27701000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5009000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 896000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 701499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 662000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7268499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 17680000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 9083500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4823500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1277000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 461000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 769999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 144000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 730500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 34969499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 17680000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 9083500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4823500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1277000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 461000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 769999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 144000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 730500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 34969499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 597 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::total 26927500 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5000500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 881000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 699500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 661500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7242500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 17565000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 9069500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4146500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1262000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 396000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 768000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 233000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 730000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 34170000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 17565000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 9069500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4146500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1262000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 396000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 768000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 233000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 730000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 34170000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 436 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 438 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 429 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 436 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 428 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 22 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 597 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 436 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 438 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 429 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 436 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 428 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2153 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 597 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2116 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 436 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 438 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 429 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 436 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 428 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2153 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.604690 # miss rate for ReadReq accesses +system.l2c.overall_accesses::total 2116 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.201835 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.195294 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.022831 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.018648 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.006881 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.009346 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.269535 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.270529 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.863636 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.960000 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.604690 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.201835 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.195294 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.022831 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.018648 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.006881 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.009346 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.313980 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.604690 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.315690 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.201835 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.195294 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.022831 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.018648 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.006881 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.009346 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.313980 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48975.069252 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 55060.810811 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54812.500000 # average ReadReq miss latency +system.l2c.overall_miss_rate::total 0.315690 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48927.576602 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 54986.486486 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49957.831325 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 54428.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 46100 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 48000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 58250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 50827.522936 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53287.234043 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68923.076923 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58458.250000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55166.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 55484.725191 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 48975.069252 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 54068.452381 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 54812.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 63850 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 46100 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 59230.692308 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 48000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 56192.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51730.028107 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 48975.069252 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 54068.452381 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 54812.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 63850 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 46100 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 59230.692308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 48000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 56192.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51730.028107 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::total 50144.320298 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53196.808511 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67769.230769 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58291.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55125 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55286.259542 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 48927.576602 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 53985.119048 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 49957.831325 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 63100 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 49500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 59076.923077 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 58250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 56153.846154 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51152.694611 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 48927.576602 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 53985.119048 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 49957.831325 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 63100 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 49500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 59076.923077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 58250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 56153.846154 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51152.694611 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2353,166 +2352,166 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 361 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 86 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 81 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 6 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 538 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 528 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 19 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 86 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 81 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 6 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 669 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 659 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 86 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 81 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 6 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 669 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13144576 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3156576 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3651132 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::total 659 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13017059 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3150576 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3026126 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 293010 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 201008 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 103002 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 56004 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 181507 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 20614310 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 194011 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 181016 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 190518 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 204511 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 770056 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3841108 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 734514 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 550017 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 19883284 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 193013 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 181515 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 153009 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200519 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 728056 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3829610 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 719513 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 549018 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511018 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5636657 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 13144576 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6997684 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3651132 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1027524 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 201008 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 606019 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 56004 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5609159 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 13017059 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6980186 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3026126 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1012523 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 103002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 605020 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 181507 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 567020 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 26250967 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 13144576 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6997684 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3651132 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1027524 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 201008 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 606019 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 56004 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 25492443 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 13017059 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6980186 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3026126 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1012523 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 103002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 605020 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 181507 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 567020 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 26250967 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.604690 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::total 25492443 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.197248 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.013699 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.004587 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.266073 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.265995 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.863636 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.960000 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.604690 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.197248 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013699 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004587 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.310729 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.604690 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::total 0.311437 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.197248 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013699 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004587 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.310729 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36411.567867 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42656.432432 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42455.023256 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.311437 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42575.351351 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 33501.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 34334 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 38316.561338 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10211.105263 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10056.444444 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10027.263158 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10225.550000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10132.315789 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40862.851064 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56501.076923 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45834.750000 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 37657.734848 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.578947 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10084.166667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10200.600000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10025.950000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.888889 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40740.531915 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55347.153846 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45751.500000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42584.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 43027.916031 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36411.567867 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41652.880952 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42455.023256 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51376.200000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 33501.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46616.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28002 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42818.007634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39239.113602 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36411.567867 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41652.880952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42455.023256 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51376.200000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 33501.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46616.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39239.113602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index 980beb479..6cfde7057 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -65,10 +65,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -76,11 +76,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -96,10 +96,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -107,11 +107,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -136,7 +136,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -184,10 +184,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -195,11 +195,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -215,10 +215,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -226,11 +226,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -284,10 +284,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -295,11 +295,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -315,10 +315,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -326,11 +326,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -384,10 +384,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -395,11 +395,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -415,10 +415,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -426,11 +426,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -452,22 +452,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -487,7 +487,7 @@ slave=system.l2c.mem_side system.system_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -500,7 +500,7 @@ port=system.membus.master[0] [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 77c22c008..c63257902 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:36 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:52 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 686f019bc..bb7e4e4f9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163854 # Simulator instruction rate (inst/s) -host_op_rate 163852 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21217098 # Simulator tick rate (ticks/s) -host_mem_usage 1151472 # Number of bytes of host memory used -host_seconds 4.13 # Real time elapsed on the host +host_inst_rate 174734 # Simulator instruction rate (inst/s) +host_op_rate 174733 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22625965 # Simulator tick rate (ticks/s) +host_mem_usage 1150028 # Number of bytes of host memory used +host_seconds 3.88 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index c224b90ec..244af9704 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -61,10 +61,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -72,11 +72,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -92,10 +92,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -103,11 +103,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -132,7 +132,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -176,10 +176,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -187,11 +187,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -207,10 +207,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -218,11 +218,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -272,10 +272,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -283,11 +283,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -303,10 +303,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -314,11 +314,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -368,10 +368,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -379,11 +379,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -399,10 +399,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -410,11 +410,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -436,22 +436,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -471,7 +471,7 @@ slave=system.l2c.mem_side system.system_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -484,7 +484,7 @@ port=system.membus.master[0] [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index d61ea072e..3b151bc02 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,82 +1,82 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:39 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:46:01 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 Iteration 2 completed +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 Iteration 4 completed +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 Iteration 5 completed -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 Iteration 6 completed +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 Iteration 9 completed -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 3] Got lock [Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 268898000 because target called exit() +Exiting @ tick 261623500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index df50fe29d..6b9b27a43 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000262 # Nu sim_ticks 261623500 # Number of ticks simulated final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 776063 # Simulator instruction rate (inst/s) -host_op_rate 776047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 307506962 # Simulator tick rate (ticks/s) -host_mem_usage 231300 # Number of bytes of host memory used -host_seconds 0.85 # Real time elapsed on the host +host_inst_rate 114971 # Simulator instruction rate (inst/s) +host_op_rate 114971 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45557694 # Simulator tick rate (ticks/s) +host_mem_usage 232524 # Number of bytes of host memory used +host_seconds 5.74 # Real time elapsed on the host sim_insts 660239 # Number of instructions simulated sim_ops 660239 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory |